1724ba675SRob Herring/* 2724ba675SRob Herring * BSD LICENSE 3724ba675SRob Herring * 4724ba675SRob Herring * Copyright(c) 2017 Broadcom. All rights reserved. 5724ba675SRob Herring * 6724ba675SRob Herring * Redistribution and use in source and binary forms, with or without 7724ba675SRob Herring * modification, are permitted provided that the following conditions 8724ba675SRob Herring * are met: 9724ba675SRob Herring * 10724ba675SRob Herring * * Redistributions of source code must retain the above copyright 11724ba675SRob Herring * notice, this list of conditions and the following disclaimer. 12724ba675SRob Herring * * Redistributions in binary form must reproduce the above copyright 13724ba675SRob Herring * notice, this list of conditions and the following disclaimer in 14724ba675SRob Herring * the documentation and/or other materials provided with the 15724ba675SRob Herring * distribution. 16724ba675SRob Herring * * Neither the name of Broadcom Corporation nor the names of its 17724ba675SRob Herring * contributors may be used to endorse or promote products derived 18724ba675SRob Herring * from this software without specific prior written permission. 19724ba675SRob Herring * 20724ba675SRob Herring * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21724ba675SRob Herring * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22724ba675SRob Herring * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23724ba675SRob Herring * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24724ba675SRob Herring * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25724ba675SRob Herring * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26724ba675SRob Herring * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27724ba675SRob Herring * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28724ba675SRob Herring * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29724ba675SRob Herring * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30724ba675SRob Herring * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31724ba675SRob Herring */ 32724ba675SRob Herring 33724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 34724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq.h> 35724ba675SRob Herring 36724ba675SRob Herring/ { 37724ba675SRob Herring compatible = "brcm,hr2"; 38724ba675SRob Herring model = "Broadcom Hurricane 2 SoC"; 39724ba675SRob Herring interrupt-parent = <&gic>; 40724ba675SRob Herring #address-cells = <1>; 41724ba675SRob Herring #size-cells = <1>; 42724ba675SRob Herring 43724ba675SRob Herring cpus { 44724ba675SRob Herring #address-cells = <1>; 45724ba675SRob Herring #size-cells = <0>; 46724ba675SRob Herring 47724ba675SRob Herring cpu0: cpu@0 { 48724ba675SRob Herring device_type = "cpu"; 49724ba675SRob Herring compatible = "arm,cortex-a9"; 50724ba675SRob Herring next-level-cache = <&L2>; 51724ba675SRob Herring reg = <0x0>; 52724ba675SRob Herring }; 53724ba675SRob Herring }; 54724ba675SRob Herring 55724ba675SRob Herring pmu { 56724ba675SRob Herring compatible = "arm,cortex-a9-pmu"; 57753a1baaSKrzysztof Kozlowski interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 58753a1baaSKrzysztof Kozlowski <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 59724ba675SRob Herring interrupt-affinity = <&cpu0>; 60724ba675SRob Herring }; 61724ba675SRob Herring 62724ba675SRob Herring mpcore@19000000 { 63724ba675SRob Herring compatible = "simple-bus"; 64724ba675SRob Herring ranges = <0x00000000 0x19000000 0x00023000>; 65724ba675SRob Herring #address-cells = <1>; 66724ba675SRob Herring #size-cells = <1>; 67724ba675SRob Herring 68724ba675SRob Herring a9pll: arm_clk@0 { 69724ba675SRob Herring #clock-cells = <0>; 70724ba675SRob Herring compatible = "brcm,hr2-armpll"; 71724ba675SRob Herring clocks = <&osc>; 72724ba675SRob Herring reg = <0x0 0x1000>; 73724ba675SRob Herring }; 74724ba675SRob Herring 75724ba675SRob Herring timer@20200 { 76724ba675SRob Herring compatible = "arm,cortex-a9-global-timer"; 77724ba675SRob Herring reg = <0x20200 0x100>; 78724ba675SRob Herring interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 79724ba675SRob Herring clocks = <&periph_clk>; 80724ba675SRob Herring }; 81724ba675SRob Herring 82724ba675SRob Herring twd-timer@20600 { 83724ba675SRob Herring compatible = "arm,cortex-a9-twd-timer"; 84724ba675SRob Herring reg = <0x20600 0x20>; 85724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 86724ba675SRob Herring IRQ_TYPE_EDGE_RISING)>; 87724ba675SRob Herring clocks = <&periph_clk>; 88724ba675SRob Herring }; 89724ba675SRob Herring 90724ba675SRob Herring twd-watchdog@20620 { 91724ba675SRob Herring compatible = "arm,cortex-a9-twd-wdt"; 92724ba675SRob Herring reg = <0x20620 0x20>; 93724ba675SRob Herring interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 94724ba675SRob Herring IRQ_TYPE_EDGE_RISING)>; 95724ba675SRob Herring clocks = <&periph_clk>; 96724ba675SRob Herring }; 97724ba675SRob Herring 98724ba675SRob Herring gic: interrupt-controller@21000 { 99724ba675SRob Herring compatible = "arm,cortex-a9-gic"; 100724ba675SRob Herring #interrupt-cells = <3>; 101724ba675SRob Herring #address-cells = <0>; 102724ba675SRob Herring interrupt-controller; 103724ba675SRob Herring reg = <0x21000 0x1000>, 104724ba675SRob Herring <0x20100 0x100>; 105724ba675SRob Herring }; 106724ba675SRob Herring 107724ba675SRob Herring L2: cache-controller@22000 { 108724ba675SRob Herring compatible = "arm,pl310-cache"; 109724ba675SRob Herring reg = <0x22000 0x1000>; 110724ba675SRob Herring cache-unified; 111724ba675SRob Herring cache-level = <2>; 112724ba675SRob Herring }; 113724ba675SRob Herring }; 114724ba675SRob Herring 115724ba675SRob Herring clocks { 116724ba675SRob Herring #address-cells = <1>; 117724ba675SRob Herring #size-cells = <1>; 118724ba675SRob Herring ranges; 119724ba675SRob Herring 120724ba675SRob Herring osc: oscillator { 121724ba675SRob Herring #clock-cells = <0>; 122724ba675SRob Herring compatible = "fixed-clock"; 123724ba675SRob Herring clock-frequency = <25000000>; 124724ba675SRob Herring }; 125724ba675SRob Herring 126724ba675SRob Herring periph_clk: periph_clk { 127724ba675SRob Herring #clock-cells = <0>; 128724ba675SRob Herring compatible = "fixed-factor-clock"; 129724ba675SRob Herring clocks = <&a9pll>; 130724ba675SRob Herring clock-div = <2>; 131724ba675SRob Herring clock-mult = <1>; 132724ba675SRob Herring }; 133724ba675SRob Herring }; 134724ba675SRob Herring 135724ba675SRob Herring axi@18000000 { 136724ba675SRob Herring compatible = "simple-bus"; 137724ba675SRob Herring ranges = <0x00000000 0x18000000 0x0011c40c>; 138724ba675SRob Herring #address-cells = <1>; 139724ba675SRob Herring #size-cells = <1>; 140724ba675SRob Herring 141724ba675SRob Herring uart0: serial@300 { 142724ba675SRob Herring compatible = "ns16550a"; 143724ba675SRob Herring reg = <0x0300 0x100>; 144724ba675SRob Herring interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 145724ba675SRob Herring clocks = <&osc>; 146724ba675SRob Herring status = "disabled"; 147724ba675SRob Herring }; 148724ba675SRob Herring 149724ba675SRob Herring uart1: serial@400 { 150724ba675SRob Herring compatible = "ns16550a"; 151724ba675SRob Herring reg = <0x0400 0x100>; 152724ba675SRob Herring interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 153724ba675SRob Herring clocks = <&osc>; 154724ba675SRob Herring status = "disabled"; 155724ba675SRob Herring }; 156724ba675SRob Herring 157724ba675SRob Herring dma@20000 { 158724ba675SRob Herring compatible = "arm,pl330", "arm,primecell"; 159724ba675SRob Herring reg = <0x20000 0x1000>; 160724ba675SRob Herring interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 161724ba675SRob Herring <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 162724ba675SRob Herring <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 163724ba675SRob Herring <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 164724ba675SRob Herring <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 165724ba675SRob Herring <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 166724ba675SRob Herring <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 167724ba675SRob Herring <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 168724ba675SRob Herring <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 169724ba675SRob Herring #dma-cells = <1>; 170724ba675SRob Herring status = "disabled"; 171724ba675SRob Herring }; 172724ba675SRob Herring 173724ba675SRob Herring amac0: ethernet@22000 { 174724ba675SRob Herring compatible = "brcm,nsp-amac"; 175724ba675SRob Herring reg = <0x22000 0x1000>, 176724ba675SRob Herring <0x110000 0x1000>; 177724ba675SRob Herring reg-names = "amac_base", "idm_base"; 178724ba675SRob Herring interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 179724ba675SRob Herring status = "disabled"; 180724ba675SRob Herring }; 181724ba675SRob Herring 182724ba675SRob Herring nand_controller: nand-controller@26000 { 183724ba675SRob Herring compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 184724ba675SRob Herring reg = <0x26000 0x600>, 185724ba675SRob Herring <0x11b408 0x600>, 186724ba675SRob Herring <0x026f00 0x20>; 187724ba675SRob Herring reg-names = "nand", "iproc-idm", "iproc-ext"; 188724ba675SRob Herring interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 189724ba675SRob Herring 190724ba675SRob Herring #address-cells = <1>; 191724ba675SRob Herring #size-cells = <0>; 192724ba675SRob Herring 193724ba675SRob Herring brcm,nand-has-wp; 194724ba675SRob Herring }; 195724ba675SRob Herring 196724ba675SRob Herring gpiob: gpio@30000 { 197724ba675SRob Herring compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio"; 198724ba675SRob Herring reg = <0x30000 0x50>; 199724ba675SRob Herring #gpio-cells = <2>; 200724ba675SRob Herring gpio-controller; 201724ba675SRob Herring ngpios = <4>; 202724ba675SRob Herring interrupt-controller; 203*ab7e3fe1SRob Herring #interrupt-cells = <2>; 204724ba675SRob Herring interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 205724ba675SRob Herring }; 206724ba675SRob Herring 207724ba675SRob Herring pwm: pwm@31000 { 208724ba675SRob Herring compatible = "brcm,iproc-pwm"; 209724ba675SRob Herring reg = <0x31000 0x28>; 210724ba675SRob Herring clocks = <&osc>; 211724ba675SRob Herring #pwm-cells = <3>; 212724ba675SRob Herring status = "disabled"; 213724ba675SRob Herring }; 214724ba675SRob Herring 215724ba675SRob Herring rng: rng@33000 { 216724ba675SRob Herring compatible = "brcm,bcm-nsp-rng"; 217724ba675SRob Herring reg = <0x33000 0x14>; 218724ba675SRob Herring }; 219724ba675SRob Herring 220724ba675SRob Herring qspi: spi@27200 { 221724ba675SRob Herring compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; 222724ba675SRob Herring reg = <0x027200 0x184>, 223724ba675SRob Herring <0x027000 0x124>, 224724ba675SRob Herring <0x11c408 0x004>, 225724ba675SRob Herring <0x0273a0 0x01c>; 226724ba675SRob Herring reg-names = "mspi", "bspi", "intr_regs", 227724ba675SRob Herring "intr_status_reg"; 228724ba675SRob Herring interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 229724ba675SRob Herring <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 230724ba675SRob Herring <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 231724ba675SRob Herring <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 232724ba675SRob Herring <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 233724ba675SRob Herring <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 234724ba675SRob Herring <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 235724ba675SRob Herring interrupt-names = "spi_lr_fullness_reached", 236724ba675SRob Herring "spi_lr_session_aborted", 237724ba675SRob Herring "spi_lr_impatient", 238724ba675SRob Herring "spi_lr_session_done", 239724ba675SRob Herring "spi_lr_overhead", 240724ba675SRob Herring "mspi_done", 241724ba675SRob Herring "mspi_halted"; 242724ba675SRob Herring num-cs = <2>; 243724ba675SRob Herring #address-cells = <1>; 244724ba675SRob Herring #size-cells = <0>; 245724ba675SRob Herring 246724ba675SRob Herring /* partitions defined in board DTS */ 247724ba675SRob Herring }; 248724ba675SRob Herring 249724ba675SRob Herring ccbtimer0: timer@34000 { 250724ba675SRob Herring compatible = "arm,sp804"; 251724ba675SRob Herring reg = <0x34000 0x1000>; 252724ba675SRob Herring interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 253724ba675SRob Herring <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 254724ba675SRob Herring }; 255724ba675SRob Herring 256724ba675SRob Herring ccbtimer1: timer@35000 { 257724ba675SRob Herring compatible = "arm,sp804"; 258724ba675SRob Herring reg = <0x35000 0x1000>; 259724ba675SRob Herring interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 260724ba675SRob Herring <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 261724ba675SRob Herring }; 262724ba675SRob Herring 263724ba675SRob Herring i2c0: i2c@38000 { 264724ba675SRob Herring compatible = "brcm,iproc-i2c"; 265724ba675SRob Herring reg = <0x38000 0x50>; 266724ba675SRob Herring #address-cells = <1>; 267724ba675SRob Herring #size-cells = <0>; 268724ba675SRob Herring interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 269724ba675SRob Herring clock-frequency = <100000>; 270724ba675SRob Herring }; 271724ba675SRob Herring 272724ba675SRob Herring watchdog: watchdog@39000 { 273724ba675SRob Herring compatible = "arm,sp805", "arm,primecell"; 274724ba675SRob Herring reg = <0x39000 0x1000>; 275724ba675SRob Herring interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 276724ba675SRob Herring }; 277724ba675SRob Herring 278724ba675SRob Herring i2c1: i2c@3b000 { 279724ba675SRob Herring compatible = "brcm,iproc-i2c"; 280724ba675SRob Herring reg = <0x3b000 0x50>; 281724ba675SRob Herring #address-cells = <1>; 282724ba675SRob Herring #size-cells = <0>; 283724ba675SRob Herring interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 284724ba675SRob Herring clock-frequency = <100000>; 285724ba675SRob Herring }; 286724ba675SRob Herring }; 287724ba675SRob Herring 288724ba675SRob Herring pflash: nor@20000000 { 289724ba675SRob Herring compatible = "cfi-flash", "jedec-flash"; 290724ba675SRob Herring reg = <0x20000000 0x04000000>; 291724ba675SRob Herring status = "disabled"; 292724ba675SRob Herring #address-cells = <1>; 293724ba675SRob Herring #size-cells = <1>; 294724ba675SRob Herring 295724ba675SRob Herring /* partitions defined in board DTS */ 296724ba675SRob Herring }; 297724ba675SRob Herring 298724ba675SRob Herring pcie0: pcie@18012000 { 299724ba675SRob Herring compatible = "brcm,iproc-pcie"; 300724ba675SRob Herring reg = <0x18012000 0x1000>; 301724ba675SRob Herring 302724ba675SRob Herring #interrupt-cells = <1>; 303724ba675SRob Herring interrupt-map-mask = <0 0 0 0>; 304724ba675SRob Herring interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 305724ba675SRob Herring 306724ba675SRob Herring linux,pci-domain = <0>; 307724ba675SRob Herring 308724ba675SRob Herring bus-range = <0x00 0xff>; 309724ba675SRob Herring 310724ba675SRob Herring #address-cells = <3>; 311724ba675SRob Herring #size-cells = <2>; 312724ba675SRob Herring device_type = "pci"; 313724ba675SRob Herring 314724ba675SRob Herring /* Note: The HW does not support I/O resources. So, 315724ba675SRob Herring * only the memory resource range is being specified. 316724ba675SRob Herring */ 317724ba675SRob Herring ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; 318724ba675SRob Herring 319724ba675SRob Herring status = "disabled"; 320724ba675SRob Herring 321724ba675SRob Herring msi-parent = <&msi0>; 322724ba675SRob Herring msi0: msi { 323724ba675SRob Herring compatible = "brcm,iproc-msi"; 324724ba675SRob Herring msi-controller; 325724ba675SRob Herring interrupt-parent = <&gic>; 326724ba675SRob Herring interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 327724ba675SRob Herring <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 328724ba675SRob Herring <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 329724ba675SRob Herring <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 330724ba675SRob Herring brcm,pcie-msi-inten; 331724ba675SRob Herring }; 332724ba675SRob Herring }; 333724ba675SRob Herring 334724ba675SRob Herring pcie1: pcie@18013000 { 335724ba675SRob Herring compatible = "brcm,iproc-pcie"; 336724ba675SRob Herring reg = <0x18013000 0x1000>; 337724ba675SRob Herring 338724ba675SRob Herring #interrupt-cells = <1>; 339724ba675SRob Herring interrupt-map-mask = <0 0 0 0>; 340724ba675SRob Herring interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 341724ba675SRob Herring 342724ba675SRob Herring linux,pci-domain = <1>; 343724ba675SRob Herring 344724ba675SRob Herring bus-range = <0x00 0xff>; 345724ba675SRob Herring 346724ba675SRob Herring #address-cells = <3>; 347724ba675SRob Herring #size-cells = <2>; 348724ba675SRob Herring device_type = "pci"; 349724ba675SRob Herring 350724ba675SRob Herring /* Note: The HW does not support I/O resources. So, 351724ba675SRob Herring * only the memory resource range is being specified. 352724ba675SRob Herring */ 353724ba675SRob Herring ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; 354724ba675SRob Herring 355724ba675SRob Herring status = "disabled"; 356724ba675SRob Herring 357724ba675SRob Herring msi-parent = <&msi1>; 358724ba675SRob Herring msi1: msi { 359724ba675SRob Herring compatible = "brcm,iproc-msi"; 360724ba675SRob Herring msi-controller; 361724ba675SRob Herring interrupt-parent = <&gic>; 362724ba675SRob Herring interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 363724ba675SRob Herring <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 364724ba675SRob Herring <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 365724ba675SRob Herring <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 366724ba675SRob Herring brcm,pcie-msi-inten; 367724ba675SRob Herring }; 368724ba675SRob Herring }; 369724ba675SRob Herring}; 370