1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 OR MIT 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2014 Carlo Caione <carlo@caione.org> 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring#include "meson.dtsi" 7*724ba675SRob Herring 8*724ba675SRob Herring/ { 9*724ba675SRob Herring model = "Amlogic Meson6 SoC"; 10*724ba675SRob Herring compatible = "amlogic,meson6"; 11*724ba675SRob Herring 12*724ba675SRob Herring cpus { 13*724ba675SRob Herring #address-cells = <1>; 14*724ba675SRob Herring #size-cells = <0>; 15*724ba675SRob Herring 16*724ba675SRob Herring cpu@200 { 17*724ba675SRob Herring device_type = "cpu"; 18*724ba675SRob Herring compatible = "arm,cortex-a9"; 19*724ba675SRob Herring next-level-cache = <&L2>; 20*724ba675SRob Herring reg = <0x200>; 21*724ba675SRob Herring }; 22*724ba675SRob Herring 23*724ba675SRob Herring cpu@201 { 24*724ba675SRob Herring device_type = "cpu"; 25*724ba675SRob Herring compatible = "arm,cortex-a9"; 26*724ba675SRob Herring next-level-cache = <&L2>; 27*724ba675SRob Herring reg = <0x201>; 28*724ba675SRob Herring }; 29*724ba675SRob Herring }; 30*724ba675SRob Herring 31*724ba675SRob Herring apb2: bus@d0000000 { 32*724ba675SRob Herring compatible = "simple-bus"; 33*724ba675SRob Herring reg = <0xd0000000 0x40000>; 34*724ba675SRob Herring #address-cells = <1>; 35*724ba675SRob Herring #size-cells = <1>; 36*724ba675SRob Herring ranges = <0x0 0xd0000000 0x40000>; 37*724ba675SRob Herring }; 38*724ba675SRob Herring 39*724ba675SRob Herring clk81: clk@0 { 40*724ba675SRob Herring #clock-cells = <0>; 41*724ba675SRob Herring compatible = "fixed-clock"; 42*724ba675SRob Herring clock-frequency = <200000000>; 43*724ba675SRob Herring }; 44*724ba675SRob Herring}; /* end of / */ 45*724ba675SRob Herring 46*724ba675SRob Herring&efuse { 47*724ba675SRob Herring status = "disabled"; 48*724ba675SRob Herring}; 49*724ba675SRob Herring 50*724ba675SRob Herring&timer_abcde { 51*724ba675SRob Herring clocks = <&xtal>, <&clk81>; 52*724ba675SRob Herring clock-names = "xtal", "pclk"; 53*724ba675SRob Herring}; 54*724ba675SRob Herring 55*724ba675SRob Herring&uart_AO { 56*724ba675SRob Herring clocks = <&xtal>, <&clk81>, <&clk81>; 57*724ba675SRob Herring clock-names = "xtal", "pclk", "baud"; 58*724ba675SRob Herring}; 59*724ba675SRob Herring 60*724ba675SRob Herring&uart_A { 61*724ba675SRob Herring clocks = <&xtal>, <&clk81>, <&clk81>; 62*724ba675SRob Herring clock-names = "xtal", "pclk", "baud"; 63*724ba675SRob Herring}; 64*724ba675SRob Herring 65*724ba675SRob Herring&uart_B { 66*724ba675SRob Herring clocks = <&xtal>, <&clk81>, <&clk81>; 67*724ba675SRob Herring clock-names = "xtal", "pclk", "baud"; 68*724ba675SRob Herring}; 69*724ba675SRob Herring 70*724ba675SRob Herring&uart_C { 71*724ba675SRob Herring clocks = <&xtal>, <&clk81>, <&clk81>; 72*724ba675SRob Herring clock-names = "xtal", "pclk", "baud"; 73*724ba675SRob Herring}; 74