1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
4*724ba675SRob Herring */
5*724ba675SRob Herring
6*724ba675SRob Herring#include "sunxi-bananapi-m2-plus.dtsi"
7*724ba675SRob Herring
8*724ba675SRob Herring/ {
9*724ba675SRob Herring	/*
10*724ba675SRob Herring	 * Bananapi M2+ v1.2 uses a GPIO line to change the effective
11*724ba675SRob Herring	 * resistance on the CPU regulator's feedback pin.
12*724ba675SRob Herring	 */
13*724ba675SRob Herring	reg_vdd_cpux: vdd-cpux {
14*724ba675SRob Herring		compatible = "regulator-gpio";
15*724ba675SRob Herring		regulator-name = "vdd-cpux";
16*724ba675SRob Herring		regulator-type = "voltage";
17*724ba675SRob Herring		regulator-boot-on;
18*724ba675SRob Herring		regulator-always-on;
19*724ba675SRob Herring		regulator-min-microvolt = <1108475>;
20*724ba675SRob Herring		regulator-max-microvolt = <1308475>;
21*724ba675SRob Herring		regulator-ramp-delay = <50>; /* 4ms */
22*724ba675SRob Herring		gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
23*724ba675SRob Herring		gpios-states = <0x1>;
24*724ba675SRob Herring		states = <1108475 0>, <1308475 1>;
25*724ba675SRob Herring	};
26*724ba675SRob Herring};
27*724ba675SRob Herring
28*724ba675SRob Herring&cpu0 {
29*724ba675SRob Herring	cpu-supply = <&reg_vdd_cpux>;
30*724ba675SRob Herring};
31*724ba675SRob Herring
32*724ba675SRob Herring&cpu1 {
33*724ba675SRob Herring	cpu-supply = <&reg_vdd_cpux>;
34*724ba675SRob Herring};
35*724ba675SRob Herring
36*724ba675SRob Herring&cpu2 {
37*724ba675SRob Herring	cpu-supply = <&reg_vdd_cpux>;
38*724ba675SRob Herring};
39*724ba675SRob Herring
40*724ba675SRob Herring&cpu3 {
41*724ba675SRob Herring	cpu-supply = <&reg_vdd_cpux>;
42*724ba675SRob Herring};
43