1*724ba675SRob Herring/* 2*724ba675SRob Herring * Copyright 2014 Chen-Yu Tsai 3*724ba675SRob Herring * 4*724ba675SRob Herring * Chen-Yu Tsai <wens@csie.org> 5*724ba675SRob Herring * 6*724ba675SRob Herring * This file is dual-licensed: you can use it either under the terms 7*724ba675SRob Herring * of the GPL or the X11 license, at your option. Note that this dual 8*724ba675SRob Herring * licensing only applies to this file, and not this project as a 9*724ba675SRob Herring * whole. 10*724ba675SRob Herring * 11*724ba675SRob Herring * a) This file is free software; you can redistribute it and/or 12*724ba675SRob Herring * modify it under the terms of the GNU General Public License as 13*724ba675SRob Herring * published by the Free Software Foundation; either version 2 of the 14*724ba675SRob Herring * License, or (at your option) any later version. 15*724ba675SRob Herring * 16*724ba675SRob Herring * This file is distributed in the hope that it will be useful, 17*724ba675SRob Herring * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*724ba675SRob Herring * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*724ba675SRob Herring * GNU General Public License for more details. 20*724ba675SRob Herring * 21*724ba675SRob Herring * Or, alternatively, 22*724ba675SRob Herring * 23*724ba675SRob Herring * b) Permission is hereby granted, free of charge, to any person 24*724ba675SRob Herring * obtaining a copy of this software and associated documentation 25*724ba675SRob Herring * files (the "Software"), to deal in the Software without 26*724ba675SRob Herring * restriction, including without limitation the rights to use, 27*724ba675SRob Herring * copy, modify, merge, publish, distribute, sublicense, and/or 28*724ba675SRob Herring * sell copies of the Software, and to permit persons to whom the 29*724ba675SRob Herring * Software is furnished to do so, subject to the following 30*724ba675SRob Herring * conditions: 31*724ba675SRob Herring * 32*724ba675SRob Herring * The above copyright notice and this permission notice shall be 33*724ba675SRob Herring * included in all copies or substantial portions of the Software. 34*724ba675SRob Herring * 35*724ba675SRob Herring * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36*724ba675SRob Herring * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37*724ba675SRob Herring * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38*724ba675SRob Herring * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39*724ba675SRob Herring * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40*724ba675SRob Herring * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41*724ba675SRob Herring * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42*724ba675SRob Herring * OTHER DEALINGS IN THE SOFTWARE. 43*724ba675SRob Herring */ 44*724ba675SRob Herring 45*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 46*724ba675SRob Herring 47*724ba675SRob Herring#include <dt-bindings/clock/sun9i-a80-ccu.h> 48*724ba675SRob Herring#include <dt-bindings/clock/sun9i-a80-de.h> 49*724ba675SRob Herring#include <dt-bindings/clock/sun9i-a80-usb.h> 50*724ba675SRob Herring#include <dt-bindings/reset/sun9i-a80-ccu.h> 51*724ba675SRob Herring#include <dt-bindings/reset/sun9i-a80-de.h> 52*724ba675SRob Herring#include <dt-bindings/reset/sun9i-a80-usb.h> 53*724ba675SRob Herring 54*724ba675SRob Herring/ { 55*724ba675SRob Herring #address-cells = <2>; 56*724ba675SRob Herring #size-cells = <2>; 57*724ba675SRob Herring interrupt-parent = <&gic>; 58*724ba675SRob Herring 59*724ba675SRob Herring aliases { 60*724ba675SRob Herring ethernet0 = &gmac; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring cpus { 64*724ba675SRob Herring #address-cells = <1>; 65*724ba675SRob Herring #size-cells = <0>; 66*724ba675SRob Herring 67*724ba675SRob Herring cpu0: cpu@0 { 68*724ba675SRob Herring compatible = "arm,cortex-a7"; 69*724ba675SRob Herring device_type = "cpu"; 70*724ba675SRob Herring cci-control-port = <&cci_control0>; 71*724ba675SRob Herring clock-frequency = <12000000>; 72*724ba675SRob Herring enable-method = "allwinner,sun9i-a80-smp"; 73*724ba675SRob Herring reg = <0x0>; 74*724ba675SRob Herring }; 75*724ba675SRob Herring 76*724ba675SRob Herring cpu1: cpu@1 { 77*724ba675SRob Herring compatible = "arm,cortex-a7"; 78*724ba675SRob Herring device_type = "cpu"; 79*724ba675SRob Herring cci-control-port = <&cci_control0>; 80*724ba675SRob Herring clock-frequency = <12000000>; 81*724ba675SRob Herring enable-method = "allwinner,sun9i-a80-smp"; 82*724ba675SRob Herring reg = <0x1>; 83*724ba675SRob Herring }; 84*724ba675SRob Herring 85*724ba675SRob Herring cpu2: cpu@2 { 86*724ba675SRob Herring compatible = "arm,cortex-a7"; 87*724ba675SRob Herring device_type = "cpu"; 88*724ba675SRob Herring cci-control-port = <&cci_control0>; 89*724ba675SRob Herring clock-frequency = <12000000>; 90*724ba675SRob Herring enable-method = "allwinner,sun9i-a80-smp"; 91*724ba675SRob Herring reg = <0x2>; 92*724ba675SRob Herring }; 93*724ba675SRob Herring 94*724ba675SRob Herring cpu3: cpu@3 { 95*724ba675SRob Herring compatible = "arm,cortex-a7"; 96*724ba675SRob Herring device_type = "cpu"; 97*724ba675SRob Herring cci-control-port = <&cci_control0>; 98*724ba675SRob Herring clock-frequency = <12000000>; 99*724ba675SRob Herring enable-method = "allwinner,sun9i-a80-smp"; 100*724ba675SRob Herring reg = <0x3>; 101*724ba675SRob Herring }; 102*724ba675SRob Herring 103*724ba675SRob Herring cpu4: cpu@100 { 104*724ba675SRob Herring compatible = "arm,cortex-a15"; 105*724ba675SRob Herring device_type = "cpu"; 106*724ba675SRob Herring cci-control-port = <&cci_control1>; 107*724ba675SRob Herring clock-frequency = <18000000>; 108*724ba675SRob Herring enable-method = "allwinner,sun9i-a80-smp"; 109*724ba675SRob Herring reg = <0x100>; 110*724ba675SRob Herring }; 111*724ba675SRob Herring 112*724ba675SRob Herring cpu5: cpu@101 { 113*724ba675SRob Herring compatible = "arm,cortex-a15"; 114*724ba675SRob Herring device_type = "cpu"; 115*724ba675SRob Herring cci-control-port = <&cci_control1>; 116*724ba675SRob Herring clock-frequency = <18000000>; 117*724ba675SRob Herring enable-method = "allwinner,sun9i-a80-smp"; 118*724ba675SRob Herring reg = <0x101>; 119*724ba675SRob Herring }; 120*724ba675SRob Herring 121*724ba675SRob Herring cpu6: cpu@102 { 122*724ba675SRob Herring compatible = "arm,cortex-a15"; 123*724ba675SRob Herring device_type = "cpu"; 124*724ba675SRob Herring cci-control-port = <&cci_control1>; 125*724ba675SRob Herring clock-frequency = <18000000>; 126*724ba675SRob Herring enable-method = "allwinner,sun9i-a80-smp"; 127*724ba675SRob Herring reg = <0x102>; 128*724ba675SRob Herring }; 129*724ba675SRob Herring 130*724ba675SRob Herring cpu7: cpu@103 { 131*724ba675SRob Herring compatible = "arm,cortex-a15"; 132*724ba675SRob Herring device_type = "cpu"; 133*724ba675SRob Herring cci-control-port = <&cci_control1>; 134*724ba675SRob Herring clock-frequency = <18000000>; 135*724ba675SRob Herring enable-method = "allwinner,sun9i-a80-smp"; 136*724ba675SRob Herring reg = <0x103>; 137*724ba675SRob Herring }; 138*724ba675SRob Herring }; 139*724ba675SRob Herring 140*724ba675SRob Herring timer { 141*724ba675SRob Herring compatible = "arm,armv7-timer"; 142*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 143*724ba675SRob Herring <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 144*724ba675SRob Herring <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 145*724ba675SRob Herring <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 146*724ba675SRob Herring clock-frequency = <24000000>; 147*724ba675SRob Herring arm,cpu-registers-not-fw-configured; 148*724ba675SRob Herring }; 149*724ba675SRob Herring 150*724ba675SRob Herring clocks { 151*724ba675SRob Herring #address-cells = <1>; 152*724ba675SRob Herring #size-cells = <1>; 153*724ba675SRob Herring /* 154*724ba675SRob Herring * map 64 bit address range down to 32 bits, 155*724ba675SRob Herring * as the peripherals are all under 512MB. 156*724ba675SRob Herring */ 157*724ba675SRob Herring ranges = <0 0 0 0x20000000>; 158*724ba675SRob Herring 159*724ba675SRob Herring /* 160*724ba675SRob Herring * This clock is actually configurable from the PRCM address 161*724ba675SRob Herring * space. The external 24M oscillator can be turned off, and 162*724ba675SRob Herring * the clock switched to an internal 16M RC oscillator. Under 163*724ba675SRob Herring * normal operation there's no reason to do this, and the 164*724ba675SRob Herring * default is to use the external good one, so just model this 165*724ba675SRob Herring * as a fixed clock. Also it is not entirely clear if the 166*724ba675SRob Herring * osc24M mux in the PRCM affects the entire clock tree, which 167*724ba675SRob Herring * would also throw all the PLL clock rates off, or just the 168*724ba675SRob Herring * downstream clocks in the PRCM. 169*724ba675SRob Herring */ 170*724ba675SRob Herring osc24M: clk-24M { 171*724ba675SRob Herring #clock-cells = <0>; 172*724ba675SRob Herring compatible = "fixed-clock"; 173*724ba675SRob Herring clock-frequency = <24000000>; 174*724ba675SRob Herring clock-output-names = "osc24M"; 175*724ba675SRob Herring }; 176*724ba675SRob Herring 177*724ba675SRob Herring /* 178*724ba675SRob Herring * The 32k clock is from an external source, normally the 179*724ba675SRob Herring * AC100 codec/RTC chip. This serves as a placeholder for 180*724ba675SRob Herring * board dts files to specify the source. 181*724ba675SRob Herring */ 182*724ba675SRob Herring osc32k: clk-32k { 183*724ba675SRob Herring #clock-cells = <0>; 184*724ba675SRob Herring compatible = "fixed-factor-clock"; 185*724ba675SRob Herring clock-div = <1>; 186*724ba675SRob Herring clock-mult = <1>; 187*724ba675SRob Herring clock-output-names = "osc32k"; 188*724ba675SRob Herring }; 189*724ba675SRob Herring 190*724ba675SRob Herring /* 191*724ba675SRob Herring * The following two are dummy clocks, placeholders 192*724ba675SRob Herring * used in the gmac_tx clock. The gmac driver will 193*724ba675SRob Herring * choose one parent depending on the PHY interface 194*724ba675SRob Herring * mode, using clk_set_rate auto-reparenting. 195*724ba675SRob Herring * 196*724ba675SRob Herring * The actual TX clock rate is not controlled by the 197*724ba675SRob Herring * gmac_tx clock. 198*724ba675SRob Herring */ 199*724ba675SRob Herring mii_phy_tx_clk: mii_phy_tx_clk { 200*724ba675SRob Herring #clock-cells = <0>; 201*724ba675SRob Herring compatible = "fixed-clock"; 202*724ba675SRob Herring clock-frequency = <25000000>; 203*724ba675SRob Herring clock-output-names = "mii_phy_tx"; 204*724ba675SRob Herring }; 205*724ba675SRob Herring 206*724ba675SRob Herring gmac_int_tx_clk: gmac_int_tx_clk { 207*724ba675SRob Herring #clock-cells = <0>; 208*724ba675SRob Herring compatible = "fixed-clock"; 209*724ba675SRob Herring clock-frequency = <125000000>; 210*724ba675SRob Herring clock-output-names = "gmac_int_tx"; 211*724ba675SRob Herring }; 212*724ba675SRob Herring 213*724ba675SRob Herring gmac_tx_clk: clk@800030 { 214*724ba675SRob Herring #clock-cells = <0>; 215*724ba675SRob Herring compatible = "allwinner,sun7i-a20-gmac-clk"; 216*724ba675SRob Herring reg = <0x00800030 0x4>; 217*724ba675SRob Herring clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 218*724ba675SRob Herring clock-output-names = "gmac_tx"; 219*724ba675SRob Herring }; 220*724ba675SRob Herring 221*724ba675SRob Herring cpus_clk: clk@8001410 { 222*724ba675SRob Herring compatible = "allwinner,sun9i-a80-cpus-clk"; 223*724ba675SRob Herring reg = <0x08001410 0x4>; 224*724ba675SRob Herring #clock-cells = <0>; 225*724ba675SRob Herring clocks = <&osc32k>, <&osc24M>, 226*724ba675SRob Herring <&ccu CLK_PLL_PERIPH0>, 227*724ba675SRob Herring <&ccu CLK_PLL_AUDIO>; 228*724ba675SRob Herring clock-output-names = "cpus"; 229*724ba675SRob Herring }; 230*724ba675SRob Herring 231*724ba675SRob Herring ahbs: clk-ahbs { 232*724ba675SRob Herring compatible = "fixed-factor-clock"; 233*724ba675SRob Herring #clock-cells = <0>; 234*724ba675SRob Herring clock-div = <1>; 235*724ba675SRob Herring clock-mult = <1>; 236*724ba675SRob Herring clocks = <&cpus_clk>; 237*724ba675SRob Herring clock-output-names = "ahbs"; 238*724ba675SRob Herring }; 239*724ba675SRob Herring 240*724ba675SRob Herring apbs: clk@800141c { 241*724ba675SRob Herring compatible = "allwinner,sun8i-a23-apb0-clk"; 242*724ba675SRob Herring reg = <0x0800141c 0x4>; 243*724ba675SRob Herring #clock-cells = <0>; 244*724ba675SRob Herring clocks = <&ahbs>; 245*724ba675SRob Herring clock-output-names = "apbs"; 246*724ba675SRob Herring }; 247*724ba675SRob Herring 248*724ba675SRob Herring apbs_gates: clk@8001428 { 249*724ba675SRob Herring compatible = "allwinner,sun9i-a80-apbs-gates-clk"; 250*724ba675SRob Herring reg = <0x08001428 0x4>; 251*724ba675SRob Herring #clock-cells = <1>; 252*724ba675SRob Herring clocks = <&apbs>; 253*724ba675SRob Herring clock-indices = <0>, <1>, 254*724ba675SRob Herring <2>, <3>, 255*724ba675SRob Herring <4>, <5>, 256*724ba675SRob Herring <6>, <7>, 257*724ba675SRob Herring <12>, <13>, 258*724ba675SRob Herring <16>, <17>, 259*724ba675SRob Herring <18>, <20>; 260*724ba675SRob Herring clock-output-names = "apbs_pio", "apbs_ir", 261*724ba675SRob Herring "apbs_timer", "apbs_rsb", 262*724ba675SRob Herring "apbs_uart", "apbs_1wire", 263*724ba675SRob Herring "apbs_i2c0", "apbs_i2c1", 264*724ba675SRob Herring "apbs_ps2_0", "apbs_ps2_1", 265*724ba675SRob Herring "apbs_dma", "apbs_i2s0", 266*724ba675SRob Herring "apbs_i2s1", "apbs_twd"; 267*724ba675SRob Herring }; 268*724ba675SRob Herring 269*724ba675SRob Herring r_1wire_clk: clk@8001450 { 270*724ba675SRob Herring reg = <0x08001450 0x4>; 271*724ba675SRob Herring #clock-cells = <0>; 272*724ba675SRob Herring compatible = "allwinner,sun4i-a10-mod0-clk"; 273*724ba675SRob Herring clocks = <&osc32k>, <&osc24M>; 274*724ba675SRob Herring clock-output-names = "r_1wire"; 275*724ba675SRob Herring }; 276*724ba675SRob Herring 277*724ba675SRob Herring r_ir_clk: clk@8001454 { 278*724ba675SRob Herring reg = <0x08001454 0x4>; 279*724ba675SRob Herring #clock-cells = <0>; 280*724ba675SRob Herring compatible = "allwinner,sun4i-a10-mod0-clk"; 281*724ba675SRob Herring clocks = <&osc32k>, <&osc24M>; 282*724ba675SRob Herring clock-output-names = "r_ir"; 283*724ba675SRob Herring }; 284*724ba675SRob Herring }; 285*724ba675SRob Herring 286*724ba675SRob Herring de: display-engine { 287*724ba675SRob Herring compatible = "allwinner,sun9i-a80-display-engine"; 288*724ba675SRob Herring allwinner,pipelines = <&fe0>, <&fe1>; 289*724ba675SRob Herring status = "disabled"; 290*724ba675SRob Herring }; 291*724ba675SRob Herring 292*724ba675SRob Herring soc@20000 { 293*724ba675SRob Herring compatible = "simple-bus"; 294*724ba675SRob Herring #address-cells = <1>; 295*724ba675SRob Herring #size-cells = <1>; 296*724ba675SRob Herring /* 297*724ba675SRob Herring * map 64 bit address range down to 32 bits, 298*724ba675SRob Herring * as the peripherals are all under 512MB. 299*724ba675SRob Herring */ 300*724ba675SRob Herring ranges = <0 0 0 0x20000000>; 301*724ba675SRob Herring 302*724ba675SRob Herring sram_b: sram@20000 { 303*724ba675SRob Herring /* 256 KiB secure SRAM at 0x20000 */ 304*724ba675SRob Herring compatible = "mmio-sram"; 305*724ba675SRob Herring reg = <0x00020000 0x40000>; 306*724ba675SRob Herring 307*724ba675SRob Herring #address-cells = <1>; 308*724ba675SRob Herring #size-cells = <1>; 309*724ba675SRob Herring ranges = <0 0x00020000 0x40000>; 310*724ba675SRob Herring 311*724ba675SRob Herring smp-sram@1000 { 312*724ba675SRob Herring /* 313*724ba675SRob Herring * This is checked by BROM to determine if 314*724ba675SRob Herring * cpu0 should jump to SMP entry vector 315*724ba675SRob Herring */ 316*724ba675SRob Herring compatible = "allwinner,sun9i-a80-smp-sram"; 317*724ba675SRob Herring reg = <0x1000 0x8>; 318*724ba675SRob Herring }; 319*724ba675SRob Herring }; 320*724ba675SRob Herring 321*724ba675SRob Herring gmac: ethernet@830000 { 322*724ba675SRob Herring compatible = "allwinner,sun7i-a20-gmac"; 323*724ba675SRob Herring reg = <0x00830000 0x1054>; 324*724ba675SRob Herring interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 325*724ba675SRob Herring interrupt-names = "macirq"; 326*724ba675SRob Herring clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>; 327*724ba675SRob Herring clock-names = "stmmaceth", "allwinner_gmac_tx"; 328*724ba675SRob Herring resets = <&ccu RST_BUS_GMAC>; 329*724ba675SRob Herring reset-names = "stmmaceth"; 330*724ba675SRob Herring snps,pbl = <2>; 331*724ba675SRob Herring snps,fixed-burst; 332*724ba675SRob Herring snps,force_sf_dma_mode; 333*724ba675SRob Herring status = "disabled"; 334*724ba675SRob Herring 335*724ba675SRob Herring mdio: mdio { 336*724ba675SRob Herring compatible = "snps,dwmac-mdio"; 337*724ba675SRob Herring #address-cells = <1>; 338*724ba675SRob Herring #size-cells = <0>; 339*724ba675SRob Herring }; 340*724ba675SRob Herring }; 341*724ba675SRob Herring 342*724ba675SRob Herring ehci0: usb@a00000 { 343*724ba675SRob Herring compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 344*724ba675SRob Herring reg = <0x00a00000 0x100>; 345*724ba675SRob Herring interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 346*724ba675SRob Herring clocks = <&usb_clocks CLK_BUS_HCI0>; 347*724ba675SRob Herring resets = <&usb_clocks RST_USB0_HCI>; 348*724ba675SRob Herring phys = <&usbphy1>; 349*724ba675SRob Herring phy-names = "usb"; 350*724ba675SRob Herring status = "disabled"; 351*724ba675SRob Herring }; 352*724ba675SRob Herring 353*724ba675SRob Herring ohci0: usb@a00400 { 354*724ba675SRob Herring compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; 355*724ba675SRob Herring reg = <0x00a00400 0x100>; 356*724ba675SRob Herring interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 357*724ba675SRob Herring clocks = <&usb_clocks CLK_BUS_HCI0>, 358*724ba675SRob Herring <&usb_clocks CLK_USB_OHCI0>; 359*724ba675SRob Herring resets = <&usb_clocks RST_USB0_HCI>; 360*724ba675SRob Herring phys = <&usbphy1>; 361*724ba675SRob Herring phy-names = "usb"; 362*724ba675SRob Herring status = "disabled"; 363*724ba675SRob Herring }; 364*724ba675SRob Herring 365*724ba675SRob Herring usbphy1: phy@a00800 { 366*724ba675SRob Herring compatible = "allwinner,sun9i-a80-usb-phy"; 367*724ba675SRob Herring reg = <0x00a00800 0x4>; 368*724ba675SRob Herring clocks = <&usb_clocks CLK_USB0_PHY>; 369*724ba675SRob Herring clock-names = "phy"; 370*724ba675SRob Herring resets = <&usb_clocks RST_USB0_PHY>; 371*724ba675SRob Herring reset-names = "phy"; 372*724ba675SRob Herring status = "disabled"; 373*724ba675SRob Herring #phy-cells = <0>; 374*724ba675SRob Herring }; 375*724ba675SRob Herring 376*724ba675SRob Herring ehci1: usb@a01000 { 377*724ba675SRob Herring compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 378*724ba675SRob Herring reg = <0x00a01000 0x100>; 379*724ba675SRob Herring interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 380*724ba675SRob Herring clocks = <&usb_clocks CLK_BUS_HCI1>; 381*724ba675SRob Herring resets = <&usb_clocks RST_USB1_HCI>; 382*724ba675SRob Herring phys = <&usbphy2>; 383*724ba675SRob Herring phy-names = "usb"; 384*724ba675SRob Herring status = "disabled"; 385*724ba675SRob Herring }; 386*724ba675SRob Herring 387*724ba675SRob Herring usbphy2: phy@a01800 { 388*724ba675SRob Herring compatible = "allwinner,sun9i-a80-usb-phy"; 389*724ba675SRob Herring reg = <0x00a01800 0x4>; 390*724ba675SRob Herring clocks = <&usb_clocks CLK_USB1_PHY>, 391*724ba675SRob Herring <&usb_clocks CLK_USB_HSIC>, 392*724ba675SRob Herring <&usb_clocks CLK_USB1_HSIC>; 393*724ba675SRob Herring clock-names = "phy", 394*724ba675SRob Herring "hsic_12M", 395*724ba675SRob Herring "hsic_480M"; 396*724ba675SRob Herring resets = <&usb_clocks RST_USB1_PHY>, 397*724ba675SRob Herring <&usb_clocks RST_USB1_HSIC>; 398*724ba675SRob Herring reset-names = "phy", 399*724ba675SRob Herring "hsic"; 400*724ba675SRob Herring status = "disabled"; 401*724ba675SRob Herring #phy-cells = <0>; 402*724ba675SRob Herring /* usb1 is always used with HSIC */ 403*724ba675SRob Herring phy_type = "hsic"; 404*724ba675SRob Herring }; 405*724ba675SRob Herring 406*724ba675SRob Herring ehci2: usb@a02000 { 407*724ba675SRob Herring compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 408*724ba675SRob Herring reg = <0x00a02000 0x100>; 409*724ba675SRob Herring interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 410*724ba675SRob Herring clocks = <&usb_clocks CLK_BUS_HCI2>; 411*724ba675SRob Herring resets = <&usb_clocks RST_USB2_HCI>; 412*724ba675SRob Herring phys = <&usbphy3>; 413*724ba675SRob Herring phy-names = "usb"; 414*724ba675SRob Herring status = "disabled"; 415*724ba675SRob Herring }; 416*724ba675SRob Herring 417*724ba675SRob Herring ohci2: usb@a02400 { 418*724ba675SRob Herring compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; 419*724ba675SRob Herring reg = <0x00a02400 0x100>; 420*724ba675SRob Herring interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 421*724ba675SRob Herring clocks = <&usb_clocks CLK_BUS_HCI2>, 422*724ba675SRob Herring <&usb_clocks CLK_USB_OHCI2>; 423*724ba675SRob Herring resets = <&usb_clocks RST_USB2_HCI>; 424*724ba675SRob Herring phys = <&usbphy3>; 425*724ba675SRob Herring phy-names = "usb"; 426*724ba675SRob Herring status = "disabled"; 427*724ba675SRob Herring }; 428*724ba675SRob Herring 429*724ba675SRob Herring usbphy3: phy@a02800 { 430*724ba675SRob Herring compatible = "allwinner,sun9i-a80-usb-phy"; 431*724ba675SRob Herring reg = <0x00a02800 0x4>; 432*724ba675SRob Herring clocks = <&usb_clocks CLK_USB2_PHY>, 433*724ba675SRob Herring <&usb_clocks CLK_USB_HSIC>, 434*724ba675SRob Herring <&usb_clocks CLK_USB2_HSIC>; 435*724ba675SRob Herring clock-names = "phy", 436*724ba675SRob Herring "hsic_12M", 437*724ba675SRob Herring "hsic_480M"; 438*724ba675SRob Herring resets = <&usb_clocks RST_USB2_PHY>, 439*724ba675SRob Herring <&usb_clocks RST_USB2_HSIC>; 440*724ba675SRob Herring reset-names = "phy", 441*724ba675SRob Herring "hsic"; 442*724ba675SRob Herring status = "disabled"; 443*724ba675SRob Herring #phy-cells = <0>; 444*724ba675SRob Herring }; 445*724ba675SRob Herring 446*724ba675SRob Herring usb_clocks: clock@a08000 { 447*724ba675SRob Herring compatible = "allwinner,sun9i-a80-usb-clks"; 448*724ba675SRob Herring reg = <0x00a08000 0x8>; 449*724ba675SRob Herring clocks = <&ccu CLK_BUS_USB>, <&osc24M>; 450*724ba675SRob Herring clock-names = "bus", "hosc"; 451*724ba675SRob Herring #clock-cells = <1>; 452*724ba675SRob Herring #reset-cells = <1>; 453*724ba675SRob Herring }; 454*724ba675SRob Herring 455*724ba675SRob Herring cpucfg@1700000 { 456*724ba675SRob Herring compatible = "allwinner,sun9i-a80-cpucfg"; 457*724ba675SRob Herring reg = <0x01700000 0x100>; 458*724ba675SRob Herring }; 459*724ba675SRob Herring 460*724ba675SRob Herring crypto: crypto@1c02000 { 461*724ba675SRob Herring compatible = "allwinner,sun9i-a80-crypto"; 462*724ba675SRob Herring reg = <0x01c02000 0x1000>; 463*724ba675SRob Herring interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 464*724ba675SRob Herring resets = <&ccu RST_BUS_SS>; 465*724ba675SRob Herring clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; 466*724ba675SRob Herring clock-names = "bus", "mod"; 467*724ba675SRob Herring }; 468*724ba675SRob Herring 469*724ba675SRob Herring mmc0: mmc@1c0f000 { 470*724ba675SRob Herring compatible = "allwinner,sun9i-a80-mmc"; 471*724ba675SRob Herring reg = <0x01c0f000 0x1000>; 472*724ba675SRob Herring clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>, 473*724ba675SRob Herring <&ccu CLK_MMC0_OUTPUT>, 474*724ba675SRob Herring <&ccu CLK_MMC0_SAMPLE>; 475*724ba675SRob Herring clock-names = "ahb", "mmc", "output", "sample"; 476*724ba675SRob Herring resets = <&mmc_config_clk 0>; 477*724ba675SRob Herring reset-names = "ahb"; 478*724ba675SRob Herring interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 479*724ba675SRob Herring status = "disabled"; 480*724ba675SRob Herring #address-cells = <1>; 481*724ba675SRob Herring #size-cells = <0>; 482*724ba675SRob Herring }; 483*724ba675SRob Herring 484*724ba675SRob Herring mmc1: mmc@1c10000 { 485*724ba675SRob Herring compatible = "allwinner,sun9i-a80-mmc"; 486*724ba675SRob Herring reg = <0x01c10000 0x1000>; 487*724ba675SRob Herring clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>, 488*724ba675SRob Herring <&ccu CLK_MMC1_OUTPUT>, 489*724ba675SRob Herring <&ccu CLK_MMC1_SAMPLE>; 490*724ba675SRob Herring clock-names = "ahb", "mmc", "output", "sample"; 491*724ba675SRob Herring resets = <&mmc_config_clk 1>; 492*724ba675SRob Herring reset-names = "ahb"; 493*724ba675SRob Herring interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 494*724ba675SRob Herring status = "disabled"; 495*724ba675SRob Herring #address-cells = <1>; 496*724ba675SRob Herring #size-cells = <0>; 497*724ba675SRob Herring }; 498*724ba675SRob Herring 499*724ba675SRob Herring mmc2: mmc@1c11000 { 500*724ba675SRob Herring compatible = "allwinner,sun9i-a80-mmc"; 501*724ba675SRob Herring reg = <0x01c11000 0x1000>; 502*724ba675SRob Herring clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>, 503*724ba675SRob Herring <&ccu CLK_MMC2_OUTPUT>, 504*724ba675SRob Herring <&ccu CLK_MMC2_SAMPLE>; 505*724ba675SRob Herring clock-names = "ahb", "mmc", "output", "sample"; 506*724ba675SRob Herring resets = <&mmc_config_clk 2>; 507*724ba675SRob Herring reset-names = "ahb"; 508*724ba675SRob Herring interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 509*724ba675SRob Herring status = "disabled"; 510*724ba675SRob Herring #address-cells = <1>; 511*724ba675SRob Herring #size-cells = <0>; 512*724ba675SRob Herring }; 513*724ba675SRob Herring 514*724ba675SRob Herring mmc3: mmc@1c12000 { 515*724ba675SRob Herring compatible = "allwinner,sun9i-a80-mmc"; 516*724ba675SRob Herring reg = <0x01c12000 0x1000>; 517*724ba675SRob Herring clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>, 518*724ba675SRob Herring <&ccu CLK_MMC3_OUTPUT>, 519*724ba675SRob Herring <&ccu CLK_MMC3_SAMPLE>; 520*724ba675SRob Herring clock-names = "ahb", "mmc", "output", "sample"; 521*724ba675SRob Herring resets = <&mmc_config_clk 3>; 522*724ba675SRob Herring reset-names = "ahb"; 523*724ba675SRob Herring interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 524*724ba675SRob Herring status = "disabled"; 525*724ba675SRob Herring #address-cells = <1>; 526*724ba675SRob Herring #size-cells = <0>; 527*724ba675SRob Herring }; 528*724ba675SRob Herring 529*724ba675SRob Herring mmc_config_clk: clk@1c13000 { 530*724ba675SRob Herring compatible = "allwinner,sun9i-a80-mmc-config-clk"; 531*724ba675SRob Herring reg = <0x01c13000 0x10>; 532*724ba675SRob Herring clocks = <&ccu CLK_BUS_MMC>; 533*724ba675SRob Herring resets = <&ccu RST_BUS_MMC>; 534*724ba675SRob Herring #clock-cells = <1>; 535*724ba675SRob Herring #reset-cells = <1>; 536*724ba675SRob Herring clock-output-names = "mmc0_config", "mmc1_config", 537*724ba675SRob Herring "mmc2_config", "mmc3_config"; 538*724ba675SRob Herring }; 539*724ba675SRob Herring 540*724ba675SRob Herring gic: interrupt-controller@1c41000 { 541*724ba675SRob Herring compatible = "arm,gic-400"; 542*724ba675SRob Herring reg = <0x01c41000 0x1000>, 543*724ba675SRob Herring <0x01c42000 0x2000>, 544*724ba675SRob Herring <0x01c44000 0x2000>, 545*724ba675SRob Herring <0x01c46000 0x2000>; 546*724ba675SRob Herring interrupt-controller; 547*724ba675SRob Herring #interrupt-cells = <3>; 548*724ba675SRob Herring interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 549*724ba675SRob Herring }; 550*724ba675SRob Herring 551*724ba675SRob Herring cci: cci@1c90000 { 552*724ba675SRob Herring compatible = "arm,cci-400"; 553*724ba675SRob Herring #address-cells = <1>; 554*724ba675SRob Herring #size-cells = <1>; 555*724ba675SRob Herring reg = <0x01c90000 0x1000>; 556*724ba675SRob Herring ranges = <0x0 0x01c90000 0x10000>; 557*724ba675SRob Herring 558*724ba675SRob Herring cci_control0: slave-if@4000 { 559*724ba675SRob Herring compatible = "arm,cci-400-ctrl-if"; 560*724ba675SRob Herring interface-type = "ace"; 561*724ba675SRob Herring reg = <0x4000 0x1000>; 562*724ba675SRob Herring }; 563*724ba675SRob Herring 564*724ba675SRob Herring cci_control1: slave-if@5000 { 565*724ba675SRob Herring compatible = "arm,cci-400-ctrl-if"; 566*724ba675SRob Herring interface-type = "ace"; 567*724ba675SRob Herring reg = <0x5000 0x1000>; 568*724ba675SRob Herring }; 569*724ba675SRob Herring 570*724ba675SRob Herring pmu@9000 { 571*724ba675SRob Herring compatible = "arm,cci-400-pmu,r1"; 572*724ba675SRob Herring reg = <0x9000 0x5000>; 573*724ba675SRob Herring interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 574*724ba675SRob Herring <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 575*724ba675SRob Herring <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 576*724ba675SRob Herring <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 577*724ba675SRob Herring <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 578*724ba675SRob Herring }; 579*724ba675SRob Herring }; 580*724ba675SRob Herring 581*724ba675SRob Herring de_clocks: clock@3000000 { 582*724ba675SRob Herring compatible = "allwinner,sun9i-a80-de-clks"; 583*724ba675SRob Herring reg = <0x03000000 0x30>; 584*724ba675SRob Herring clocks = <&ccu CLK_DE>, 585*724ba675SRob Herring <&ccu CLK_SDRAM>, 586*724ba675SRob Herring <&ccu CLK_BUS_DE>; 587*724ba675SRob Herring clock-names = "mod", 588*724ba675SRob Herring "dram", 589*724ba675SRob Herring "bus"; 590*724ba675SRob Herring resets = <&ccu RST_BUS_DE>; 591*724ba675SRob Herring #clock-cells = <1>; 592*724ba675SRob Herring #reset-cells = <1>; 593*724ba675SRob Herring }; 594*724ba675SRob Herring 595*724ba675SRob Herring fe0: display-frontend@3100000 { 596*724ba675SRob Herring compatible = "allwinner,sun9i-a80-display-frontend"; 597*724ba675SRob Herring reg = <0x03100000 0x40000>; 598*724ba675SRob Herring interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 599*724ba675SRob Herring clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>, 600*724ba675SRob Herring <&de_clocks CLK_DRAM_FE0>; 601*724ba675SRob Herring clock-names = "ahb", "mod", 602*724ba675SRob Herring "ram"; 603*724ba675SRob Herring resets = <&de_clocks RST_FE0>; 604*724ba675SRob Herring 605*724ba675SRob Herring ports { 606*724ba675SRob Herring #address-cells = <1>; 607*724ba675SRob Herring #size-cells = <0>; 608*724ba675SRob Herring 609*724ba675SRob Herring fe0_out: port@1 { 610*724ba675SRob Herring reg = <1>; 611*724ba675SRob Herring 612*724ba675SRob Herring fe0_out_deu0: endpoint { 613*724ba675SRob Herring remote-endpoint = <&deu0_in_fe0>; 614*724ba675SRob Herring }; 615*724ba675SRob Herring }; 616*724ba675SRob Herring }; 617*724ba675SRob Herring }; 618*724ba675SRob Herring 619*724ba675SRob Herring fe1: display-frontend@3140000 { 620*724ba675SRob Herring compatible = "allwinner,sun9i-a80-display-frontend"; 621*724ba675SRob Herring reg = <0x03140000 0x40000>; 622*724ba675SRob Herring interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 623*724ba675SRob Herring clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>, 624*724ba675SRob Herring <&de_clocks CLK_DRAM_FE1>; 625*724ba675SRob Herring clock-names = "ahb", "mod", 626*724ba675SRob Herring "ram"; 627*724ba675SRob Herring resets = <&de_clocks RST_FE0>; 628*724ba675SRob Herring 629*724ba675SRob Herring ports { 630*724ba675SRob Herring #address-cells = <1>; 631*724ba675SRob Herring #size-cells = <0>; 632*724ba675SRob Herring 633*724ba675SRob Herring fe1_out: port@1 { 634*724ba675SRob Herring reg = <1>; 635*724ba675SRob Herring 636*724ba675SRob Herring fe1_out_deu1: endpoint { 637*724ba675SRob Herring remote-endpoint = <&deu1_in_fe1>; 638*724ba675SRob Herring }; 639*724ba675SRob Herring }; 640*724ba675SRob Herring }; 641*724ba675SRob Herring }; 642*724ba675SRob Herring 643*724ba675SRob Herring be0: display-backend@3200000 { 644*724ba675SRob Herring compatible = "allwinner,sun9i-a80-display-backend"; 645*724ba675SRob Herring reg = <0x03200000 0x40000>; 646*724ba675SRob Herring interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 647*724ba675SRob Herring clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>, 648*724ba675SRob Herring <&de_clocks CLK_DRAM_BE0>; 649*724ba675SRob Herring clock-names = "ahb", "mod", 650*724ba675SRob Herring "ram"; 651*724ba675SRob Herring resets = <&de_clocks RST_BE0>; 652*724ba675SRob Herring 653*724ba675SRob Herring ports { 654*724ba675SRob Herring #address-cells = <1>; 655*724ba675SRob Herring #size-cells = <0>; 656*724ba675SRob Herring 657*724ba675SRob Herring be0_in: port@0 { 658*724ba675SRob Herring #address-cells = <1>; 659*724ba675SRob Herring #size-cells = <0>; 660*724ba675SRob Herring reg = <0>; 661*724ba675SRob Herring 662*724ba675SRob Herring be0_in_deu0: endpoint@0 { 663*724ba675SRob Herring reg = <0>; 664*724ba675SRob Herring remote-endpoint = <&deu0_out_be0>; 665*724ba675SRob Herring }; 666*724ba675SRob Herring 667*724ba675SRob Herring be0_in_deu1: endpoint@1 { 668*724ba675SRob Herring reg = <1>; 669*724ba675SRob Herring remote-endpoint = <&deu1_out_be0>; 670*724ba675SRob Herring }; 671*724ba675SRob Herring }; 672*724ba675SRob Herring 673*724ba675SRob Herring be0_out: port@1 { 674*724ba675SRob Herring reg = <1>; 675*724ba675SRob Herring 676*724ba675SRob Herring be0_out_drc0: endpoint { 677*724ba675SRob Herring remote-endpoint = <&drc0_in_be0>; 678*724ba675SRob Herring }; 679*724ba675SRob Herring }; 680*724ba675SRob Herring }; 681*724ba675SRob Herring }; 682*724ba675SRob Herring 683*724ba675SRob Herring be1: display-backend@3240000 { 684*724ba675SRob Herring compatible = "allwinner,sun9i-a80-display-backend"; 685*724ba675SRob Herring reg = <0x03240000 0x40000>; 686*724ba675SRob Herring interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 687*724ba675SRob Herring clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>, 688*724ba675SRob Herring <&de_clocks CLK_DRAM_BE1>; 689*724ba675SRob Herring clock-names = "ahb", "mod", 690*724ba675SRob Herring "ram"; 691*724ba675SRob Herring resets = <&de_clocks RST_BE1>; 692*724ba675SRob Herring 693*724ba675SRob Herring ports { 694*724ba675SRob Herring #address-cells = <1>; 695*724ba675SRob Herring #size-cells = <0>; 696*724ba675SRob Herring 697*724ba675SRob Herring be1_in: port@0 { 698*724ba675SRob Herring #address-cells = <1>; 699*724ba675SRob Herring #size-cells = <0>; 700*724ba675SRob Herring reg = <0>; 701*724ba675SRob Herring 702*724ba675SRob Herring be1_in_deu0: endpoint@0 { 703*724ba675SRob Herring reg = <0>; 704*724ba675SRob Herring remote-endpoint = <&deu0_out_be1>; 705*724ba675SRob Herring }; 706*724ba675SRob Herring 707*724ba675SRob Herring be1_in_deu1: endpoint@1 { 708*724ba675SRob Herring reg = <1>; 709*724ba675SRob Herring remote-endpoint = <&deu1_out_be1>; 710*724ba675SRob Herring }; 711*724ba675SRob Herring }; 712*724ba675SRob Herring 713*724ba675SRob Herring be1_out: port@1 { 714*724ba675SRob Herring reg = <1>; 715*724ba675SRob Herring 716*724ba675SRob Herring be1_out_drc1: endpoint { 717*724ba675SRob Herring remote-endpoint = <&drc1_in_be1>; 718*724ba675SRob Herring }; 719*724ba675SRob Herring }; 720*724ba675SRob Herring }; 721*724ba675SRob Herring }; 722*724ba675SRob Herring 723*724ba675SRob Herring deu0: deu@3300000 { 724*724ba675SRob Herring compatible = "allwinner,sun9i-a80-deu"; 725*724ba675SRob Herring reg = <0x03300000 0x40000>; 726*724ba675SRob Herring interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 727*724ba675SRob Herring clocks = <&de_clocks CLK_BUS_DEU0>, 728*724ba675SRob Herring <&de_clocks CLK_IEP_DEU0>, 729*724ba675SRob Herring <&de_clocks CLK_DRAM_DEU0>; 730*724ba675SRob Herring clock-names = "ahb", 731*724ba675SRob Herring "mod", 732*724ba675SRob Herring "ram"; 733*724ba675SRob Herring resets = <&de_clocks RST_DEU0>; 734*724ba675SRob Herring 735*724ba675SRob Herring ports { 736*724ba675SRob Herring #address-cells = <1>; 737*724ba675SRob Herring #size-cells = <0>; 738*724ba675SRob Herring 739*724ba675SRob Herring deu0_in: port@0 { 740*724ba675SRob Herring reg = <0>; 741*724ba675SRob Herring 742*724ba675SRob Herring deu0_in_fe0: endpoint { 743*724ba675SRob Herring remote-endpoint = <&fe0_out_deu0>; 744*724ba675SRob Herring }; 745*724ba675SRob Herring }; 746*724ba675SRob Herring 747*724ba675SRob Herring deu0_out: port@1 { 748*724ba675SRob Herring #address-cells = <1>; 749*724ba675SRob Herring #size-cells = <0>; 750*724ba675SRob Herring reg = <1>; 751*724ba675SRob Herring 752*724ba675SRob Herring deu0_out_be0: endpoint@0 { 753*724ba675SRob Herring reg = <0>; 754*724ba675SRob Herring remote-endpoint = <&be0_in_deu0>; 755*724ba675SRob Herring }; 756*724ba675SRob Herring 757*724ba675SRob Herring deu0_out_be1: endpoint@1 { 758*724ba675SRob Herring reg = <1>; 759*724ba675SRob Herring remote-endpoint = <&be1_in_deu0>; 760*724ba675SRob Herring }; 761*724ba675SRob Herring }; 762*724ba675SRob Herring }; 763*724ba675SRob Herring }; 764*724ba675SRob Herring 765*724ba675SRob Herring deu1: deu@3340000 { 766*724ba675SRob Herring compatible = "allwinner,sun9i-a80-deu"; 767*724ba675SRob Herring reg = <0x03340000 0x40000>; 768*724ba675SRob Herring interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 769*724ba675SRob Herring clocks = <&de_clocks CLK_BUS_DEU1>, 770*724ba675SRob Herring <&de_clocks CLK_IEP_DEU1>, 771*724ba675SRob Herring <&de_clocks CLK_DRAM_DEU1>; 772*724ba675SRob Herring clock-names = "ahb", 773*724ba675SRob Herring "mod", 774*724ba675SRob Herring "ram"; 775*724ba675SRob Herring resets = <&de_clocks RST_DEU1>; 776*724ba675SRob Herring 777*724ba675SRob Herring ports { 778*724ba675SRob Herring #address-cells = <1>; 779*724ba675SRob Herring #size-cells = <0>; 780*724ba675SRob Herring 781*724ba675SRob Herring deu1_in: port@0 { 782*724ba675SRob Herring reg = <0>; 783*724ba675SRob Herring 784*724ba675SRob Herring deu1_in_fe1: endpoint { 785*724ba675SRob Herring remote-endpoint = <&fe1_out_deu1>; 786*724ba675SRob Herring }; 787*724ba675SRob Herring }; 788*724ba675SRob Herring 789*724ba675SRob Herring deu1_out: port@1 { 790*724ba675SRob Herring #address-cells = <1>; 791*724ba675SRob Herring #size-cells = <0>; 792*724ba675SRob Herring reg = <1>; 793*724ba675SRob Herring 794*724ba675SRob Herring deu1_out_be0: endpoint@0 { 795*724ba675SRob Herring reg = <0>; 796*724ba675SRob Herring remote-endpoint = <&be0_in_deu1>; 797*724ba675SRob Herring }; 798*724ba675SRob Herring 799*724ba675SRob Herring deu1_out_be1: endpoint@1 { 800*724ba675SRob Herring reg = <1>; 801*724ba675SRob Herring remote-endpoint = <&be1_in_deu1>; 802*724ba675SRob Herring }; 803*724ba675SRob Herring }; 804*724ba675SRob Herring }; 805*724ba675SRob Herring }; 806*724ba675SRob Herring 807*724ba675SRob Herring drc0: drc@3400000 { 808*724ba675SRob Herring compatible = "allwinner,sun9i-a80-drc"; 809*724ba675SRob Herring reg = <0x03400000 0x40000>; 810*724ba675SRob Herring interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 811*724ba675SRob Herring clocks = <&de_clocks CLK_BUS_DRC0>, 812*724ba675SRob Herring <&de_clocks CLK_IEP_DRC0>, 813*724ba675SRob Herring <&de_clocks CLK_DRAM_DRC0>; 814*724ba675SRob Herring clock-names = "ahb", 815*724ba675SRob Herring "mod", 816*724ba675SRob Herring "ram"; 817*724ba675SRob Herring resets = <&de_clocks RST_DRC0>; 818*724ba675SRob Herring 819*724ba675SRob Herring ports { 820*724ba675SRob Herring #address-cells = <1>; 821*724ba675SRob Herring #size-cells = <0>; 822*724ba675SRob Herring 823*724ba675SRob Herring drc0_in: port@0 { 824*724ba675SRob Herring reg = <0>; 825*724ba675SRob Herring 826*724ba675SRob Herring drc0_in_be0: endpoint { 827*724ba675SRob Herring remote-endpoint = <&be0_out_drc0>; 828*724ba675SRob Herring }; 829*724ba675SRob Herring }; 830*724ba675SRob Herring 831*724ba675SRob Herring drc0_out: port@1 { 832*724ba675SRob Herring reg = <1>; 833*724ba675SRob Herring 834*724ba675SRob Herring drc0_out_tcon0: endpoint { 835*724ba675SRob Herring remote-endpoint = <&tcon0_in_drc0>; 836*724ba675SRob Herring }; 837*724ba675SRob Herring }; 838*724ba675SRob Herring }; 839*724ba675SRob Herring }; 840*724ba675SRob Herring 841*724ba675SRob Herring drc1: drc@3440000 { 842*724ba675SRob Herring compatible = "allwinner,sun9i-a80-drc"; 843*724ba675SRob Herring reg = <0x03440000 0x40000>; 844*724ba675SRob Herring interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 845*724ba675SRob Herring clocks = <&de_clocks CLK_BUS_DRC1>, 846*724ba675SRob Herring <&de_clocks CLK_IEP_DRC1>, 847*724ba675SRob Herring <&de_clocks CLK_DRAM_DRC1>; 848*724ba675SRob Herring clock-names = "ahb", 849*724ba675SRob Herring "mod", 850*724ba675SRob Herring "ram"; 851*724ba675SRob Herring resets = <&de_clocks RST_DRC1>; 852*724ba675SRob Herring 853*724ba675SRob Herring ports { 854*724ba675SRob Herring #address-cells = <1>; 855*724ba675SRob Herring #size-cells = <0>; 856*724ba675SRob Herring 857*724ba675SRob Herring drc1_in: port@0 { 858*724ba675SRob Herring reg = <0>; 859*724ba675SRob Herring 860*724ba675SRob Herring drc1_in_be1: endpoint { 861*724ba675SRob Herring remote-endpoint = <&be1_out_drc1>; 862*724ba675SRob Herring }; 863*724ba675SRob Herring }; 864*724ba675SRob Herring 865*724ba675SRob Herring drc1_out: port@1 { 866*724ba675SRob Herring reg = <1>; 867*724ba675SRob Herring 868*724ba675SRob Herring drc1_out_tcon1: endpoint { 869*724ba675SRob Herring remote-endpoint = <&tcon1_in_drc1>; 870*724ba675SRob Herring }; 871*724ba675SRob Herring }; 872*724ba675SRob Herring }; 873*724ba675SRob Herring }; 874*724ba675SRob Herring 875*724ba675SRob Herring tcon0: lcd-controller@3c00000 { 876*724ba675SRob Herring compatible = "allwinner,sun9i-a80-tcon-lcd"; 877*724ba675SRob Herring reg = <0x03c00000 0x10000>; 878*724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 879*724ba675SRob Herring clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>; 880*724ba675SRob Herring clock-names = "ahb", "tcon-ch0"; 881*724ba675SRob Herring resets = <&ccu RST_BUS_LCD0>, 882*724ba675SRob Herring <&ccu RST_BUS_EDP>, 883*724ba675SRob Herring <&ccu RST_BUS_LVDS>; 884*724ba675SRob Herring reset-names = "lcd", 885*724ba675SRob Herring "edp", 886*724ba675SRob Herring "lvds"; 887*724ba675SRob Herring clock-output-names = "tcon0-pixel-clock"; 888*724ba675SRob Herring #clock-cells = <0>; 889*724ba675SRob Herring 890*724ba675SRob Herring ports { 891*724ba675SRob Herring #address-cells = <1>; 892*724ba675SRob Herring #size-cells = <0>; 893*724ba675SRob Herring 894*724ba675SRob Herring tcon0_in: port@0 { 895*724ba675SRob Herring reg = <0>; 896*724ba675SRob Herring 897*724ba675SRob Herring tcon0_in_drc0: endpoint { 898*724ba675SRob Herring remote-endpoint = <&drc0_out_tcon0>; 899*724ba675SRob Herring }; 900*724ba675SRob Herring }; 901*724ba675SRob Herring 902*724ba675SRob Herring tcon0_out: port@1 { 903*724ba675SRob Herring reg = <1>; 904*724ba675SRob Herring }; 905*724ba675SRob Herring }; 906*724ba675SRob Herring }; 907*724ba675SRob Herring 908*724ba675SRob Herring tcon1: lcd-controller@3c10000 { 909*724ba675SRob Herring compatible = "allwinner,sun9i-a80-tcon-tv"; 910*724ba675SRob Herring reg = <0x03c10000 0x10000>; 911*724ba675SRob Herring interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 912*724ba675SRob Herring clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>; 913*724ba675SRob Herring clock-names = "ahb", "tcon-ch1"; 914*724ba675SRob Herring resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>; 915*724ba675SRob Herring reset-names = "lcd", "edp"; 916*724ba675SRob Herring 917*724ba675SRob Herring ports { 918*724ba675SRob Herring #address-cells = <1>; 919*724ba675SRob Herring #size-cells = <0>; 920*724ba675SRob Herring 921*724ba675SRob Herring tcon1_in: port@0 { 922*724ba675SRob Herring reg = <0>; 923*724ba675SRob Herring 924*724ba675SRob Herring tcon1_in_drc1: endpoint { 925*724ba675SRob Herring remote-endpoint = <&drc1_out_tcon1>; 926*724ba675SRob Herring }; 927*724ba675SRob Herring }; 928*724ba675SRob Herring 929*724ba675SRob Herring tcon1_out: port@1 { 930*724ba675SRob Herring reg = <1>; 931*724ba675SRob Herring }; 932*724ba675SRob Herring }; 933*724ba675SRob Herring }; 934*724ba675SRob Herring 935*724ba675SRob Herring ccu: clock@6000000 { 936*724ba675SRob Herring compatible = "allwinner,sun9i-a80-ccu"; 937*724ba675SRob Herring reg = <0x06000000 0x800>; 938*724ba675SRob Herring clocks = <&osc24M>, <&osc32k>; 939*724ba675SRob Herring clock-names = "hosc", "losc"; 940*724ba675SRob Herring #clock-cells = <1>; 941*724ba675SRob Herring #reset-cells = <1>; 942*724ba675SRob Herring }; 943*724ba675SRob Herring 944*724ba675SRob Herring timer@6000c00 { 945*724ba675SRob Herring compatible = "allwinner,sun4i-a10-timer"; 946*724ba675SRob Herring reg = <0x06000c00 0xa0>; 947*724ba675SRob Herring interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 948*724ba675SRob Herring <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 949*724ba675SRob Herring <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 950*724ba675SRob Herring <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 951*724ba675SRob Herring <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 952*724ba675SRob Herring <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 953*724ba675SRob Herring 954*724ba675SRob Herring clocks = <&osc24M>; 955*724ba675SRob Herring }; 956*724ba675SRob Herring 957*724ba675SRob Herring wdt: watchdog@6000ca0 { 958*724ba675SRob Herring compatible = "allwinner,sun6i-a31-wdt"; 959*724ba675SRob Herring reg = <0x06000ca0 0x20>; 960*724ba675SRob Herring interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 961*724ba675SRob Herring clocks = <&osc24M>; 962*724ba675SRob Herring }; 963*724ba675SRob Herring 964*724ba675SRob Herring pio: pinctrl@6000800 { 965*724ba675SRob Herring compatible = "allwinner,sun9i-a80-pinctrl"; 966*724ba675SRob Herring reg = <0x06000800 0x400>; 967*724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 968*724ba675SRob Herring <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 969*724ba675SRob Herring <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 970*724ba675SRob Herring <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 971*724ba675SRob Herring <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 972*724ba675SRob Herring clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; 973*724ba675SRob Herring clock-names = "apb", "hosc", "losc"; 974*724ba675SRob Herring gpio-controller; 975*724ba675SRob Herring interrupt-controller; 976*724ba675SRob Herring #interrupt-cells = <3>; 977*724ba675SRob Herring #gpio-cells = <3>; 978*724ba675SRob Herring 979*724ba675SRob Herring gmac_rgmii_pins: gmac-rgmii-pins { 980*724ba675SRob Herring pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", 981*724ba675SRob Herring "PA7", "PA8", "PA9", "PA10", "PA12", 982*724ba675SRob Herring "PA13", "PA15", "PA16", "PA17"; 983*724ba675SRob Herring function = "gmac"; 984*724ba675SRob Herring /* 985*724ba675SRob Herring * data lines in RGMII mode use DDR mode 986*724ba675SRob Herring * and need a higher signal drive strength 987*724ba675SRob Herring */ 988*724ba675SRob Herring drive-strength = <40>; 989*724ba675SRob Herring }; 990*724ba675SRob Herring 991*724ba675SRob Herring i2c3_pins: i2c3-pins { 992*724ba675SRob Herring pins = "PG10", "PG11"; 993*724ba675SRob Herring function = "i2c3"; 994*724ba675SRob Herring }; 995*724ba675SRob Herring 996*724ba675SRob Herring lcd0_rgb888_pins: lcd0-rgb888-pins { 997*724ba675SRob Herring pins = "PD0", "PD1", "PD2", "PD3", 998*724ba675SRob Herring "PD4", "PD5", "PD6", "PD7", 999*724ba675SRob Herring "PD8", "PD9", "PD10", "PD11", 1000*724ba675SRob Herring "PD12", "PD13", "PD14", "PD15", 1001*724ba675SRob Herring "PD16", "PD17", "PD18", "PD19", 1002*724ba675SRob Herring "PD20", "PD21", "PD22", "PD23", 1003*724ba675SRob Herring "PD24", "PD25", "PD26", "PD27"; 1004*724ba675SRob Herring function = "lcd0"; 1005*724ba675SRob Herring }; 1006*724ba675SRob Herring 1007*724ba675SRob Herring mmc0_pins: mmc0-pins { 1008*724ba675SRob Herring pins = "PF0", "PF1" ,"PF2", "PF3", 1009*724ba675SRob Herring "PF4", "PF5"; 1010*724ba675SRob Herring function = "mmc0"; 1011*724ba675SRob Herring drive-strength = <30>; 1012*724ba675SRob Herring bias-pull-up; 1013*724ba675SRob Herring }; 1014*724ba675SRob Herring 1015*724ba675SRob Herring mmc1_pins: mmc1-pins { 1016*724ba675SRob Herring pins = "PG0", "PG1" ,"PG2", "PG3", 1017*724ba675SRob Herring "PG4", "PG5"; 1018*724ba675SRob Herring function = "mmc1"; 1019*724ba675SRob Herring drive-strength = <30>; 1020*724ba675SRob Herring bias-pull-up; 1021*724ba675SRob Herring }; 1022*724ba675SRob Herring 1023*724ba675SRob Herring mmc2_8bit_pins: mmc2-8bit-pins { 1024*724ba675SRob Herring pins = "PC6", "PC7", "PC8", "PC9", 1025*724ba675SRob Herring "PC10", "PC11", "PC12", 1026*724ba675SRob Herring "PC13", "PC14", "PC15", 1027*724ba675SRob Herring "PC16"; 1028*724ba675SRob Herring function = "mmc2"; 1029*724ba675SRob Herring drive-strength = <30>; 1030*724ba675SRob Herring bias-pull-up; 1031*724ba675SRob Herring }; 1032*724ba675SRob Herring 1033*724ba675SRob Herring uart0_ph_pins: uart0-ph-pins { 1034*724ba675SRob Herring pins = "PH12", "PH13"; 1035*724ba675SRob Herring function = "uart0"; 1036*724ba675SRob Herring }; 1037*724ba675SRob Herring 1038*724ba675SRob Herring uart4_pins: uart4-pins { 1039*724ba675SRob Herring pins = "PG12", "PG13", "PG14", "PG15"; 1040*724ba675SRob Herring function = "uart4"; 1041*724ba675SRob Herring }; 1042*724ba675SRob Herring }; 1043*724ba675SRob Herring 1044*724ba675SRob Herring uart0: serial@7000000 { 1045*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 1046*724ba675SRob Herring reg = <0x07000000 0x400>; 1047*724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1048*724ba675SRob Herring reg-shift = <2>; 1049*724ba675SRob Herring reg-io-width = <4>; 1050*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART0>; 1051*724ba675SRob Herring resets = <&ccu RST_BUS_UART0>; 1052*724ba675SRob Herring status = "disabled"; 1053*724ba675SRob Herring }; 1054*724ba675SRob Herring 1055*724ba675SRob Herring uart1: serial@7000400 { 1056*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 1057*724ba675SRob Herring reg = <0x07000400 0x400>; 1058*724ba675SRob Herring interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1059*724ba675SRob Herring reg-shift = <2>; 1060*724ba675SRob Herring reg-io-width = <4>; 1061*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART1>; 1062*724ba675SRob Herring resets = <&ccu RST_BUS_UART1>; 1063*724ba675SRob Herring status = "disabled"; 1064*724ba675SRob Herring }; 1065*724ba675SRob Herring 1066*724ba675SRob Herring uart2: serial@7000800 { 1067*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 1068*724ba675SRob Herring reg = <0x07000800 0x400>; 1069*724ba675SRob Herring interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1070*724ba675SRob Herring reg-shift = <2>; 1071*724ba675SRob Herring reg-io-width = <4>; 1072*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART2>; 1073*724ba675SRob Herring resets = <&ccu RST_BUS_UART2>; 1074*724ba675SRob Herring status = "disabled"; 1075*724ba675SRob Herring }; 1076*724ba675SRob Herring 1077*724ba675SRob Herring uart3: serial@7000c00 { 1078*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 1079*724ba675SRob Herring reg = <0x07000c00 0x400>; 1080*724ba675SRob Herring interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1081*724ba675SRob Herring reg-shift = <2>; 1082*724ba675SRob Herring reg-io-width = <4>; 1083*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART3>; 1084*724ba675SRob Herring resets = <&ccu RST_BUS_UART3>; 1085*724ba675SRob Herring status = "disabled"; 1086*724ba675SRob Herring }; 1087*724ba675SRob Herring 1088*724ba675SRob Herring uart4: serial@7001000 { 1089*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 1090*724ba675SRob Herring reg = <0x07001000 0x400>; 1091*724ba675SRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1092*724ba675SRob Herring reg-shift = <2>; 1093*724ba675SRob Herring reg-io-width = <4>; 1094*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART4>; 1095*724ba675SRob Herring resets = <&ccu RST_BUS_UART4>; 1096*724ba675SRob Herring status = "disabled"; 1097*724ba675SRob Herring }; 1098*724ba675SRob Herring 1099*724ba675SRob Herring uart5: serial@7001400 { 1100*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 1101*724ba675SRob Herring reg = <0x07001400 0x400>; 1102*724ba675SRob Herring interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1103*724ba675SRob Herring reg-shift = <2>; 1104*724ba675SRob Herring reg-io-width = <4>; 1105*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART5>; 1106*724ba675SRob Herring resets = <&ccu RST_BUS_UART5>; 1107*724ba675SRob Herring status = "disabled"; 1108*724ba675SRob Herring }; 1109*724ba675SRob Herring 1110*724ba675SRob Herring i2c0: i2c@7002800 { 1111*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 1112*724ba675SRob Herring reg = <0x07002800 0x400>; 1113*724ba675SRob Herring interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1114*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C0>; 1115*724ba675SRob Herring resets = <&ccu RST_BUS_I2C0>; 1116*724ba675SRob Herring status = "disabled"; 1117*724ba675SRob Herring #address-cells = <1>; 1118*724ba675SRob Herring #size-cells = <0>; 1119*724ba675SRob Herring }; 1120*724ba675SRob Herring 1121*724ba675SRob Herring i2c1: i2c@7002c00 { 1122*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 1123*724ba675SRob Herring reg = <0x07002c00 0x400>; 1124*724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1125*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C1>; 1126*724ba675SRob Herring resets = <&ccu RST_BUS_I2C1>; 1127*724ba675SRob Herring status = "disabled"; 1128*724ba675SRob Herring #address-cells = <1>; 1129*724ba675SRob Herring #size-cells = <0>; 1130*724ba675SRob Herring }; 1131*724ba675SRob Herring 1132*724ba675SRob Herring i2c2: i2c@7003000 { 1133*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 1134*724ba675SRob Herring reg = <0x07003000 0x400>; 1135*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1136*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C2>; 1137*724ba675SRob Herring resets = <&ccu RST_BUS_I2C2>; 1138*724ba675SRob Herring status = "disabled"; 1139*724ba675SRob Herring #address-cells = <1>; 1140*724ba675SRob Herring #size-cells = <0>; 1141*724ba675SRob Herring }; 1142*724ba675SRob Herring 1143*724ba675SRob Herring i2c3: i2c@7003400 { 1144*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 1145*724ba675SRob Herring reg = <0x07003400 0x400>; 1146*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1147*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C3>; 1148*724ba675SRob Herring resets = <&ccu RST_BUS_I2C3>; 1149*724ba675SRob Herring status = "disabled"; 1150*724ba675SRob Herring #address-cells = <1>; 1151*724ba675SRob Herring #size-cells = <0>; 1152*724ba675SRob Herring }; 1153*724ba675SRob Herring 1154*724ba675SRob Herring i2c4: i2c@7003800 { 1155*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 1156*724ba675SRob Herring reg = <0x07003800 0x400>; 1157*724ba675SRob Herring interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1158*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C4>; 1159*724ba675SRob Herring resets = <&ccu RST_BUS_I2C4>; 1160*724ba675SRob Herring status = "disabled"; 1161*724ba675SRob Herring #address-cells = <1>; 1162*724ba675SRob Herring #size-cells = <0>; 1163*724ba675SRob Herring }; 1164*724ba675SRob Herring 1165*724ba675SRob Herring r_wdt: watchdog@8001000 { 1166*724ba675SRob Herring compatible = "allwinner,sun6i-a31-wdt"; 1167*724ba675SRob Herring reg = <0x08001000 0x20>; 1168*724ba675SRob Herring interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1169*724ba675SRob Herring clocks = <&osc24M>; 1170*724ba675SRob Herring }; 1171*724ba675SRob Herring 1172*724ba675SRob Herring prcm@8001400 { 1173*724ba675SRob Herring compatible = "allwinner,sun9i-a80-prcm"; 1174*724ba675SRob Herring reg = <0x08001400 0x200>; 1175*724ba675SRob Herring }; 1176*724ba675SRob Herring 1177*724ba675SRob Herring apbs_rst: reset@80014b0 { 1178*724ba675SRob Herring reg = <0x080014b0 0x4>; 1179*724ba675SRob Herring compatible = "allwinner,sun6i-a31-clock-reset"; 1180*724ba675SRob Herring #reset-cells = <1>; 1181*724ba675SRob Herring }; 1182*724ba675SRob Herring 1183*724ba675SRob Herring nmi_intc: interrupt-controller@80015a0 { 1184*724ba675SRob Herring compatible = "allwinner,sun9i-a80-nmi"; 1185*724ba675SRob Herring interrupt-controller; 1186*724ba675SRob Herring #interrupt-cells = <2>; 1187*724ba675SRob Herring reg = <0x080015a0 0xc>; 1188*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1189*724ba675SRob Herring }; 1190*724ba675SRob Herring 1191*724ba675SRob Herring r_ir: ir@8002000 { 1192*724ba675SRob Herring compatible = "allwinner,sun6i-a31-ir"; 1193*724ba675SRob Herring interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1194*724ba675SRob Herring pinctrl-names = "default"; 1195*724ba675SRob Herring pinctrl-0 = <&r_ir_pins>; 1196*724ba675SRob Herring clocks = <&apbs_gates 1>, <&r_ir_clk>; 1197*724ba675SRob Herring clock-names = "apb", "ir"; 1198*724ba675SRob Herring resets = <&apbs_rst 1>; 1199*724ba675SRob Herring reg = <0x08002000 0x40>; 1200*724ba675SRob Herring status = "disabled"; 1201*724ba675SRob Herring }; 1202*724ba675SRob Herring 1203*724ba675SRob Herring r_uart: serial@8002800 { 1204*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 1205*724ba675SRob Herring reg = <0x08002800 0x400>; 1206*724ba675SRob Herring interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1207*724ba675SRob Herring reg-shift = <2>; 1208*724ba675SRob Herring reg-io-width = <4>; 1209*724ba675SRob Herring clocks = <&apbs_gates 4>; 1210*724ba675SRob Herring resets = <&apbs_rst 4>; 1211*724ba675SRob Herring status = "disabled"; 1212*724ba675SRob Herring }; 1213*724ba675SRob Herring 1214*724ba675SRob Herring r_pio: pinctrl@8002c00 { 1215*724ba675SRob Herring compatible = "allwinner,sun9i-a80-r-pinctrl"; 1216*724ba675SRob Herring reg = <0x08002c00 0x400>; 1217*724ba675SRob Herring interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1218*724ba675SRob Herring <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1219*724ba675SRob Herring clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; 1220*724ba675SRob Herring clock-names = "apb", "hosc", "losc"; 1221*724ba675SRob Herring gpio-controller; 1222*724ba675SRob Herring interrupt-controller; 1223*724ba675SRob Herring #interrupt-cells = <3>; 1224*724ba675SRob Herring #gpio-cells = <3>; 1225*724ba675SRob Herring 1226*724ba675SRob Herring r_ir_pins: r-ir-pins { 1227*724ba675SRob Herring pins = "PL6"; 1228*724ba675SRob Herring function = "s_cir_rx"; 1229*724ba675SRob Herring }; 1230*724ba675SRob Herring 1231*724ba675SRob Herring r_rsb_pins: r-rsb-pins { 1232*724ba675SRob Herring pins = "PN0", "PN1"; 1233*724ba675SRob Herring function = "s_rsb"; 1234*724ba675SRob Herring drive-strength = <20>; 1235*724ba675SRob Herring bias-pull-up; 1236*724ba675SRob Herring }; 1237*724ba675SRob Herring }; 1238*724ba675SRob Herring 1239*724ba675SRob Herring r_rsb: rsb@8003400 { 1240*724ba675SRob Herring compatible = "allwinner,sun8i-a23-rsb"; 1241*724ba675SRob Herring reg = <0x08003400 0x400>; 1242*724ba675SRob Herring interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1243*724ba675SRob Herring clocks = <&apbs_gates 3>; 1244*724ba675SRob Herring clock-frequency = <3000000>; 1245*724ba675SRob Herring resets = <&apbs_rst 3>; 1246*724ba675SRob Herring pinctrl-names = "default"; 1247*724ba675SRob Herring pinctrl-0 = <&r_rsb_pins>; 1248*724ba675SRob Herring status = "disabled"; 1249*724ba675SRob Herring #address-cells = <1>; 1250*724ba675SRob Herring #size-cells = <0>; 1251*724ba675SRob Herring }; 1252*724ba675SRob Herring }; 1253*724ba675SRob Herring}; 1254