1*724ba675SRob Herring/* 2*724ba675SRob Herring * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> 3*724ba675SRob Herring * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org> 4*724ba675SRob Herring * 5*724ba675SRob Herring * This file is dual-licensed: you can use it either under the terms 6*724ba675SRob Herring * of the GPL or the X11 license, at your option. Note that this dual 7*724ba675SRob Herring * licensing only applies to this file, and not this project as a 8*724ba675SRob Herring * whole. 9*724ba675SRob Herring * 10*724ba675SRob Herring * a) This file is free software; you can redistribute it and/or 11*724ba675SRob Herring * modify it under the terms of the GNU General Public License as 12*724ba675SRob Herring * published by the Free Software Foundation; either version 2 of the 13*724ba675SRob Herring * License, or (at your option) any later version. 14*724ba675SRob Herring * 15*724ba675SRob Herring * This file is distributed in the hope that it will be useful, 16*724ba675SRob Herring * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*724ba675SRob Herring * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*724ba675SRob Herring * GNU General Public License for more details. 19*724ba675SRob Herring * 20*724ba675SRob Herring * Or, alternatively, 21*724ba675SRob Herring * 22*724ba675SRob Herring * b) Permission is hereby granted, free of charge, to any person 23*724ba675SRob Herring * obtaining a copy of this software and associated documentation 24*724ba675SRob Herring * files (the "Software"), to deal in the Software without 25*724ba675SRob Herring * restriction, including without limitation the rights to use, 26*724ba675SRob Herring * copy, modify, merge, publish, distribute, sublicense, and/or 27*724ba675SRob Herring * sell copies of the Software, and to permit persons to whom the 28*724ba675SRob Herring * Software is furnished to do so, subject to the following 29*724ba675SRob Herring * conditions: 30*724ba675SRob Herring * 31*724ba675SRob Herring * The above copyright notice and this permission notice shall be 32*724ba675SRob Herring * included in all copies or substantial portions of the Software. 33*724ba675SRob Herring * 34*724ba675SRob Herring * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35*724ba675SRob Herring * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36*724ba675SRob Herring * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37*724ba675SRob Herring * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38*724ba675SRob Herring * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39*724ba675SRob Herring * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40*724ba675SRob Herring * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41*724ba675SRob Herring * OTHER DEALINGS IN THE SOFTWARE. 42*724ba675SRob Herring */ 43*724ba675SRob Herring 44*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 45*724ba675SRob Herring#include <dt-bindings/clock/sun6i-rtc.h> 46*724ba675SRob Herring#include <dt-bindings/clock/sun8i-v3s-ccu.h> 47*724ba675SRob Herring#include <dt-bindings/reset/sun8i-v3s-ccu.h> 48*724ba675SRob Herring#include <dt-bindings/clock/sun8i-de2.h> 49*724ba675SRob Herring 50*724ba675SRob Herring/ { 51*724ba675SRob Herring #address-cells = <1>; 52*724ba675SRob Herring #size-cells = <1>; 53*724ba675SRob Herring interrupt-parent = <&gic>; 54*724ba675SRob Herring 55*724ba675SRob Herring chosen { 56*724ba675SRob Herring #address-cells = <1>; 57*724ba675SRob Herring #size-cells = <1>; 58*724ba675SRob Herring ranges; 59*724ba675SRob Herring 60*724ba675SRob Herring framebuffer-lcd { 61*724ba675SRob Herring compatible = "allwinner,simple-framebuffer", 62*724ba675SRob Herring "simple-framebuffer"; 63*724ba675SRob Herring allwinner,pipeline = "mixer0-lcd0"; 64*724ba675SRob Herring clocks = <&display_clocks CLK_MIXER0>, 65*724ba675SRob Herring <&ccu CLK_TCON0>; 66*724ba675SRob Herring status = "disabled"; 67*724ba675SRob Herring }; 68*724ba675SRob Herring }; 69*724ba675SRob Herring 70*724ba675SRob Herring cpus { 71*724ba675SRob Herring #address-cells = <1>; 72*724ba675SRob Herring #size-cells = <0>; 73*724ba675SRob Herring 74*724ba675SRob Herring cpu@0 { 75*724ba675SRob Herring compatible = "arm,cortex-a7"; 76*724ba675SRob Herring device_type = "cpu"; 77*724ba675SRob Herring reg = <0>; 78*724ba675SRob Herring clocks = <&ccu CLK_CPU>; 79*724ba675SRob Herring }; 80*724ba675SRob Herring }; 81*724ba675SRob Herring 82*724ba675SRob Herring de: display-engine { 83*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-display-engine"; 84*724ba675SRob Herring allwinner,pipelines = <&mixer0>; 85*724ba675SRob Herring status = "disabled"; 86*724ba675SRob Herring }; 87*724ba675SRob Herring 88*724ba675SRob Herring timer { 89*724ba675SRob Herring compatible = "arm,armv7-timer"; 90*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 91*724ba675SRob Herring <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 92*724ba675SRob Herring <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 93*724ba675SRob Herring <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 94*724ba675SRob Herring }; 95*724ba675SRob Herring 96*724ba675SRob Herring clocks { 97*724ba675SRob Herring #address-cells = <1>; 98*724ba675SRob Herring #size-cells = <1>; 99*724ba675SRob Herring ranges; 100*724ba675SRob Herring 101*724ba675SRob Herring osc24M: osc24M_clk { 102*724ba675SRob Herring #clock-cells = <0>; 103*724ba675SRob Herring compatible = "fixed-clock"; 104*724ba675SRob Herring clock-frequency = <24000000>; 105*724ba675SRob Herring clock-accuracy = <50000>; 106*724ba675SRob Herring clock-output-names = "osc24M"; 107*724ba675SRob Herring }; 108*724ba675SRob Herring 109*724ba675SRob Herring osc32k: osc32k_clk { 110*724ba675SRob Herring #clock-cells = <0>; 111*724ba675SRob Herring compatible = "fixed-clock"; 112*724ba675SRob Herring clock-frequency = <32768>; 113*724ba675SRob Herring clock-accuracy = <50000>; 114*724ba675SRob Herring clock-output-names = "ext-osc32k"; 115*724ba675SRob Herring }; 116*724ba675SRob Herring }; 117*724ba675SRob Herring 118*724ba675SRob Herring soc { 119*724ba675SRob Herring compatible = "simple-bus"; 120*724ba675SRob Herring #address-cells = <1>; 121*724ba675SRob Herring #size-cells = <1>; 122*724ba675SRob Herring ranges; 123*724ba675SRob Herring 124*724ba675SRob Herring display_clocks: clock@1000000 { 125*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-de2-clk"; 126*724ba675SRob Herring reg = <0x01000000 0x10000>; 127*724ba675SRob Herring clocks = <&ccu CLK_BUS_DE>, 128*724ba675SRob Herring <&ccu CLK_DE>; 129*724ba675SRob Herring clock-names = "bus", 130*724ba675SRob Herring "mod"; 131*724ba675SRob Herring resets = <&ccu RST_BUS_DE>; 132*724ba675SRob Herring #clock-cells = <1>; 133*724ba675SRob Herring #reset-cells = <1>; 134*724ba675SRob Herring }; 135*724ba675SRob Herring 136*724ba675SRob Herring mixer0: mixer@1100000 { 137*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-de2-mixer"; 138*724ba675SRob Herring reg = <0x01100000 0x100000>; 139*724ba675SRob Herring clocks = <&display_clocks 0>, 140*724ba675SRob Herring <&display_clocks 6>; 141*724ba675SRob Herring clock-names = "bus", 142*724ba675SRob Herring "mod"; 143*724ba675SRob Herring resets = <&display_clocks 0>; 144*724ba675SRob Herring 145*724ba675SRob Herring ports { 146*724ba675SRob Herring #address-cells = <1>; 147*724ba675SRob Herring #size-cells = <0>; 148*724ba675SRob Herring 149*724ba675SRob Herring mixer0_out: port@1 { 150*724ba675SRob Herring reg = <1>; 151*724ba675SRob Herring 152*724ba675SRob Herring mixer0_out_tcon0: endpoint { 153*724ba675SRob Herring remote-endpoint = <&tcon0_in_mixer0>; 154*724ba675SRob Herring }; 155*724ba675SRob Herring }; 156*724ba675SRob Herring }; 157*724ba675SRob Herring }; 158*724ba675SRob Herring 159*724ba675SRob Herring syscon: system-control@1c00000 { 160*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-system-control", 161*724ba675SRob Herring "allwinner,sun8i-h3-system-control"; 162*724ba675SRob Herring reg = <0x01c00000 0xd0>; 163*724ba675SRob Herring #address-cells = <1>; 164*724ba675SRob Herring #size-cells = <1>; 165*724ba675SRob Herring ranges; 166*724ba675SRob Herring }; 167*724ba675SRob Herring 168*724ba675SRob Herring nmi_intc: interrupt-controller@1c000d0 { 169*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-nmi", 170*724ba675SRob Herring "allwinner,sun9i-a80-nmi"; 171*724ba675SRob Herring interrupt-controller; 172*724ba675SRob Herring #interrupt-cells = <2>; 173*724ba675SRob Herring reg = <0x01c000d0 0x0c>; 174*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 175*724ba675SRob Herring }; 176*724ba675SRob Herring 177*724ba675SRob Herring dma: dma-controller@1c02000 { 178*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-dma"; 179*724ba675SRob Herring reg = <0x01c02000 0x1000>; 180*724ba675SRob Herring interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 181*724ba675SRob Herring clocks = <&ccu CLK_BUS_DMA>; 182*724ba675SRob Herring resets = <&ccu RST_BUS_DMA>; 183*724ba675SRob Herring #dma-cells = <1>; 184*724ba675SRob Herring }; 185*724ba675SRob Herring 186*724ba675SRob Herring tcon0: lcd-controller@1c0c000 { 187*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-tcon"; 188*724ba675SRob Herring reg = <0x01c0c000 0x1000>; 189*724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 190*724ba675SRob Herring clocks = <&ccu CLK_BUS_TCON0>, 191*724ba675SRob Herring <&ccu CLK_TCON0>; 192*724ba675SRob Herring clock-names = "ahb", 193*724ba675SRob Herring "tcon-ch0"; 194*724ba675SRob Herring clock-output-names = "tcon-data-clock"; 195*724ba675SRob Herring #clock-cells = <0>; 196*724ba675SRob Herring resets = <&ccu RST_BUS_TCON0>; 197*724ba675SRob Herring reset-names = "lcd"; 198*724ba675SRob Herring status = "disabled"; 199*724ba675SRob Herring 200*724ba675SRob Herring ports { 201*724ba675SRob Herring #address-cells = <1>; 202*724ba675SRob Herring #size-cells = <0>; 203*724ba675SRob Herring 204*724ba675SRob Herring tcon0_in: port@0 { 205*724ba675SRob Herring reg = <0>; 206*724ba675SRob Herring 207*724ba675SRob Herring tcon0_in_mixer0: endpoint { 208*724ba675SRob Herring remote-endpoint = <&mixer0_out_tcon0>; 209*724ba675SRob Herring }; 210*724ba675SRob Herring }; 211*724ba675SRob Herring 212*724ba675SRob Herring tcon0_out: port@1 { 213*724ba675SRob Herring #address-cells = <1>; 214*724ba675SRob Herring #size-cells = <0>; 215*724ba675SRob Herring reg = <1>; 216*724ba675SRob Herring }; 217*724ba675SRob Herring }; 218*724ba675SRob Herring }; 219*724ba675SRob Herring 220*724ba675SRob Herring 221*724ba675SRob Herring mmc0: mmc@1c0f000 { 222*724ba675SRob Herring compatible = "allwinner,sun7i-a20-mmc"; 223*724ba675SRob Herring reg = <0x01c0f000 0x1000>; 224*724ba675SRob Herring clocks = <&ccu CLK_BUS_MMC0>, 225*724ba675SRob Herring <&ccu CLK_MMC0>, 226*724ba675SRob Herring <&ccu CLK_MMC0_OUTPUT>, 227*724ba675SRob Herring <&ccu CLK_MMC0_SAMPLE>; 228*724ba675SRob Herring clock-names = "ahb", 229*724ba675SRob Herring "mmc", 230*724ba675SRob Herring "output", 231*724ba675SRob Herring "sample"; 232*724ba675SRob Herring resets = <&ccu RST_BUS_MMC0>; 233*724ba675SRob Herring reset-names = "ahb"; 234*724ba675SRob Herring interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 235*724ba675SRob Herring pinctrl-names = "default"; 236*724ba675SRob Herring pinctrl-0 = <&mmc0_pins>; 237*724ba675SRob Herring status = "disabled"; 238*724ba675SRob Herring #address-cells = <1>; 239*724ba675SRob Herring #size-cells = <0>; 240*724ba675SRob Herring }; 241*724ba675SRob Herring 242*724ba675SRob Herring mmc1: mmc@1c10000 { 243*724ba675SRob Herring compatible = "allwinner,sun7i-a20-mmc"; 244*724ba675SRob Herring reg = <0x01c10000 0x1000>; 245*724ba675SRob Herring clocks = <&ccu CLK_BUS_MMC1>, 246*724ba675SRob Herring <&ccu CLK_MMC1>, 247*724ba675SRob Herring <&ccu CLK_MMC1_OUTPUT>, 248*724ba675SRob Herring <&ccu CLK_MMC1_SAMPLE>; 249*724ba675SRob Herring clock-names = "ahb", 250*724ba675SRob Herring "mmc", 251*724ba675SRob Herring "output", 252*724ba675SRob Herring "sample"; 253*724ba675SRob Herring resets = <&ccu RST_BUS_MMC1>; 254*724ba675SRob Herring reset-names = "ahb"; 255*724ba675SRob Herring interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 256*724ba675SRob Herring pinctrl-names = "default"; 257*724ba675SRob Herring pinctrl-0 = <&mmc1_pins>; 258*724ba675SRob Herring status = "disabled"; 259*724ba675SRob Herring #address-cells = <1>; 260*724ba675SRob Herring #size-cells = <0>; 261*724ba675SRob Herring }; 262*724ba675SRob Herring 263*724ba675SRob Herring mmc2: mmc@1c11000 { 264*724ba675SRob Herring compatible = "allwinner,sun7i-a20-mmc"; 265*724ba675SRob Herring reg = <0x01c11000 0x1000>; 266*724ba675SRob Herring clocks = <&ccu CLK_BUS_MMC2>, 267*724ba675SRob Herring <&ccu CLK_MMC2>, 268*724ba675SRob Herring <&ccu CLK_MMC2_OUTPUT>, 269*724ba675SRob Herring <&ccu CLK_MMC2_SAMPLE>; 270*724ba675SRob Herring clock-names = "ahb", 271*724ba675SRob Herring "mmc", 272*724ba675SRob Herring "output", 273*724ba675SRob Herring "sample"; 274*724ba675SRob Herring resets = <&ccu RST_BUS_MMC2>; 275*724ba675SRob Herring reset-names = "ahb"; 276*724ba675SRob Herring interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 277*724ba675SRob Herring status = "disabled"; 278*724ba675SRob Herring #address-cells = <1>; 279*724ba675SRob Herring #size-cells = <0>; 280*724ba675SRob Herring }; 281*724ba675SRob Herring 282*724ba675SRob Herring crypto@1c15000 { 283*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-crypto", 284*724ba675SRob Herring "allwinner,sun8i-a33-crypto"; 285*724ba675SRob Herring reg = <0x01c15000 0x1000>; 286*724ba675SRob Herring interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 287*724ba675SRob Herring clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 288*724ba675SRob Herring clock-names = "ahb", "mod"; 289*724ba675SRob Herring dmas = <&dma 16>, <&dma 16>; 290*724ba675SRob Herring dma-names = "rx", "tx"; 291*724ba675SRob Herring resets = <&ccu RST_BUS_CE>; 292*724ba675SRob Herring reset-names = "ahb"; 293*724ba675SRob Herring }; 294*724ba675SRob Herring 295*724ba675SRob Herring usb_otg: usb@1c19000 { 296*724ba675SRob Herring compatible = "allwinner,sun8i-h3-musb"; 297*724ba675SRob Herring reg = <0x01c19000 0x0400>; 298*724ba675SRob Herring clocks = <&ccu CLK_BUS_OTG>; 299*724ba675SRob Herring resets = <&ccu RST_BUS_OTG>; 300*724ba675SRob Herring interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 301*724ba675SRob Herring interrupt-names = "mc"; 302*724ba675SRob Herring phys = <&usbphy 0>; 303*724ba675SRob Herring phy-names = "usb"; 304*724ba675SRob Herring extcon = <&usbphy 0>; 305*724ba675SRob Herring status = "disabled"; 306*724ba675SRob Herring }; 307*724ba675SRob Herring 308*724ba675SRob Herring usbphy: phy@1c19400 { 309*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-usb-phy"; 310*724ba675SRob Herring reg = <0x01c19400 0x2c>, 311*724ba675SRob Herring <0x01c1a800 0x4>; 312*724ba675SRob Herring reg-names = "phy_ctrl", 313*724ba675SRob Herring "pmu0"; 314*724ba675SRob Herring clocks = <&ccu CLK_USB_PHY0>; 315*724ba675SRob Herring clock-names = "usb0_phy"; 316*724ba675SRob Herring resets = <&ccu RST_USB_PHY0>; 317*724ba675SRob Herring reset-names = "usb0_reset"; 318*724ba675SRob Herring status = "disabled"; 319*724ba675SRob Herring #phy-cells = <1>; 320*724ba675SRob Herring }; 321*724ba675SRob Herring 322*724ba675SRob Herring ccu: clock@1c20000 { 323*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-ccu"; 324*724ba675SRob Herring reg = <0x01c20000 0x400>; 325*724ba675SRob Herring clocks = <&osc24M>, <&rtc CLK_OSC32K>; 326*724ba675SRob Herring clock-names = "hosc", "losc"; 327*724ba675SRob Herring #clock-cells = <1>; 328*724ba675SRob Herring #reset-cells = <1>; 329*724ba675SRob Herring }; 330*724ba675SRob Herring 331*724ba675SRob Herring rtc: rtc@1c20400 { 332*724ba675SRob Herring #clock-cells = <1>; 333*724ba675SRob Herring compatible = "allwinner,sun8i-v3-rtc"; 334*724ba675SRob Herring reg = <0x01c20400 0x54>; 335*724ba675SRob Herring interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 336*724ba675SRob Herring <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 337*724ba675SRob Herring clocks = <&osc32k>; 338*724ba675SRob Herring clock-output-names = "osc32k", "osc32k-out"; 339*724ba675SRob Herring }; 340*724ba675SRob Herring 341*724ba675SRob Herring pio: pinctrl@1c20800 { 342*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-pinctrl"; 343*724ba675SRob Herring reg = <0x01c20800 0x400>; 344*724ba675SRob Herring interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 345*724ba675SRob Herring <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 346*724ba675SRob Herring clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 347*724ba675SRob Herring <&rtc CLK_OSC32K>; 348*724ba675SRob Herring clock-names = "apb", "hosc", "losc"; 349*724ba675SRob Herring gpio-controller; 350*724ba675SRob Herring #gpio-cells = <3>; 351*724ba675SRob Herring interrupt-controller; 352*724ba675SRob Herring #interrupt-cells = <3>; 353*724ba675SRob Herring 354*724ba675SRob Herring /omit-if-no-ref/ 355*724ba675SRob Herring csi0_mclk_pin: csi0-mclk-pin { 356*724ba675SRob Herring pins = "PE20"; 357*724ba675SRob Herring function = "csi_mipi"; 358*724ba675SRob Herring }; 359*724ba675SRob Herring 360*724ba675SRob Herring /omit-if-no-ref/ 361*724ba675SRob Herring csi1_8bit_pins: csi1-8bit-pins { 362*724ba675SRob Herring pins = "PE0", "PE2", "PE3", "PE8", "PE9", 363*724ba675SRob Herring "PE10", "PE11", "PE12", "PE13", "PE14", 364*724ba675SRob Herring "PE15"; 365*724ba675SRob Herring function = "csi"; 366*724ba675SRob Herring }; 367*724ba675SRob Herring 368*724ba675SRob Herring /omit-if-no-ref/ 369*724ba675SRob Herring csi1_mclk_pin: csi1-mclk-pin { 370*724ba675SRob Herring pins = "PE1"; 371*724ba675SRob Herring function = "csi"; 372*724ba675SRob Herring }; 373*724ba675SRob Herring 374*724ba675SRob Herring i2c0_pins: i2c0-pins { 375*724ba675SRob Herring pins = "PB6", "PB7"; 376*724ba675SRob Herring function = "i2c0"; 377*724ba675SRob Herring }; 378*724ba675SRob Herring 379*724ba675SRob Herring /omit-if-no-ref/ 380*724ba675SRob Herring i2c1_pb_pins: i2c1-pb-pins { 381*724ba675SRob Herring pins = "PB8", "PB9"; 382*724ba675SRob Herring function = "i2c1"; 383*724ba675SRob Herring }; 384*724ba675SRob Herring 385*724ba675SRob Herring /omit-if-no-ref/ 386*724ba675SRob Herring i2c1_pe_pins: i2c1-pe-pins { 387*724ba675SRob Herring pins = "PE21", "PE22"; 388*724ba675SRob Herring function = "i2c1"; 389*724ba675SRob Herring }; 390*724ba675SRob Herring 391*724ba675SRob Herring uart0_pb_pins: uart0-pb-pins { 392*724ba675SRob Herring pins = "PB8", "PB9"; 393*724ba675SRob Herring function = "uart0"; 394*724ba675SRob Herring }; 395*724ba675SRob Herring 396*724ba675SRob Herring uart2_pins: uart2-pins { 397*724ba675SRob Herring pins = "PB0", "PB1"; 398*724ba675SRob Herring function = "uart2"; 399*724ba675SRob Herring }; 400*724ba675SRob Herring 401*724ba675SRob Herring mmc0_pins: mmc0-pins { 402*724ba675SRob Herring pins = "PF0", "PF1", "PF2", "PF3", 403*724ba675SRob Herring "PF4", "PF5"; 404*724ba675SRob Herring function = "mmc0"; 405*724ba675SRob Herring drive-strength = <30>; 406*724ba675SRob Herring bias-pull-up; 407*724ba675SRob Herring }; 408*724ba675SRob Herring 409*724ba675SRob Herring mmc1_pins: mmc1-pins { 410*724ba675SRob Herring pins = "PG0", "PG1", "PG2", "PG3", 411*724ba675SRob Herring "PG4", "PG5"; 412*724ba675SRob Herring function = "mmc1"; 413*724ba675SRob Herring drive-strength = <30>; 414*724ba675SRob Herring bias-pull-up; 415*724ba675SRob Herring }; 416*724ba675SRob Herring 417*724ba675SRob Herring spi0_pins: spi0-pins { 418*724ba675SRob Herring pins = "PC0", "PC1", "PC2", "PC3"; 419*724ba675SRob Herring function = "spi0"; 420*724ba675SRob Herring }; 421*724ba675SRob Herring }; 422*724ba675SRob Herring 423*724ba675SRob Herring timer@1c20c00 { 424*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-timer"; 425*724ba675SRob Herring reg = <0x01c20c00 0xa0>; 426*724ba675SRob Herring interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 427*724ba675SRob Herring <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 428*724ba675SRob Herring <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 429*724ba675SRob Herring clocks = <&osc24M>; 430*724ba675SRob Herring }; 431*724ba675SRob Herring 432*724ba675SRob Herring wdt0: watchdog@1c20ca0 { 433*724ba675SRob Herring compatible = "allwinner,sun6i-a31-wdt"; 434*724ba675SRob Herring reg = <0x01c20ca0 0x20>; 435*724ba675SRob Herring interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 436*724ba675SRob Herring clocks = <&osc24M>; 437*724ba675SRob Herring }; 438*724ba675SRob Herring 439*724ba675SRob Herring pwm: pwm@1c21400 { 440*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-pwm", 441*724ba675SRob Herring "allwinner,sun7i-a20-pwm"; 442*724ba675SRob Herring reg = <0x01c21400 0xc>; 443*724ba675SRob Herring clocks = <&osc24M>; 444*724ba675SRob Herring #pwm-cells = <3>; 445*724ba675SRob Herring status = "disabled"; 446*724ba675SRob Herring }; 447*724ba675SRob Herring 448*724ba675SRob Herring lradc: lradc@1c22800 { 449*724ba675SRob Herring compatible = "allwinner,sun4i-a10-lradc-keys"; 450*724ba675SRob Herring reg = <0x01c22800 0x400>; 451*724ba675SRob Herring interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 452*724ba675SRob Herring status = "disabled"; 453*724ba675SRob Herring }; 454*724ba675SRob Herring 455*724ba675SRob Herring codec: codec@1c22c00 { 456*724ba675SRob Herring #sound-dai-cells = <0>; 457*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-codec"; 458*724ba675SRob Herring reg = <0x01c22c00 0x400>; 459*724ba675SRob Herring interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 460*724ba675SRob Herring clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 461*724ba675SRob Herring clock-names = "apb", "codec"; 462*724ba675SRob Herring resets = <&ccu RST_BUS_CODEC>; 463*724ba675SRob Herring dmas = <&dma 15>, <&dma 15>; 464*724ba675SRob Herring dma-names = "rx", "tx"; 465*724ba675SRob Herring allwinner,codec-analog-controls = <&codec_analog>; 466*724ba675SRob Herring status = "disabled"; 467*724ba675SRob Herring }; 468*724ba675SRob Herring 469*724ba675SRob Herring codec_analog: codec-analog@1c23000 { 470*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-codec-analog"; 471*724ba675SRob Herring reg = <0x01c23000 0x4>; 472*724ba675SRob Herring }; 473*724ba675SRob Herring 474*724ba675SRob Herring uart0: serial@1c28000 { 475*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 476*724ba675SRob Herring reg = <0x01c28000 0x400>; 477*724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 478*724ba675SRob Herring reg-shift = <2>; 479*724ba675SRob Herring reg-io-width = <4>; 480*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART0>; 481*724ba675SRob Herring dmas = <&dma 6>, <&dma 6>; 482*724ba675SRob Herring dma-names = "tx", "rx"; 483*724ba675SRob Herring resets = <&ccu RST_BUS_UART0>; 484*724ba675SRob Herring status = "disabled"; 485*724ba675SRob Herring }; 486*724ba675SRob Herring 487*724ba675SRob Herring uart1: serial@1c28400 { 488*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 489*724ba675SRob Herring reg = <0x01c28400 0x400>; 490*724ba675SRob Herring interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 491*724ba675SRob Herring reg-shift = <2>; 492*724ba675SRob Herring reg-io-width = <4>; 493*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART1>; 494*724ba675SRob Herring dmas = <&dma 7>, <&dma 7>; 495*724ba675SRob Herring dma-names = "tx", "rx"; 496*724ba675SRob Herring resets = <&ccu RST_BUS_UART1>; 497*724ba675SRob Herring status = "disabled"; 498*724ba675SRob Herring }; 499*724ba675SRob Herring 500*724ba675SRob Herring uart2: serial@1c28800 { 501*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 502*724ba675SRob Herring reg = <0x01c28800 0x400>; 503*724ba675SRob Herring interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 504*724ba675SRob Herring reg-shift = <2>; 505*724ba675SRob Herring reg-io-width = <4>; 506*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART2>; 507*724ba675SRob Herring dmas = <&dma 8>, <&dma 8>; 508*724ba675SRob Herring dma-names = "tx", "rx"; 509*724ba675SRob Herring resets = <&ccu RST_BUS_UART2>; 510*724ba675SRob Herring pinctrl-0 = <&uart2_pins>; 511*724ba675SRob Herring pinctrl-names = "default"; 512*724ba675SRob Herring status = "disabled"; 513*724ba675SRob Herring }; 514*724ba675SRob Herring 515*724ba675SRob Herring i2c0: i2c@1c2ac00 { 516*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 517*724ba675SRob Herring reg = <0x01c2ac00 0x400>; 518*724ba675SRob Herring interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 519*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C0>; 520*724ba675SRob Herring resets = <&ccu RST_BUS_I2C0>; 521*724ba675SRob Herring pinctrl-names = "default"; 522*724ba675SRob Herring pinctrl-0 = <&i2c0_pins>; 523*724ba675SRob Herring status = "disabled"; 524*724ba675SRob Herring #address-cells = <1>; 525*724ba675SRob Herring #size-cells = <0>; 526*724ba675SRob Herring }; 527*724ba675SRob Herring 528*724ba675SRob Herring i2c1: i2c@1c2b000 { 529*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 530*724ba675SRob Herring reg = <0x01c2b000 0x400>; 531*724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 532*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C1>; 533*724ba675SRob Herring resets = <&ccu RST_BUS_I2C1>; 534*724ba675SRob Herring status = "disabled"; 535*724ba675SRob Herring #address-cells = <1>; 536*724ba675SRob Herring #size-cells = <0>; 537*724ba675SRob Herring }; 538*724ba675SRob Herring 539*724ba675SRob Herring emac: ethernet@1c30000 { 540*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-emac"; 541*724ba675SRob Herring syscon = <&syscon>; 542*724ba675SRob Herring reg = <0x01c30000 0x10000>; 543*724ba675SRob Herring interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 544*724ba675SRob Herring interrupt-names = "macirq"; 545*724ba675SRob Herring resets = <&ccu RST_BUS_EMAC>; 546*724ba675SRob Herring reset-names = "stmmaceth"; 547*724ba675SRob Herring clocks = <&ccu CLK_BUS_EMAC>; 548*724ba675SRob Herring clock-names = "stmmaceth"; 549*724ba675SRob Herring phy-handle = <&int_mii_phy>; 550*724ba675SRob Herring phy-mode = "mii"; 551*724ba675SRob Herring status = "disabled"; 552*724ba675SRob Herring 553*724ba675SRob Herring mdio: mdio { 554*724ba675SRob Herring #address-cells = <1>; 555*724ba675SRob Herring #size-cells = <0>; 556*724ba675SRob Herring compatible = "snps,dwmac-mdio"; 557*724ba675SRob Herring }; 558*724ba675SRob Herring 559*724ba675SRob Herring mdio_mux: mdio-mux { 560*724ba675SRob Herring compatible = "allwinner,sun8i-h3-mdio-mux"; 561*724ba675SRob Herring #address-cells = <1>; 562*724ba675SRob Herring #size-cells = <0>; 563*724ba675SRob Herring 564*724ba675SRob Herring mdio-parent-bus = <&mdio>; 565*724ba675SRob Herring /* Only one MDIO is usable at the time */ 566*724ba675SRob Herring internal_mdio: mdio@1 { 567*724ba675SRob Herring compatible = "allwinner,sun8i-h3-mdio-internal"; 568*724ba675SRob Herring reg = <1>; 569*724ba675SRob Herring #address-cells = <1>; 570*724ba675SRob Herring #size-cells = <0>; 571*724ba675SRob Herring 572*724ba675SRob Herring int_mii_phy: ethernet-phy@1 { 573*724ba675SRob Herring compatible = "ethernet-phy-ieee802.3-c22"; 574*724ba675SRob Herring reg = <1>; 575*724ba675SRob Herring clocks = <&ccu CLK_BUS_EPHY>; 576*724ba675SRob Herring resets = <&ccu RST_BUS_EPHY>; 577*724ba675SRob Herring }; 578*724ba675SRob Herring }; 579*724ba675SRob Herring }; 580*724ba675SRob Herring }; 581*724ba675SRob Herring 582*724ba675SRob Herring spi0: spi@1c68000 { 583*724ba675SRob Herring compatible = "allwinner,sun8i-h3-spi"; 584*724ba675SRob Herring reg = <0x01c68000 0x1000>; 585*724ba675SRob Herring interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 586*724ba675SRob Herring clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 587*724ba675SRob Herring clock-names = "ahb", "mod"; 588*724ba675SRob Herring dmas = <&dma 23>, <&dma 23>; 589*724ba675SRob Herring dma-names = "rx", "tx"; 590*724ba675SRob Herring pinctrl-names = "default"; 591*724ba675SRob Herring pinctrl-0 = <&spi0_pins>; 592*724ba675SRob Herring resets = <&ccu RST_BUS_SPI0>; 593*724ba675SRob Herring status = "disabled"; 594*724ba675SRob Herring #address-cells = <1>; 595*724ba675SRob Herring #size-cells = <0>; 596*724ba675SRob Herring }; 597*724ba675SRob Herring 598*724ba675SRob Herring gic: interrupt-controller@1c81000 { 599*724ba675SRob Herring compatible = "arm,gic-400"; 600*724ba675SRob Herring reg = <0x01c81000 0x1000>, 601*724ba675SRob Herring <0x01c82000 0x2000>, 602*724ba675SRob Herring <0x01c84000 0x2000>, 603*724ba675SRob Herring <0x01c86000 0x2000>; 604*724ba675SRob Herring interrupt-controller; 605*724ba675SRob Herring #interrupt-cells = <3>; 606*724ba675SRob Herring interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 607*724ba675SRob Herring }; 608*724ba675SRob Herring 609*724ba675SRob Herring csi1: camera@1cb4000 { 610*724ba675SRob Herring compatible = "allwinner,sun8i-v3s-csi"; 611*724ba675SRob Herring reg = <0x01cb4000 0x3000>; 612*724ba675SRob Herring interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 613*724ba675SRob Herring clocks = <&ccu CLK_BUS_CSI>, 614*724ba675SRob Herring <&ccu CLK_CSI1_SCLK>, 615*724ba675SRob Herring <&ccu CLK_DRAM_CSI>; 616*724ba675SRob Herring clock-names = "bus", "mod", "ram"; 617*724ba675SRob Herring resets = <&ccu RST_BUS_CSI>; 618*724ba675SRob Herring status = "disabled"; 619*724ba675SRob Herring }; 620*724ba675SRob Herring }; 621*724ba675SRob Herring}; 622