1*724ba675SRob Herring/* 2*724ba675SRob Herring * Copyright 2017 Chen-Yu Tsai <wens@csie.org> 3*724ba675SRob Herring * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 4*724ba675SRob Herring * 5*724ba675SRob Herring * This file is dual-licensed: you can use it either under the terms 6*724ba675SRob Herring * of the GPL or the X11 license, at your option. Note that this dual 7*724ba675SRob Herring * licensing only applies to this file, and not this project as a 8*724ba675SRob Herring * whole. 9*724ba675SRob Herring * 10*724ba675SRob Herring * a) This file is free software; you can redistribute it and/or 11*724ba675SRob Herring * modify it under the terms of the GNU General Public License as 12*724ba675SRob Herring * published by the Free Software Foundation; either version 2 of the 13*724ba675SRob Herring * License, or (at your option) any later version. 14*724ba675SRob Herring * 15*724ba675SRob Herring * This file is distributed in the hope that it will be useful, 16*724ba675SRob Herring * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*724ba675SRob Herring * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*724ba675SRob Herring * GNU General Public License for more details. 19*724ba675SRob Herring * 20*724ba675SRob Herring * Or, alternatively, 21*724ba675SRob Herring * 22*724ba675SRob Herring * b) Permission is hereby granted, free of charge, to any person 23*724ba675SRob Herring * obtaining a copy of this software and associated documentation 24*724ba675SRob Herring * files (the "Software"), to deal in the Software without 25*724ba675SRob Herring * restriction, including without limitation the rights to use, 26*724ba675SRob Herring * copy, modify, merge, publish, distribute, sublicense, and/or 27*724ba675SRob Herring * sell copies of the Software, and to permit persons to whom the 28*724ba675SRob Herring * Software is furnished to do so, subject to the following 29*724ba675SRob Herring * conditions: 30*724ba675SRob Herring * 31*724ba675SRob Herring * The above copyright notice and this permission notice shall be 32*724ba675SRob Herring * included in all copies or substantial portions of the Software. 33*724ba675SRob Herring * 34*724ba675SRob Herring * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35*724ba675SRob Herring * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36*724ba675SRob Herring * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37*724ba675SRob Herring * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38*724ba675SRob Herring * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39*724ba675SRob Herring * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40*724ba675SRob Herring * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41*724ba675SRob Herring * OTHER DEALINGS IN THE SOFTWARE. 42*724ba675SRob Herring */ 43*724ba675SRob Herring 44*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 45*724ba675SRob Herring#include <dt-bindings/clock/sun6i-rtc.h> 46*724ba675SRob Herring#include <dt-bindings/clock/sun8i-de2.h> 47*724ba675SRob Herring#include <dt-bindings/clock/sun8i-r40-ccu.h> 48*724ba675SRob Herring#include <dt-bindings/clock/sun8i-tcon-top.h> 49*724ba675SRob Herring#include <dt-bindings/reset/sun8i-r40-ccu.h> 50*724ba675SRob Herring#include <dt-bindings/reset/sun8i-de2.h> 51*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h> 52*724ba675SRob Herring 53*724ba675SRob Herring/ { 54*724ba675SRob Herring #address-cells = <1>; 55*724ba675SRob Herring #size-cells = <1>; 56*724ba675SRob Herring interrupt-parent = <&gic>; 57*724ba675SRob Herring 58*724ba675SRob Herring clocks { 59*724ba675SRob Herring #address-cells = <1>; 60*724ba675SRob Herring #size-cells = <1>; 61*724ba675SRob Herring ranges; 62*724ba675SRob Herring 63*724ba675SRob Herring osc24M: osc24M { 64*724ba675SRob Herring #clock-cells = <0>; 65*724ba675SRob Herring compatible = "fixed-clock"; 66*724ba675SRob Herring clock-frequency = <24000000>; 67*724ba675SRob Herring clock-accuracy = <50000>; 68*724ba675SRob Herring clock-output-names = "osc24M"; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring osc32k: osc32k { 72*724ba675SRob Herring #clock-cells = <0>; 73*724ba675SRob Herring compatible = "fixed-clock"; 74*724ba675SRob Herring clock-frequency = <32768>; 75*724ba675SRob Herring clock-accuracy = <20000>; 76*724ba675SRob Herring clock-output-names = "ext-osc32k"; 77*724ba675SRob Herring }; 78*724ba675SRob Herring }; 79*724ba675SRob Herring 80*724ba675SRob Herring cpus { 81*724ba675SRob Herring #address-cells = <1>; 82*724ba675SRob Herring #size-cells = <0>; 83*724ba675SRob Herring 84*724ba675SRob Herring cpu0: cpu@0 { 85*724ba675SRob Herring compatible = "arm,cortex-a7"; 86*724ba675SRob Herring device_type = "cpu"; 87*724ba675SRob Herring reg = <0>; 88*724ba675SRob Herring clocks = <&ccu CLK_CPU>; 89*724ba675SRob Herring clock-names = "cpu"; 90*724ba675SRob Herring #cooling-cells = <2>; 91*724ba675SRob Herring }; 92*724ba675SRob Herring 93*724ba675SRob Herring cpu1: cpu@1 { 94*724ba675SRob Herring compatible = "arm,cortex-a7"; 95*724ba675SRob Herring device_type = "cpu"; 96*724ba675SRob Herring reg = <1>; 97*724ba675SRob Herring clocks = <&ccu CLK_CPU>; 98*724ba675SRob Herring clock-names = "cpu"; 99*724ba675SRob Herring #cooling-cells = <2>; 100*724ba675SRob Herring }; 101*724ba675SRob Herring 102*724ba675SRob Herring cpu2: cpu@2 { 103*724ba675SRob Herring compatible = "arm,cortex-a7"; 104*724ba675SRob Herring device_type = "cpu"; 105*724ba675SRob Herring reg = <2>; 106*724ba675SRob Herring clocks = <&ccu CLK_CPU>; 107*724ba675SRob Herring clock-names = "cpu"; 108*724ba675SRob Herring #cooling-cells = <2>; 109*724ba675SRob Herring }; 110*724ba675SRob Herring 111*724ba675SRob Herring cpu3: cpu@3 { 112*724ba675SRob Herring compatible = "arm,cortex-a7"; 113*724ba675SRob Herring device_type = "cpu"; 114*724ba675SRob Herring reg = <3>; 115*724ba675SRob Herring clocks = <&ccu CLK_CPU>; 116*724ba675SRob Herring clock-names = "cpu"; 117*724ba675SRob Herring #cooling-cells = <2>; 118*724ba675SRob Herring }; 119*724ba675SRob Herring }; 120*724ba675SRob Herring 121*724ba675SRob Herring de: display-engine { 122*724ba675SRob Herring compatible = "allwinner,sun8i-r40-display-engine"; 123*724ba675SRob Herring allwinner,pipelines = <&mixer0>, <&mixer1>; 124*724ba675SRob Herring status = "disabled"; 125*724ba675SRob Herring }; 126*724ba675SRob Herring 127*724ba675SRob Herring thermal-zones { 128*724ba675SRob Herring cpu_thermal: cpu0-thermal { 129*724ba675SRob Herring /* milliseconds */ 130*724ba675SRob Herring polling-delay-passive = <0>; 131*724ba675SRob Herring polling-delay = <0>; 132*724ba675SRob Herring thermal-sensors = <&ths 0>; 133*724ba675SRob Herring 134*724ba675SRob Herring trips { 135*724ba675SRob Herring cpu_hot_trip: cpu-hot { 136*724ba675SRob Herring temperature = <80000>; 137*724ba675SRob Herring hysteresis = <2000>; 138*724ba675SRob Herring type = "passive"; 139*724ba675SRob Herring }; 140*724ba675SRob Herring 141*724ba675SRob Herring cpu_very_hot_trip: cpu-very-hot { 142*724ba675SRob Herring temperature = <115000>; 143*724ba675SRob Herring hysteresis = <0>; 144*724ba675SRob Herring type = "critical"; 145*724ba675SRob Herring }; 146*724ba675SRob Herring }; 147*724ba675SRob Herring 148*724ba675SRob Herring cooling-maps { 149*724ba675SRob Herring cpu-hot-limit { 150*724ba675SRob Herring trip = <&cpu_hot_trip>; 151*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 152*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 153*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 154*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 155*724ba675SRob Herring }; 156*724ba675SRob Herring }; 157*724ba675SRob Herring }; 158*724ba675SRob Herring 159*724ba675SRob Herring gpu_thermal: gpu-thermal { 160*724ba675SRob Herring /* milliseconds */ 161*724ba675SRob Herring polling-delay-passive = <0>; 162*724ba675SRob Herring polling-delay = <0>; 163*724ba675SRob Herring thermal-sensors = <&ths 1>; 164*724ba675SRob Herring }; 165*724ba675SRob Herring }; 166*724ba675SRob Herring 167*724ba675SRob Herring soc { 168*724ba675SRob Herring compatible = "simple-bus"; 169*724ba675SRob Herring #address-cells = <1>; 170*724ba675SRob Herring #size-cells = <1>; 171*724ba675SRob Herring ranges; 172*724ba675SRob Herring 173*724ba675SRob Herring display_clocks: clock@1000000 { 174*724ba675SRob Herring compatible = "allwinner,sun8i-r40-de2-clk", 175*724ba675SRob Herring "allwinner,sun8i-h3-de2-clk"; 176*724ba675SRob Herring reg = <0x01000000 0x10000>; 177*724ba675SRob Herring clocks = <&ccu CLK_BUS_DE>, 178*724ba675SRob Herring <&ccu CLK_DE>; 179*724ba675SRob Herring clock-names = "bus", 180*724ba675SRob Herring "mod"; 181*724ba675SRob Herring resets = <&ccu RST_BUS_DE>; 182*724ba675SRob Herring #clock-cells = <1>; 183*724ba675SRob Herring #reset-cells = <1>; 184*724ba675SRob Herring }; 185*724ba675SRob Herring 186*724ba675SRob Herring mixer0: mixer@1100000 { 187*724ba675SRob Herring compatible = "allwinner,sun8i-r40-de2-mixer-0"; 188*724ba675SRob Herring reg = <0x01100000 0x100000>; 189*724ba675SRob Herring clocks = <&display_clocks CLK_BUS_MIXER0>, 190*724ba675SRob Herring <&display_clocks CLK_MIXER0>; 191*724ba675SRob Herring clock-names = "bus", 192*724ba675SRob Herring "mod"; 193*724ba675SRob Herring resets = <&display_clocks RST_MIXER0>; 194*724ba675SRob Herring 195*724ba675SRob Herring ports { 196*724ba675SRob Herring #address-cells = <1>; 197*724ba675SRob Herring #size-cells = <0>; 198*724ba675SRob Herring 199*724ba675SRob Herring mixer0_out: port@1 { 200*724ba675SRob Herring reg = <1>; 201*724ba675SRob Herring mixer0_out_tcon_top: endpoint { 202*724ba675SRob Herring remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 203*724ba675SRob Herring }; 204*724ba675SRob Herring }; 205*724ba675SRob Herring }; 206*724ba675SRob Herring }; 207*724ba675SRob Herring 208*724ba675SRob Herring mixer1: mixer@1200000 { 209*724ba675SRob Herring compatible = "allwinner,sun8i-r40-de2-mixer-1"; 210*724ba675SRob Herring reg = <0x01200000 0x100000>; 211*724ba675SRob Herring clocks = <&display_clocks CLK_BUS_MIXER1>, 212*724ba675SRob Herring <&display_clocks CLK_MIXER1>; 213*724ba675SRob Herring clock-names = "bus", 214*724ba675SRob Herring "mod"; 215*724ba675SRob Herring resets = <&display_clocks RST_WB>; 216*724ba675SRob Herring 217*724ba675SRob Herring ports { 218*724ba675SRob Herring #address-cells = <1>; 219*724ba675SRob Herring #size-cells = <0>; 220*724ba675SRob Herring 221*724ba675SRob Herring mixer1_out: port@1 { 222*724ba675SRob Herring reg = <1>; 223*724ba675SRob Herring mixer1_out_tcon_top: endpoint { 224*724ba675SRob Herring remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 225*724ba675SRob Herring }; 226*724ba675SRob Herring }; 227*724ba675SRob Herring }; 228*724ba675SRob Herring }; 229*724ba675SRob Herring 230*724ba675SRob Herring deinterlace: deinterlace@1400000 { 231*724ba675SRob Herring compatible = "allwinner,sun8i-r40-deinterlace", 232*724ba675SRob Herring "allwinner,sun8i-h3-deinterlace"; 233*724ba675SRob Herring reg = <0x01400000 0x20000>; 234*724ba675SRob Herring clocks = <&ccu CLK_BUS_DEINTERLACE>, 235*724ba675SRob Herring <&ccu CLK_DEINTERLACE>, 236*724ba675SRob Herring /* 237*724ba675SRob Herring * NOTE: Contrary to what datasheet claims, 238*724ba675SRob Herring * DRAM deinterlace gate doesn't exist and 239*724ba675SRob Herring * it's shared with CSI1. 240*724ba675SRob Herring */ 241*724ba675SRob Herring <&ccu CLK_DRAM_CSI1>; 242*724ba675SRob Herring clock-names = "bus", "mod", "ram"; 243*724ba675SRob Herring resets = <&ccu RST_BUS_DEINTERLACE>; 244*724ba675SRob Herring interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 245*724ba675SRob Herring interconnects = <&mbus 9>; 246*724ba675SRob Herring interconnect-names = "dma-mem"; 247*724ba675SRob Herring }; 248*724ba675SRob Herring 249*724ba675SRob Herring syscon: system-control@1c00000 { 250*724ba675SRob Herring compatible = "allwinner,sun8i-r40-system-control", 251*724ba675SRob Herring "allwinner,sun4i-a10-system-control"; 252*724ba675SRob Herring reg = <0x01c00000 0x30>; 253*724ba675SRob Herring #address-cells = <1>; 254*724ba675SRob Herring #size-cells = <1>; 255*724ba675SRob Herring ranges; 256*724ba675SRob Herring 257*724ba675SRob Herring sram_c: sram@1d00000 { 258*724ba675SRob Herring compatible = "mmio-sram"; 259*724ba675SRob Herring reg = <0x01d00000 0xd0000>; 260*724ba675SRob Herring #address-cells = <1>; 261*724ba675SRob Herring #size-cells = <1>; 262*724ba675SRob Herring ranges = <0 0x01d00000 0xd0000>; 263*724ba675SRob Herring 264*724ba675SRob Herring ve_sram: sram-section@0 { 265*724ba675SRob Herring compatible = "allwinner,sun8i-r40-sram-c1", 266*724ba675SRob Herring "allwinner,sun4i-a10-sram-c1"; 267*724ba675SRob Herring reg = <0x000000 0x80000>; 268*724ba675SRob Herring }; 269*724ba675SRob Herring }; 270*724ba675SRob Herring }; 271*724ba675SRob Herring 272*724ba675SRob Herring nmi_intc: interrupt-controller@1c00030 { 273*724ba675SRob Herring compatible = "allwinner,sun7i-a20-sc-nmi"; 274*724ba675SRob Herring interrupt-controller; 275*724ba675SRob Herring #interrupt-cells = <2>; 276*724ba675SRob Herring reg = <0x01c00030 0x0c>; 277*724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 278*724ba675SRob Herring }; 279*724ba675SRob Herring 280*724ba675SRob Herring dma: dma-controller@1c02000 { 281*724ba675SRob Herring compatible = "allwinner,sun8i-r40-dma", 282*724ba675SRob Herring "allwinner,sun50i-a64-dma"; 283*724ba675SRob Herring reg = <0x01c02000 0x1000>; 284*724ba675SRob Herring interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 285*724ba675SRob Herring clocks = <&ccu CLK_BUS_DMA>; 286*724ba675SRob Herring dma-channels = <16>; 287*724ba675SRob Herring dma-requests = <31>; 288*724ba675SRob Herring resets = <&ccu RST_BUS_DMA>; 289*724ba675SRob Herring #dma-cells = <1>; 290*724ba675SRob Herring }; 291*724ba675SRob Herring 292*724ba675SRob Herring spi0: spi@1c05000 { 293*724ba675SRob Herring compatible = "allwinner,sun8i-r40-spi", 294*724ba675SRob Herring "allwinner,sun8i-h3-spi"; 295*724ba675SRob Herring reg = <0x01c05000 0x1000>; 296*724ba675SRob Herring interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 297*724ba675SRob Herring clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 298*724ba675SRob Herring clock-names = "ahb", "mod"; 299*724ba675SRob Herring resets = <&ccu RST_BUS_SPI0>; 300*724ba675SRob Herring status = "disabled"; 301*724ba675SRob Herring #address-cells = <1>; 302*724ba675SRob Herring #size-cells = <0>; 303*724ba675SRob Herring }; 304*724ba675SRob Herring 305*724ba675SRob Herring spi1: spi@1c06000 { 306*724ba675SRob Herring compatible = "allwinner,sun8i-r40-spi", 307*724ba675SRob Herring "allwinner,sun8i-h3-spi"; 308*724ba675SRob Herring reg = <0x01c06000 0x1000>; 309*724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 310*724ba675SRob Herring clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 311*724ba675SRob Herring clock-names = "ahb", "mod"; 312*724ba675SRob Herring resets = <&ccu RST_BUS_SPI1>; 313*724ba675SRob Herring status = "disabled"; 314*724ba675SRob Herring #address-cells = <1>; 315*724ba675SRob Herring #size-cells = <0>; 316*724ba675SRob Herring }; 317*724ba675SRob Herring 318*724ba675SRob Herring csi0: csi@1c09000 { 319*724ba675SRob Herring compatible = "allwinner,sun8i-r40-csi0", 320*724ba675SRob Herring "allwinner,sun7i-a20-csi0"; 321*724ba675SRob Herring reg = <0x01c09000 0x1000>; 322*724ba675SRob Herring interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 323*724ba675SRob Herring clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>, 324*724ba675SRob Herring <&ccu CLK_DRAM_CSI0>; 325*724ba675SRob Herring clock-names = "bus", "isp", "ram"; 326*724ba675SRob Herring resets = <&ccu RST_BUS_CSI0>; 327*724ba675SRob Herring interconnects = <&mbus 5>; 328*724ba675SRob Herring interconnect-names = "dma-mem"; 329*724ba675SRob Herring status = "disabled"; 330*724ba675SRob Herring }; 331*724ba675SRob Herring 332*724ba675SRob Herring video-codec@1c0e000 { 333*724ba675SRob Herring compatible = "allwinner,sun8i-r40-video-engine"; 334*724ba675SRob Herring reg = <0x01c0e000 0x1000>; 335*724ba675SRob Herring clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 336*724ba675SRob Herring <&ccu CLK_DRAM_VE>; 337*724ba675SRob Herring clock-names = "ahb", "mod", "ram"; 338*724ba675SRob Herring resets = <&ccu RST_BUS_VE>; 339*724ba675SRob Herring interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 340*724ba675SRob Herring allwinner,sram = <&ve_sram 1>; 341*724ba675SRob Herring }; 342*724ba675SRob Herring 343*724ba675SRob Herring mmc0: mmc@1c0f000 { 344*724ba675SRob Herring compatible = "allwinner,sun8i-r40-mmc", 345*724ba675SRob Herring "allwinner,sun50i-a64-mmc"; 346*724ba675SRob Herring reg = <0x01c0f000 0x1000>; 347*724ba675SRob Herring clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 348*724ba675SRob Herring clock-names = "ahb", "mmc"; 349*724ba675SRob Herring resets = <&ccu RST_BUS_MMC0>; 350*724ba675SRob Herring reset-names = "ahb"; 351*724ba675SRob Herring pinctrl-0 = <&mmc0_pins>; 352*724ba675SRob Herring pinctrl-names = "default"; 353*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 354*724ba675SRob Herring status = "disabled"; 355*724ba675SRob Herring #address-cells = <1>; 356*724ba675SRob Herring #size-cells = <0>; 357*724ba675SRob Herring }; 358*724ba675SRob Herring 359*724ba675SRob Herring mmc1: mmc@1c10000 { 360*724ba675SRob Herring compatible = "allwinner,sun8i-r40-mmc", 361*724ba675SRob Herring "allwinner,sun50i-a64-mmc"; 362*724ba675SRob Herring reg = <0x01c10000 0x1000>; 363*724ba675SRob Herring clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 364*724ba675SRob Herring clock-names = "ahb", "mmc"; 365*724ba675SRob Herring resets = <&ccu RST_BUS_MMC1>; 366*724ba675SRob Herring reset-names = "ahb"; 367*724ba675SRob Herring interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 368*724ba675SRob Herring status = "disabled"; 369*724ba675SRob Herring #address-cells = <1>; 370*724ba675SRob Herring #size-cells = <0>; 371*724ba675SRob Herring }; 372*724ba675SRob Herring 373*724ba675SRob Herring mmc2: mmc@1c11000 { 374*724ba675SRob Herring compatible = "allwinner,sun8i-r40-emmc", 375*724ba675SRob Herring "allwinner,sun50i-a64-emmc"; 376*724ba675SRob Herring reg = <0x01c11000 0x1000>; 377*724ba675SRob Herring clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 378*724ba675SRob Herring clock-names = "ahb", "mmc"; 379*724ba675SRob Herring resets = <&ccu RST_BUS_MMC2>; 380*724ba675SRob Herring reset-names = "ahb"; 381*724ba675SRob Herring pinctrl-0 = <&mmc2_pins>; 382*724ba675SRob Herring pinctrl-names = "default"; 383*724ba675SRob Herring interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 384*724ba675SRob Herring status = "disabled"; 385*724ba675SRob Herring #address-cells = <1>; 386*724ba675SRob Herring #size-cells = <0>; 387*724ba675SRob Herring }; 388*724ba675SRob Herring 389*724ba675SRob Herring mmc3: mmc@1c12000 { 390*724ba675SRob Herring compatible = "allwinner,sun8i-r40-mmc", 391*724ba675SRob Herring "allwinner,sun50i-a64-mmc"; 392*724ba675SRob Herring reg = <0x01c12000 0x1000>; 393*724ba675SRob Herring clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; 394*724ba675SRob Herring clock-names = "ahb", "mmc"; 395*724ba675SRob Herring resets = <&ccu RST_BUS_MMC3>; 396*724ba675SRob Herring reset-names = "ahb"; 397*724ba675SRob Herring pinctrl-0 = <&mmc3_pins>; 398*724ba675SRob Herring pinctrl-names = "default"; 399*724ba675SRob Herring interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 400*724ba675SRob Herring status = "disabled"; 401*724ba675SRob Herring #address-cells = <1>; 402*724ba675SRob Herring #size-cells = <0>; 403*724ba675SRob Herring }; 404*724ba675SRob Herring 405*724ba675SRob Herring usbphy: phy@1c13400 { 406*724ba675SRob Herring compatible = "allwinner,sun8i-r40-usb-phy"; 407*724ba675SRob Herring reg = <0x01c13400 0x14>, 408*724ba675SRob Herring <0x01c14800 0x4>, 409*724ba675SRob Herring <0x01c19800 0x4>, 410*724ba675SRob Herring <0x01c1c800 0x4>; 411*724ba675SRob Herring reg-names = "phy_ctrl", 412*724ba675SRob Herring "pmu0", 413*724ba675SRob Herring "pmu1", 414*724ba675SRob Herring "pmu2"; 415*724ba675SRob Herring clocks = <&ccu CLK_USB_PHY0>, 416*724ba675SRob Herring <&ccu CLK_USB_PHY1>, 417*724ba675SRob Herring <&ccu CLK_USB_PHY2>; 418*724ba675SRob Herring clock-names = "usb0_phy", 419*724ba675SRob Herring "usb1_phy", 420*724ba675SRob Herring "usb2_phy"; 421*724ba675SRob Herring resets = <&ccu RST_USB_PHY0>, 422*724ba675SRob Herring <&ccu RST_USB_PHY1>, 423*724ba675SRob Herring <&ccu RST_USB_PHY2>; 424*724ba675SRob Herring reset-names = "usb0_reset", 425*724ba675SRob Herring "usb1_reset", 426*724ba675SRob Herring "usb2_reset"; 427*724ba675SRob Herring status = "disabled"; 428*724ba675SRob Herring #phy-cells = <1>; 429*724ba675SRob Herring }; 430*724ba675SRob Herring 431*724ba675SRob Herring crypto: crypto@1c15000 { 432*724ba675SRob Herring compatible = "allwinner,sun8i-r40-crypto"; 433*724ba675SRob Herring reg = <0x01c15000 0x1000>; 434*724ba675SRob Herring interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 435*724ba675SRob Herring clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 436*724ba675SRob Herring clock-names = "bus", "mod"; 437*724ba675SRob Herring resets = <&ccu RST_BUS_CE>; 438*724ba675SRob Herring }; 439*724ba675SRob Herring 440*724ba675SRob Herring spi2: spi@1c17000 { 441*724ba675SRob Herring compatible = "allwinner,sun8i-r40-spi", 442*724ba675SRob Herring "allwinner,sun8i-h3-spi"; 443*724ba675SRob Herring reg = <0x01c17000 0x1000>; 444*724ba675SRob Herring interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 445*724ba675SRob Herring clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; 446*724ba675SRob Herring clock-names = "ahb", "mod"; 447*724ba675SRob Herring resets = <&ccu RST_BUS_SPI2>; 448*724ba675SRob Herring status = "disabled"; 449*724ba675SRob Herring #address-cells = <1>; 450*724ba675SRob Herring #size-cells = <0>; 451*724ba675SRob Herring }; 452*724ba675SRob Herring 453*724ba675SRob Herring ahci: sata@1c18000 { 454*724ba675SRob Herring compatible = "allwinner,sun8i-r40-ahci"; 455*724ba675SRob Herring reg = <0x01c18000 0x1000>; 456*724ba675SRob Herring interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 457*724ba675SRob Herring clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; 458*724ba675SRob Herring resets = <&ccu RST_BUS_SATA>; 459*724ba675SRob Herring reset-names = "ahci"; 460*724ba675SRob Herring status = "disabled"; 461*724ba675SRob Herring }; 462*724ba675SRob Herring 463*724ba675SRob Herring ehci1: usb@1c19000 { 464*724ba675SRob Herring compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 465*724ba675SRob Herring reg = <0x01c19000 0x100>; 466*724ba675SRob Herring interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 467*724ba675SRob Herring clocks = <&ccu CLK_BUS_EHCI1>; 468*724ba675SRob Herring resets = <&ccu RST_BUS_EHCI1>; 469*724ba675SRob Herring phys = <&usbphy 1>; 470*724ba675SRob Herring phy-names = "usb"; 471*724ba675SRob Herring status = "disabled"; 472*724ba675SRob Herring }; 473*724ba675SRob Herring 474*724ba675SRob Herring ohci1: usb@1c19400 { 475*724ba675SRob Herring compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; 476*724ba675SRob Herring reg = <0x01c19400 0x100>; 477*724ba675SRob Herring interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 478*724ba675SRob Herring clocks = <&ccu CLK_BUS_OHCI1>, 479*724ba675SRob Herring <&ccu CLK_USB_OHCI1>; 480*724ba675SRob Herring resets = <&ccu RST_BUS_OHCI1>; 481*724ba675SRob Herring phys = <&usbphy 1>; 482*724ba675SRob Herring phy-names = "usb"; 483*724ba675SRob Herring status = "disabled"; 484*724ba675SRob Herring }; 485*724ba675SRob Herring 486*724ba675SRob Herring ehci2: usb@1c1c000 { 487*724ba675SRob Herring compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 488*724ba675SRob Herring reg = <0x01c1c000 0x100>; 489*724ba675SRob Herring interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 490*724ba675SRob Herring clocks = <&ccu CLK_BUS_EHCI2>; 491*724ba675SRob Herring resets = <&ccu RST_BUS_EHCI2>; 492*724ba675SRob Herring phys = <&usbphy 2>; 493*724ba675SRob Herring phy-names = "usb"; 494*724ba675SRob Herring status = "disabled"; 495*724ba675SRob Herring }; 496*724ba675SRob Herring 497*724ba675SRob Herring ohci2: usb@1c1c400 { 498*724ba675SRob Herring compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; 499*724ba675SRob Herring reg = <0x01c1c400 0x100>; 500*724ba675SRob Herring interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 501*724ba675SRob Herring clocks = <&ccu CLK_BUS_OHCI2>, 502*724ba675SRob Herring <&ccu CLK_USB_OHCI2>; 503*724ba675SRob Herring resets = <&ccu RST_BUS_OHCI2>; 504*724ba675SRob Herring phys = <&usbphy 2>; 505*724ba675SRob Herring phy-names = "usb"; 506*724ba675SRob Herring status = "disabled"; 507*724ba675SRob Herring }; 508*724ba675SRob Herring 509*724ba675SRob Herring spi3: spi@1c1f000 { 510*724ba675SRob Herring compatible = "allwinner,sun8i-r40-spi", 511*724ba675SRob Herring "allwinner,sun8i-h3-spi"; 512*724ba675SRob Herring reg = <0x01c1f000 0x1000>; 513*724ba675SRob Herring interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 514*724ba675SRob Herring clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; 515*724ba675SRob Herring clock-names = "ahb", "mod"; 516*724ba675SRob Herring resets = <&ccu RST_BUS_SPI3>; 517*724ba675SRob Herring status = "disabled"; 518*724ba675SRob Herring #address-cells = <1>; 519*724ba675SRob Herring #size-cells = <0>; 520*724ba675SRob Herring }; 521*724ba675SRob Herring 522*724ba675SRob Herring ccu: clock@1c20000 { 523*724ba675SRob Herring compatible = "allwinner,sun8i-r40-ccu"; 524*724ba675SRob Herring reg = <0x01c20000 0x400>; 525*724ba675SRob Herring clocks = <&osc24M>, <&rtc CLK_OSC32K>; 526*724ba675SRob Herring clock-names = "hosc", "losc"; 527*724ba675SRob Herring #clock-cells = <1>; 528*724ba675SRob Herring #reset-cells = <1>; 529*724ba675SRob Herring }; 530*724ba675SRob Herring 531*724ba675SRob Herring rtc: rtc@1c20400 { 532*724ba675SRob Herring compatible = "allwinner,sun8i-r40-rtc"; 533*724ba675SRob Herring reg = <0x01c20400 0x400>; 534*724ba675SRob Herring interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 535*724ba675SRob Herring clock-output-names = "osc32k", "osc32k-out"; 536*724ba675SRob Herring clocks = <&osc32k>; 537*724ba675SRob Herring #clock-cells = <1>; 538*724ba675SRob Herring }; 539*724ba675SRob Herring 540*724ba675SRob Herring pio: pinctrl@1c20800 { 541*724ba675SRob Herring compatible = "allwinner,sun8i-r40-pinctrl"; 542*724ba675SRob Herring reg = <0x01c20800 0x400>; 543*724ba675SRob Herring interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 544*724ba675SRob Herring clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 545*724ba675SRob Herring <&rtc CLK_OSC32K>; 546*724ba675SRob Herring clock-names = "apb", "hosc", "losc"; 547*724ba675SRob Herring gpio-controller; 548*724ba675SRob Herring interrupt-controller; 549*724ba675SRob Herring #interrupt-cells = <3>; 550*724ba675SRob Herring #gpio-cells = <3>; 551*724ba675SRob Herring 552*724ba675SRob Herring can_ph_pins: can-ph-pins { 553*724ba675SRob Herring pins = "PH20", "PH21"; 554*724ba675SRob Herring function = "can"; 555*724ba675SRob Herring }; 556*724ba675SRob Herring 557*724ba675SRob Herring can_pa_pins: can-pa-pins { 558*724ba675SRob Herring pins = "PA16", "PA17"; 559*724ba675SRob Herring function = "can"; 560*724ba675SRob Herring }; 561*724ba675SRob Herring 562*724ba675SRob Herring clk_out_a_pin: clk-out-a-pin { 563*724ba675SRob Herring pins = "PI12"; 564*724ba675SRob Herring function = "clk_out_a"; 565*724ba675SRob Herring }; 566*724ba675SRob Herring 567*724ba675SRob Herring /omit-if-no-ref/ 568*724ba675SRob Herring csi0_8bits_pins: csi0-8bits-pins { 569*724ba675SRob Herring pins = "PE0", "PE2", "PE3", "PE4", "PE5", 570*724ba675SRob Herring "PE6", "PE7", "PE8", "PE9", "PE10", 571*724ba675SRob Herring "PE11"; 572*724ba675SRob Herring function = "csi0"; 573*724ba675SRob Herring }; 574*724ba675SRob Herring 575*724ba675SRob Herring /omit-if-no-ref/ 576*724ba675SRob Herring csi0_mclk_pin: csi0-mclk-pin { 577*724ba675SRob Herring pins = "PE1"; 578*724ba675SRob Herring function = "csi0"; 579*724ba675SRob Herring }; 580*724ba675SRob Herring 581*724ba675SRob Herring gmac_rgmii_pins: gmac-rgmii-pins { 582*724ba675SRob Herring pins = "PA0", "PA1", "PA2", "PA3", 583*724ba675SRob Herring "PA4", "PA5", "PA6", "PA7", 584*724ba675SRob Herring "PA8", "PA10", "PA11", "PA12", 585*724ba675SRob Herring "PA13", "PA15", "PA16"; 586*724ba675SRob Herring function = "gmac"; 587*724ba675SRob Herring /* 588*724ba675SRob Herring * data lines in RGMII mode use DDR mode 589*724ba675SRob Herring * and need a higher signal drive strength 590*724ba675SRob Herring */ 591*724ba675SRob Herring drive-strength = <40>; 592*724ba675SRob Herring }; 593*724ba675SRob Herring 594*724ba675SRob Herring i2c0_pins: i2c0-pins { 595*724ba675SRob Herring pins = "PB0", "PB1"; 596*724ba675SRob Herring function = "i2c0"; 597*724ba675SRob Herring }; 598*724ba675SRob Herring 599*724ba675SRob Herring i2c1_pins: i2c1-pins { 600*724ba675SRob Herring pins = "PB18", "PB19"; 601*724ba675SRob Herring function = "i2c1"; 602*724ba675SRob Herring }; 603*724ba675SRob Herring 604*724ba675SRob Herring i2c2_pins: i2c2-pins { 605*724ba675SRob Herring pins = "PB20", "PB21"; 606*724ba675SRob Herring function = "i2c2"; 607*724ba675SRob Herring }; 608*724ba675SRob Herring 609*724ba675SRob Herring i2c3_pins: i2c3-pins { 610*724ba675SRob Herring pins = "PI0", "PI1"; 611*724ba675SRob Herring function = "i2c3"; 612*724ba675SRob Herring }; 613*724ba675SRob Herring 614*724ba675SRob Herring i2c4_pins: i2c4-pins { 615*724ba675SRob Herring pins = "PI2", "PI3"; 616*724ba675SRob Herring function = "i2c4"; 617*724ba675SRob Herring }; 618*724ba675SRob Herring 619*724ba675SRob Herring ir0_pins: ir0-pins { 620*724ba675SRob Herring pins = "PB4"; 621*724ba675SRob Herring function = "ir0"; 622*724ba675SRob Herring }; 623*724ba675SRob Herring 624*724ba675SRob Herring ir1_pins: ir1-pins { 625*724ba675SRob Herring pins = "PB23"; 626*724ba675SRob Herring function = "ir1"; 627*724ba675SRob Herring }; 628*724ba675SRob Herring 629*724ba675SRob Herring mmc0_pins: mmc0-pins { 630*724ba675SRob Herring pins = "PF0", "PF1", "PF2", 631*724ba675SRob Herring "PF3", "PF4", "PF5"; 632*724ba675SRob Herring function = "mmc0"; 633*724ba675SRob Herring drive-strength = <30>; 634*724ba675SRob Herring bias-pull-up; 635*724ba675SRob Herring }; 636*724ba675SRob Herring 637*724ba675SRob Herring mmc1_pg_pins: mmc1-pg-pins { 638*724ba675SRob Herring pins = "PG0", "PG1", "PG2", 639*724ba675SRob Herring "PG3", "PG4", "PG5"; 640*724ba675SRob Herring function = "mmc1"; 641*724ba675SRob Herring drive-strength = <30>; 642*724ba675SRob Herring bias-pull-up; 643*724ba675SRob Herring }; 644*724ba675SRob Herring 645*724ba675SRob Herring mmc2_pins: mmc2-pins { 646*724ba675SRob Herring pins = "PC5", "PC6", "PC7", "PC8", "PC9", 647*724ba675SRob Herring "PC10", "PC11", "PC12", "PC13", "PC14", 648*724ba675SRob Herring "PC15", "PC24"; 649*724ba675SRob Herring function = "mmc2"; 650*724ba675SRob Herring drive-strength = <30>; 651*724ba675SRob Herring bias-pull-up; 652*724ba675SRob Herring }; 653*724ba675SRob Herring 654*724ba675SRob Herring /omit-if-no-ref/ 655*724ba675SRob Herring mmc3_pins: mmc3-pins { 656*724ba675SRob Herring pins = "PI4", "PI5", "PI6", 657*724ba675SRob Herring "PI7", "PI8", "PI9"; 658*724ba675SRob Herring function = "mmc3"; 659*724ba675SRob Herring drive-strength = <30>; 660*724ba675SRob Herring bias-pull-up; 661*724ba675SRob Herring }; 662*724ba675SRob Herring 663*724ba675SRob Herring /omit-if-no-ref/ 664*724ba675SRob Herring spi0_pc_pins: spi0-pc-pins { 665*724ba675SRob Herring pins = "PC0", "PC1", "PC2"; 666*724ba675SRob Herring function = "spi0"; 667*724ba675SRob Herring }; 668*724ba675SRob Herring 669*724ba675SRob Herring /omit-if-no-ref/ 670*724ba675SRob Herring spi0_cs0_pc_pin: spi0-cs0-pc-pin { 671*724ba675SRob Herring pins = "PC23"; 672*724ba675SRob Herring function = "spi0"; 673*724ba675SRob Herring }; 674*724ba675SRob Herring 675*724ba675SRob Herring /omit-if-no-ref/ 676*724ba675SRob Herring spi1_pi_pins: spi1-pi-pins { 677*724ba675SRob Herring pins = "PI17", "PI18", "PI19"; 678*724ba675SRob Herring function = "spi1"; 679*724ba675SRob Herring }; 680*724ba675SRob Herring 681*724ba675SRob Herring /omit-if-no-ref/ 682*724ba675SRob Herring spi1_cs0_pi_pin: spi1-cs0-pi-pin { 683*724ba675SRob Herring pins = "PI16"; 684*724ba675SRob Herring function = "spi1"; 685*724ba675SRob Herring }; 686*724ba675SRob Herring 687*724ba675SRob Herring /omit-if-no-ref/ 688*724ba675SRob Herring spi1_cs1_pi_pin: spi1-cs1-pi-pin { 689*724ba675SRob Herring pins = "PI15"; 690*724ba675SRob Herring function = "spi1"; 691*724ba675SRob Herring }; 692*724ba675SRob Herring 693*724ba675SRob Herring /omit-if-no-ref/ 694*724ba675SRob Herring uart0_pb_pins: uart0-pb-pins { 695*724ba675SRob Herring pins = "PB22", "PB23"; 696*724ba675SRob Herring function = "uart0"; 697*724ba675SRob Herring }; 698*724ba675SRob Herring 699*724ba675SRob Herring /omit-if-no-ref/ 700*724ba675SRob Herring uart2_pi_pins: uart2-pi-pins { 701*724ba675SRob Herring pins = "PI18", "PI19"; 702*724ba675SRob Herring function = "uart2"; 703*724ba675SRob Herring }; 704*724ba675SRob Herring 705*724ba675SRob Herring /omit-if-no-ref/ 706*724ba675SRob Herring uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{ 707*724ba675SRob Herring pins = "PI16", "PI17"; 708*724ba675SRob Herring function = "uart2"; 709*724ba675SRob Herring }; 710*724ba675SRob Herring 711*724ba675SRob Herring /omit-if-no-ref/ 712*724ba675SRob Herring uart3_pg_pins: uart3-pg-pins { 713*724ba675SRob Herring pins = "PG6", "PG7"; 714*724ba675SRob Herring function = "uart3"; 715*724ba675SRob Herring }; 716*724ba675SRob Herring 717*724ba675SRob Herring /omit-if-no-ref/ 718*724ba675SRob Herring uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { 719*724ba675SRob Herring pins = "PG8", "PG9"; 720*724ba675SRob Herring function = "uart3"; 721*724ba675SRob Herring }; 722*724ba675SRob Herring 723*724ba675SRob Herring /omit-if-no-ref/ 724*724ba675SRob Herring uart4_pg_pins: uart4-pg-pins { 725*724ba675SRob Herring pins = "PG10", "PG11"; 726*724ba675SRob Herring function = "uart4"; 727*724ba675SRob Herring }; 728*724ba675SRob Herring 729*724ba675SRob Herring /omit-if-no-ref/ 730*724ba675SRob Herring uart5_ph_pins: uart5-ph-pins { 731*724ba675SRob Herring pins = "PH6", "PH7"; 732*724ba675SRob Herring function = "uart5"; 733*724ba675SRob Herring }; 734*724ba675SRob Herring 735*724ba675SRob Herring /omit-if-no-ref/ 736*724ba675SRob Herring uart7_pi_pins: uart7-pi-pins { 737*724ba675SRob Herring pins = "PI20", "PI21"; 738*724ba675SRob Herring function = "uart7"; 739*724ba675SRob Herring }; 740*724ba675SRob Herring }; 741*724ba675SRob Herring 742*724ba675SRob Herring timer@1c20c00 { 743*724ba675SRob Herring compatible = "allwinner,sun4i-a10-timer"; 744*724ba675SRob Herring reg = <0x01c20c00 0x90>; 745*724ba675SRob Herring interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 746*724ba675SRob Herring <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 747*724ba675SRob Herring <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 748*724ba675SRob Herring <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 749*724ba675SRob Herring <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 750*724ba675SRob Herring <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 751*724ba675SRob Herring clocks = <&osc24M>; 752*724ba675SRob Herring }; 753*724ba675SRob Herring 754*724ba675SRob Herring wdt: watchdog@1c20c90 { 755*724ba675SRob Herring compatible = "allwinner,sun4i-a10-wdt"; 756*724ba675SRob Herring reg = <0x01c20c90 0x10>; 757*724ba675SRob Herring interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 758*724ba675SRob Herring clocks = <&osc24M>; 759*724ba675SRob Herring }; 760*724ba675SRob Herring 761*724ba675SRob Herring ir0: ir@1c21800 { 762*724ba675SRob Herring compatible = "allwinner,sun8i-r40-ir", 763*724ba675SRob Herring "allwinner,sun6i-a31-ir"; 764*724ba675SRob Herring reg = <0x01c21800 0x400>; 765*724ba675SRob Herring pinctrl-0 = <&ir0_pins>; 766*724ba675SRob Herring pinctrl-names = "default"; 767*724ba675SRob Herring clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>; 768*724ba675SRob Herring clock-names = "apb", "ir"; 769*724ba675SRob Herring interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 770*724ba675SRob Herring resets = <&ccu RST_BUS_IR0>; 771*724ba675SRob Herring status = "disabled"; 772*724ba675SRob Herring }; 773*724ba675SRob Herring 774*724ba675SRob Herring ir1: ir@1c21c00 { 775*724ba675SRob Herring compatible = "allwinner,sun8i-r40-ir", 776*724ba675SRob Herring "allwinner,sun6i-a31-ir"; 777*724ba675SRob Herring reg = <0x01c21c00 0x400>; 778*724ba675SRob Herring pinctrl-0 = <&ir1_pins>; 779*724ba675SRob Herring pinctrl-names = "default"; 780*724ba675SRob Herring clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>; 781*724ba675SRob Herring clock-names = "apb", "ir"; 782*724ba675SRob Herring interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 783*724ba675SRob Herring resets = <&ccu RST_BUS_IR1>; 784*724ba675SRob Herring status = "disabled"; 785*724ba675SRob Herring }; 786*724ba675SRob Herring 787*724ba675SRob Herring i2s0: i2s@1c22000 { 788*724ba675SRob Herring #sound-dai-cells = <0>; 789*724ba675SRob Herring compatible = "allwinner,sun8i-r40-i2s", 790*724ba675SRob Herring "allwinner,sun8i-h3-i2s"; 791*724ba675SRob Herring reg = <0x01c22000 0x400>; 792*724ba675SRob Herring interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 793*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 794*724ba675SRob Herring clock-names = "apb", "mod"; 795*724ba675SRob Herring resets = <&ccu RST_BUS_I2S0>; 796*724ba675SRob Herring dmas = <&dma 3>, <&dma 3>; 797*724ba675SRob Herring dma-names = "rx", "tx"; 798*724ba675SRob Herring }; 799*724ba675SRob Herring 800*724ba675SRob Herring i2s1: i2s@1c22400 { 801*724ba675SRob Herring #sound-dai-cells = <0>; 802*724ba675SRob Herring compatible = "allwinner,sun8i-r40-i2s", 803*724ba675SRob Herring "allwinner,sun8i-h3-i2s"; 804*724ba675SRob Herring reg = <0x01c22400 0x400>; 805*724ba675SRob Herring interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 806*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 807*724ba675SRob Herring clock-names = "apb", "mod"; 808*724ba675SRob Herring resets = <&ccu RST_BUS_I2S1>; 809*724ba675SRob Herring dmas = <&dma 4>, <&dma 4>; 810*724ba675SRob Herring dma-names = "rx", "tx"; 811*724ba675SRob Herring }; 812*724ba675SRob Herring 813*724ba675SRob Herring i2s2: i2s@1c22800 { 814*724ba675SRob Herring #sound-dai-cells = <0>; 815*724ba675SRob Herring compatible = "allwinner,sun8i-r40-i2s", 816*724ba675SRob Herring "allwinner,sun8i-h3-i2s"; 817*724ba675SRob Herring reg = <0x01c22800 0x400>; 818*724ba675SRob Herring interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 819*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 820*724ba675SRob Herring clock-names = "apb", "mod"; 821*724ba675SRob Herring resets = <&ccu RST_BUS_I2S2>; 822*724ba675SRob Herring dmas = <&dma 6>, <&dma 6>; 823*724ba675SRob Herring dma-names = "rx", "tx"; 824*724ba675SRob Herring }; 825*724ba675SRob Herring 826*724ba675SRob Herring ths: thermal-sensor@1c24c00 { 827*724ba675SRob Herring compatible = "allwinner,sun8i-r40-ths"; 828*724ba675SRob Herring reg = <0x01c24c00 0x100>; 829*724ba675SRob Herring clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 830*724ba675SRob Herring clock-names = "bus", "mod"; 831*724ba675SRob Herring interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 832*724ba675SRob Herring resets = <&ccu RST_BUS_THS>; 833*724ba675SRob Herring /* TODO: add nvmem-cells for calibration */ 834*724ba675SRob Herring #thermal-sensor-cells = <1>; 835*724ba675SRob Herring }; 836*724ba675SRob Herring 837*724ba675SRob Herring uart0: serial@1c28000 { 838*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 839*724ba675SRob Herring reg = <0x01c28000 0x400>; 840*724ba675SRob Herring interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 841*724ba675SRob Herring reg-shift = <2>; 842*724ba675SRob Herring reg-io-width = <4>; 843*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART0>; 844*724ba675SRob Herring resets = <&ccu RST_BUS_UART0>; 845*724ba675SRob Herring status = "disabled"; 846*724ba675SRob Herring }; 847*724ba675SRob Herring 848*724ba675SRob Herring uart1: serial@1c28400 { 849*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 850*724ba675SRob Herring reg = <0x01c28400 0x400>; 851*724ba675SRob Herring interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 852*724ba675SRob Herring reg-shift = <2>; 853*724ba675SRob Herring reg-io-width = <4>; 854*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART1>; 855*724ba675SRob Herring resets = <&ccu RST_BUS_UART1>; 856*724ba675SRob Herring status = "disabled"; 857*724ba675SRob Herring }; 858*724ba675SRob Herring 859*724ba675SRob Herring uart2: serial@1c28800 { 860*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 861*724ba675SRob Herring reg = <0x01c28800 0x400>; 862*724ba675SRob Herring interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 863*724ba675SRob Herring reg-shift = <2>; 864*724ba675SRob Herring reg-io-width = <4>; 865*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART2>; 866*724ba675SRob Herring resets = <&ccu RST_BUS_UART2>; 867*724ba675SRob Herring status = "disabled"; 868*724ba675SRob Herring }; 869*724ba675SRob Herring 870*724ba675SRob Herring uart3: serial@1c28c00 { 871*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 872*724ba675SRob Herring reg = <0x01c28c00 0x400>; 873*724ba675SRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 874*724ba675SRob Herring reg-shift = <2>; 875*724ba675SRob Herring reg-io-width = <4>; 876*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART3>; 877*724ba675SRob Herring resets = <&ccu RST_BUS_UART3>; 878*724ba675SRob Herring status = "disabled"; 879*724ba675SRob Herring }; 880*724ba675SRob Herring 881*724ba675SRob Herring uart4: serial@1c29000 { 882*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 883*724ba675SRob Herring reg = <0x01c29000 0x400>; 884*724ba675SRob Herring interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 885*724ba675SRob Herring reg-shift = <2>; 886*724ba675SRob Herring reg-io-width = <4>; 887*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART4>; 888*724ba675SRob Herring resets = <&ccu RST_BUS_UART4>; 889*724ba675SRob Herring status = "disabled"; 890*724ba675SRob Herring }; 891*724ba675SRob Herring 892*724ba675SRob Herring uart5: serial@1c29400 { 893*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 894*724ba675SRob Herring reg = <0x01c29400 0x400>; 895*724ba675SRob Herring interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 896*724ba675SRob Herring reg-shift = <2>; 897*724ba675SRob Herring reg-io-width = <4>; 898*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART5>; 899*724ba675SRob Herring resets = <&ccu RST_BUS_UART5>; 900*724ba675SRob Herring status = "disabled"; 901*724ba675SRob Herring }; 902*724ba675SRob Herring 903*724ba675SRob Herring uart6: serial@1c29800 { 904*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 905*724ba675SRob Herring reg = <0x01c29800 0x400>; 906*724ba675SRob Herring interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 907*724ba675SRob Herring reg-shift = <2>; 908*724ba675SRob Herring reg-io-width = <4>; 909*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART6>; 910*724ba675SRob Herring resets = <&ccu RST_BUS_UART6>; 911*724ba675SRob Herring status = "disabled"; 912*724ba675SRob Herring }; 913*724ba675SRob Herring 914*724ba675SRob Herring uart7: serial@1c29c00 { 915*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 916*724ba675SRob Herring reg = <0x01c29c00 0x400>; 917*724ba675SRob Herring interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 918*724ba675SRob Herring reg-shift = <2>; 919*724ba675SRob Herring reg-io-width = <4>; 920*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART7>; 921*724ba675SRob Herring resets = <&ccu RST_BUS_UART7>; 922*724ba675SRob Herring status = "disabled"; 923*724ba675SRob Herring }; 924*724ba675SRob Herring 925*724ba675SRob Herring i2c0: i2c@1c2ac00 { 926*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 927*724ba675SRob Herring reg = <0x01c2ac00 0x400>; 928*724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 929*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C0>; 930*724ba675SRob Herring resets = <&ccu RST_BUS_I2C0>; 931*724ba675SRob Herring pinctrl-0 = <&i2c0_pins>; 932*724ba675SRob Herring pinctrl-names = "default"; 933*724ba675SRob Herring status = "disabled"; 934*724ba675SRob Herring #address-cells = <1>; 935*724ba675SRob Herring #size-cells = <0>; 936*724ba675SRob Herring }; 937*724ba675SRob Herring 938*724ba675SRob Herring i2c1: i2c@1c2b000 { 939*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 940*724ba675SRob Herring reg = <0x01c2b000 0x400>; 941*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 942*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C1>; 943*724ba675SRob Herring resets = <&ccu RST_BUS_I2C1>; 944*724ba675SRob Herring pinctrl-0 = <&i2c1_pins>; 945*724ba675SRob Herring pinctrl-names = "default"; 946*724ba675SRob Herring status = "disabled"; 947*724ba675SRob Herring #address-cells = <1>; 948*724ba675SRob Herring #size-cells = <0>; 949*724ba675SRob Herring }; 950*724ba675SRob Herring 951*724ba675SRob Herring i2c2: i2c@1c2b400 { 952*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 953*724ba675SRob Herring reg = <0x01c2b400 0x400>; 954*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 955*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C2>; 956*724ba675SRob Herring resets = <&ccu RST_BUS_I2C2>; 957*724ba675SRob Herring pinctrl-0 = <&i2c2_pins>; 958*724ba675SRob Herring pinctrl-names = "default"; 959*724ba675SRob Herring status = "disabled"; 960*724ba675SRob Herring #address-cells = <1>; 961*724ba675SRob Herring #size-cells = <0>; 962*724ba675SRob Herring }; 963*724ba675SRob Herring 964*724ba675SRob Herring i2c3: i2c@1c2b800 { 965*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 966*724ba675SRob Herring reg = <0x01c2b800 0x400>; 967*724ba675SRob Herring interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 968*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C3>; 969*724ba675SRob Herring resets = <&ccu RST_BUS_I2C3>; 970*724ba675SRob Herring pinctrl-0 = <&i2c3_pins>; 971*724ba675SRob Herring pinctrl-names = "default"; 972*724ba675SRob Herring status = "disabled"; 973*724ba675SRob Herring #address-cells = <1>; 974*724ba675SRob Herring #size-cells = <0>; 975*724ba675SRob Herring }; 976*724ba675SRob Herring 977*724ba675SRob Herring can0: can@1c2bc00 { 978*724ba675SRob Herring compatible = "allwinner,sun8i-r40-can"; 979*724ba675SRob Herring reg = <0x01c2bc00 0x400>; 980*724ba675SRob Herring interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 981*724ba675SRob Herring clocks = <&ccu CLK_BUS_CAN>; 982*724ba675SRob Herring resets = <&ccu RST_BUS_CAN>; 983*724ba675SRob Herring status = "disabled"; 984*724ba675SRob Herring }; 985*724ba675SRob Herring 986*724ba675SRob Herring i2c4: i2c@1c2c000 { 987*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 988*724ba675SRob Herring reg = <0x01c2c000 0x400>; 989*724ba675SRob Herring interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 990*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C4>; 991*724ba675SRob Herring resets = <&ccu RST_BUS_I2C4>; 992*724ba675SRob Herring pinctrl-0 = <&i2c4_pins>; 993*724ba675SRob Herring pinctrl-names = "default"; 994*724ba675SRob Herring status = "disabled"; 995*724ba675SRob Herring #address-cells = <1>; 996*724ba675SRob Herring #size-cells = <0>; 997*724ba675SRob Herring }; 998*724ba675SRob Herring 999*724ba675SRob Herring mali: gpu@1c40000 { 1000*724ba675SRob Herring compatible = "allwinner,sun8i-r40-mali", "arm,mali-400"; 1001*724ba675SRob Herring reg = <0x01c40000 0x10000>; 1002*724ba675SRob Herring interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1003*724ba675SRob Herring <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1004*724ba675SRob Herring <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1005*724ba675SRob Herring <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 1006*724ba675SRob Herring <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 1007*724ba675SRob Herring <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1008*724ba675SRob Herring <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1009*724ba675SRob Herring interrupt-names = "gp", 1010*724ba675SRob Herring "gpmmu", 1011*724ba675SRob Herring "pp0", 1012*724ba675SRob Herring "ppmmu0", 1013*724ba675SRob Herring "pp1", 1014*724ba675SRob Herring "ppmmu1", 1015*724ba675SRob Herring "pmu"; 1016*724ba675SRob Herring clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 1017*724ba675SRob Herring clock-names = "bus", "core"; 1018*724ba675SRob Herring resets = <&ccu RST_BUS_GPU>; 1019*724ba675SRob Herring }; 1020*724ba675SRob Herring 1021*724ba675SRob Herring gmac: ethernet@1c50000 { 1022*724ba675SRob Herring compatible = "allwinner,sun8i-r40-gmac"; 1023*724ba675SRob Herring syscon = <&ccu>; 1024*724ba675SRob Herring reg = <0x01c50000 0x10000>; 1025*724ba675SRob Herring interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1026*724ba675SRob Herring interrupt-names = "macirq"; 1027*724ba675SRob Herring resets = <&ccu RST_BUS_GMAC>; 1028*724ba675SRob Herring reset-names = "stmmaceth"; 1029*724ba675SRob Herring clocks = <&ccu CLK_BUS_GMAC>; 1030*724ba675SRob Herring clock-names = "stmmaceth"; 1031*724ba675SRob Herring status = "disabled"; 1032*724ba675SRob Herring 1033*724ba675SRob Herring gmac_mdio: mdio { 1034*724ba675SRob Herring compatible = "snps,dwmac-mdio"; 1035*724ba675SRob Herring #address-cells = <1>; 1036*724ba675SRob Herring #size-cells = <0>; 1037*724ba675SRob Herring }; 1038*724ba675SRob Herring }; 1039*724ba675SRob Herring 1040*724ba675SRob Herring mbus: dram-controller@1c62000 { 1041*724ba675SRob Herring compatible = "allwinner,sun8i-r40-mbus"; 1042*724ba675SRob Herring reg = <0x01c62000 0x1000>; 1043*724ba675SRob Herring clocks = <&ccu 155>; 1044*724ba675SRob Herring #address-cells = <1>; 1045*724ba675SRob Herring #size-cells = <1>; 1046*724ba675SRob Herring dma-ranges = <0x00000000 0x40000000 0x80000000>; 1047*724ba675SRob Herring #interconnect-cells = <1>; 1048*724ba675SRob Herring }; 1049*724ba675SRob Herring 1050*724ba675SRob Herring tcon_top: tcon-top@1c70000 { 1051*724ba675SRob Herring compatible = "allwinner,sun8i-r40-tcon-top"; 1052*724ba675SRob Herring reg = <0x01c70000 0x1000>; 1053*724ba675SRob Herring clocks = <&ccu CLK_BUS_TCON_TOP>, 1054*724ba675SRob Herring <&ccu CLK_TCON_TV0>, 1055*724ba675SRob Herring <&ccu CLK_TVE0>, 1056*724ba675SRob Herring <&ccu CLK_TCON_TV1>, 1057*724ba675SRob Herring <&ccu CLK_TVE1>, 1058*724ba675SRob Herring <&ccu CLK_DSI_DPHY>; 1059*724ba675SRob Herring clock-names = "bus", 1060*724ba675SRob Herring "tcon-tv0", 1061*724ba675SRob Herring "tve0", 1062*724ba675SRob Herring "tcon-tv1", 1063*724ba675SRob Herring "tve1", 1064*724ba675SRob Herring "dsi"; 1065*724ba675SRob Herring clock-output-names = "tcon-top-tv0", 1066*724ba675SRob Herring "tcon-top-tv1", 1067*724ba675SRob Herring "tcon-top-dsi"; 1068*724ba675SRob Herring resets = <&ccu RST_BUS_TCON_TOP>; 1069*724ba675SRob Herring #clock-cells = <1>; 1070*724ba675SRob Herring 1071*724ba675SRob Herring ports { 1072*724ba675SRob Herring #address-cells = <1>; 1073*724ba675SRob Herring #size-cells = <0>; 1074*724ba675SRob Herring 1075*724ba675SRob Herring tcon_top_mixer0_in: port@0 { 1076*724ba675SRob Herring reg = <0>; 1077*724ba675SRob Herring 1078*724ba675SRob Herring tcon_top_mixer0_in_mixer0: endpoint { 1079*724ba675SRob Herring remote-endpoint = <&mixer0_out_tcon_top>; 1080*724ba675SRob Herring }; 1081*724ba675SRob Herring }; 1082*724ba675SRob Herring 1083*724ba675SRob Herring tcon_top_mixer0_out: port@1 { 1084*724ba675SRob Herring #address-cells = <1>; 1085*724ba675SRob Herring #size-cells = <0>; 1086*724ba675SRob Herring reg = <1>; 1087*724ba675SRob Herring 1088*724ba675SRob Herring tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 1089*724ba675SRob Herring reg = <0>; 1090*724ba675SRob Herring }; 1091*724ba675SRob Herring 1092*724ba675SRob Herring tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { 1093*724ba675SRob Herring reg = <1>; 1094*724ba675SRob Herring }; 1095*724ba675SRob Herring 1096*724ba675SRob Herring tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 1097*724ba675SRob Herring reg = <2>; 1098*724ba675SRob Herring remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 1099*724ba675SRob Herring }; 1100*724ba675SRob Herring 1101*724ba675SRob Herring tcon_top_mixer0_out_tcon_tv1: endpoint@3 { 1102*724ba675SRob Herring reg = <3>; 1103*724ba675SRob Herring remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; 1104*724ba675SRob Herring }; 1105*724ba675SRob Herring }; 1106*724ba675SRob Herring 1107*724ba675SRob Herring tcon_top_mixer1_in: port@2 { 1108*724ba675SRob Herring #address-cells = <1>; 1109*724ba675SRob Herring #size-cells = <0>; 1110*724ba675SRob Herring reg = <2>; 1111*724ba675SRob Herring 1112*724ba675SRob Herring tcon_top_mixer1_in_mixer1: endpoint@1 { 1113*724ba675SRob Herring reg = <1>; 1114*724ba675SRob Herring remote-endpoint = <&mixer1_out_tcon_top>; 1115*724ba675SRob Herring }; 1116*724ba675SRob Herring }; 1117*724ba675SRob Herring 1118*724ba675SRob Herring tcon_top_mixer1_out: port@3 { 1119*724ba675SRob Herring #address-cells = <1>; 1120*724ba675SRob Herring #size-cells = <0>; 1121*724ba675SRob Herring reg = <3>; 1122*724ba675SRob Herring 1123*724ba675SRob Herring tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 1124*724ba675SRob Herring reg = <0>; 1125*724ba675SRob Herring }; 1126*724ba675SRob Herring 1127*724ba675SRob Herring tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { 1128*724ba675SRob Herring reg = <1>; 1129*724ba675SRob Herring }; 1130*724ba675SRob Herring 1131*724ba675SRob Herring tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 1132*724ba675SRob Herring reg = <2>; 1133*724ba675SRob Herring remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 1134*724ba675SRob Herring }; 1135*724ba675SRob Herring 1136*724ba675SRob Herring tcon_top_mixer1_out_tcon_tv1: endpoint@3 { 1137*724ba675SRob Herring reg = <3>; 1138*724ba675SRob Herring remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; 1139*724ba675SRob Herring }; 1140*724ba675SRob Herring }; 1141*724ba675SRob Herring 1142*724ba675SRob Herring tcon_top_hdmi_in: port@4 { 1143*724ba675SRob Herring #address-cells = <1>; 1144*724ba675SRob Herring #size-cells = <0>; 1145*724ba675SRob Herring reg = <4>; 1146*724ba675SRob Herring 1147*724ba675SRob Herring tcon_top_hdmi_in_tcon_tv0: endpoint@0 { 1148*724ba675SRob Herring reg = <0>; 1149*724ba675SRob Herring remote-endpoint = <&tcon_tv0_out_tcon_top>; 1150*724ba675SRob Herring }; 1151*724ba675SRob Herring 1152*724ba675SRob Herring tcon_top_hdmi_in_tcon_tv1: endpoint@1 { 1153*724ba675SRob Herring reg = <1>; 1154*724ba675SRob Herring remote-endpoint = <&tcon_tv1_out_tcon_top>; 1155*724ba675SRob Herring }; 1156*724ba675SRob Herring }; 1157*724ba675SRob Herring 1158*724ba675SRob Herring tcon_top_hdmi_out: port@5 { 1159*724ba675SRob Herring reg = <5>; 1160*724ba675SRob Herring 1161*724ba675SRob Herring tcon_top_hdmi_out_hdmi: endpoint { 1162*724ba675SRob Herring remote-endpoint = <&hdmi_in_tcon_top>; 1163*724ba675SRob Herring }; 1164*724ba675SRob Herring }; 1165*724ba675SRob Herring }; 1166*724ba675SRob Herring }; 1167*724ba675SRob Herring 1168*724ba675SRob Herring tcon_tv0: lcd-controller@1c73000 { 1169*724ba675SRob Herring compatible = "allwinner,sun8i-r40-tcon-tv"; 1170*724ba675SRob Herring reg = <0x01c73000 0x1000>; 1171*724ba675SRob Herring interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1172*724ba675SRob Herring clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>; 1173*724ba675SRob Herring clock-names = "ahb", "tcon-ch1"; 1174*724ba675SRob Herring resets = <&ccu RST_BUS_TCON_TV0>; 1175*724ba675SRob Herring reset-names = "lcd"; 1176*724ba675SRob Herring status = "disabled"; 1177*724ba675SRob Herring 1178*724ba675SRob Herring ports { 1179*724ba675SRob Herring #address-cells = <1>; 1180*724ba675SRob Herring #size-cells = <0>; 1181*724ba675SRob Herring 1182*724ba675SRob Herring tcon_tv0_in: port@0 { 1183*724ba675SRob Herring #address-cells = <1>; 1184*724ba675SRob Herring #size-cells = <0>; 1185*724ba675SRob Herring reg = <0>; 1186*724ba675SRob Herring 1187*724ba675SRob Herring tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 1188*724ba675SRob Herring reg = <0>; 1189*724ba675SRob Herring remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 1190*724ba675SRob Herring }; 1191*724ba675SRob Herring 1192*724ba675SRob Herring tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 1193*724ba675SRob Herring reg = <1>; 1194*724ba675SRob Herring remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 1195*724ba675SRob Herring }; 1196*724ba675SRob Herring }; 1197*724ba675SRob Herring 1198*724ba675SRob Herring tcon_tv0_out: port@1 { 1199*724ba675SRob Herring #address-cells = <1>; 1200*724ba675SRob Herring #size-cells = <0>; 1201*724ba675SRob Herring reg = <1>; 1202*724ba675SRob Herring 1203*724ba675SRob Herring tcon_tv0_out_tcon_top: endpoint@1 { 1204*724ba675SRob Herring reg = <1>; 1205*724ba675SRob Herring remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 1206*724ba675SRob Herring }; 1207*724ba675SRob Herring }; 1208*724ba675SRob Herring }; 1209*724ba675SRob Herring }; 1210*724ba675SRob Herring 1211*724ba675SRob Herring tcon_tv1: lcd-controller@1c74000 { 1212*724ba675SRob Herring compatible = "allwinner,sun8i-r40-tcon-tv"; 1213*724ba675SRob Herring reg = <0x01c74000 0x1000>; 1214*724ba675SRob Herring interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1215*724ba675SRob Herring clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>; 1216*724ba675SRob Herring clock-names = "ahb", "tcon-ch1"; 1217*724ba675SRob Herring resets = <&ccu RST_BUS_TCON_TV1>; 1218*724ba675SRob Herring reset-names = "lcd"; 1219*724ba675SRob Herring status = "disabled"; 1220*724ba675SRob Herring 1221*724ba675SRob Herring ports { 1222*724ba675SRob Herring #address-cells = <1>; 1223*724ba675SRob Herring #size-cells = <0>; 1224*724ba675SRob Herring 1225*724ba675SRob Herring tcon_tv1_in: port@0 { 1226*724ba675SRob Herring #address-cells = <1>; 1227*724ba675SRob Herring #size-cells = <0>; 1228*724ba675SRob Herring reg = <0>; 1229*724ba675SRob Herring 1230*724ba675SRob Herring tcon_tv1_in_tcon_top_mixer0: endpoint@0 { 1231*724ba675SRob Herring reg = <0>; 1232*724ba675SRob Herring remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>; 1233*724ba675SRob Herring }; 1234*724ba675SRob Herring 1235*724ba675SRob Herring tcon_tv1_in_tcon_top_mixer1: endpoint@1 { 1236*724ba675SRob Herring reg = <1>; 1237*724ba675SRob Herring remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>; 1238*724ba675SRob Herring }; 1239*724ba675SRob Herring }; 1240*724ba675SRob Herring 1241*724ba675SRob Herring tcon_tv1_out: port@1 { 1242*724ba675SRob Herring #address-cells = <1>; 1243*724ba675SRob Herring #size-cells = <0>; 1244*724ba675SRob Herring reg = <1>; 1245*724ba675SRob Herring 1246*724ba675SRob Herring tcon_tv1_out_tcon_top: endpoint@1 { 1247*724ba675SRob Herring reg = <1>; 1248*724ba675SRob Herring remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>; 1249*724ba675SRob Herring }; 1250*724ba675SRob Herring }; 1251*724ba675SRob Herring }; 1252*724ba675SRob Herring }; 1253*724ba675SRob Herring 1254*724ba675SRob Herring gic: interrupt-controller@1c81000 { 1255*724ba675SRob Herring compatible = "arm,gic-400"; 1256*724ba675SRob Herring reg = <0x01c81000 0x1000>, 1257*724ba675SRob Herring <0x01c82000 0x2000>, 1258*724ba675SRob Herring <0x01c84000 0x2000>, 1259*724ba675SRob Herring <0x01c86000 0x2000>; 1260*724ba675SRob Herring interrupt-controller; 1261*724ba675SRob Herring #interrupt-cells = <3>; 1262*724ba675SRob Herring interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1263*724ba675SRob Herring }; 1264*724ba675SRob Herring 1265*724ba675SRob Herring hdmi: hdmi@1ee0000 { 1266*724ba675SRob Herring compatible = "allwinner,sun8i-r40-dw-hdmi", 1267*724ba675SRob Herring "allwinner,sun8i-a83t-dw-hdmi"; 1268*724ba675SRob Herring reg = <0x01ee0000 0x10000>; 1269*724ba675SRob Herring reg-io-width = <1>; 1270*724ba675SRob Herring interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1271*724ba675SRob Herring clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, 1272*724ba675SRob Herring <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; 1273*724ba675SRob Herring clock-names = "iahb", "isfr", "tmds", "cec"; 1274*724ba675SRob Herring resets = <&ccu RST_BUS_HDMI1>; 1275*724ba675SRob Herring reset-names = "ctrl"; 1276*724ba675SRob Herring phys = <&hdmi_phy>; 1277*724ba675SRob Herring phy-names = "phy"; 1278*724ba675SRob Herring status = "disabled"; 1279*724ba675SRob Herring 1280*724ba675SRob Herring ports { 1281*724ba675SRob Herring #address-cells = <1>; 1282*724ba675SRob Herring #size-cells = <0>; 1283*724ba675SRob Herring 1284*724ba675SRob Herring hdmi_in: port@0 { 1285*724ba675SRob Herring reg = <0>; 1286*724ba675SRob Herring 1287*724ba675SRob Herring hdmi_in_tcon_top: endpoint { 1288*724ba675SRob Herring remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 1289*724ba675SRob Herring }; 1290*724ba675SRob Herring }; 1291*724ba675SRob Herring 1292*724ba675SRob Herring hdmi_out: port@1 { 1293*724ba675SRob Herring reg = <1>; 1294*724ba675SRob Herring }; 1295*724ba675SRob Herring }; 1296*724ba675SRob Herring }; 1297*724ba675SRob Herring 1298*724ba675SRob Herring hdmi_phy: hdmi-phy@1ef0000 { 1299*724ba675SRob Herring compatible = "allwinner,sun8i-r40-hdmi-phy"; 1300*724ba675SRob Herring reg = <0x01ef0000 0x10000>; 1301*724ba675SRob Herring clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, 1302*724ba675SRob Herring <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>; 1303*724ba675SRob Herring clock-names = "bus", "mod", "pll-0", "pll-1"; 1304*724ba675SRob Herring resets = <&ccu RST_BUS_HDMI0>; 1305*724ba675SRob Herring reset-names = "phy"; 1306*724ba675SRob Herring #phy-cells = <0>; 1307*724ba675SRob Herring }; 1308*724ba675SRob Herring }; 1309*724ba675SRob Herring 1310*724ba675SRob Herring pmu { 1311*724ba675SRob Herring compatible = "arm,cortex-a7-pmu"; 1312*724ba675SRob Herring interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1313*724ba675SRob Herring <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1314*724ba675SRob Herring <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1315*724ba675SRob Herring <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1316*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1317*724ba675SRob Herring }; 1318*724ba675SRob Herring 1319*724ba675SRob Herring timer { 1320*724ba675SRob Herring compatible = "arm,armv7-timer"; 1321*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1322*724ba675SRob Herring <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1323*724ba675SRob Herring <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1324*724ba675SRob Herring <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1325*724ba675SRob Herring }; 1326*724ba675SRob Herring}; 1327