1*724ba675SRob Herring/* 2*724ba675SRob Herring * Copyright 2015 Vishnu Patekar 3*724ba675SRob Herring * 4*724ba675SRob Herring * Vishnu Patekar <vishnupatekar0510@gmail.com> 5*724ba675SRob Herring * 6*724ba675SRob Herring * This file is dual-licensed: you can use it either under the terms 7*724ba675SRob Herring * of the GPL or the X11 license, at your option. Note that this dual 8*724ba675SRob Herring * licensing only applies to this file, and not this project as a 9*724ba675SRob Herring * whole. 10*724ba675SRob Herring * 11*724ba675SRob Herring * a) This file is free software; you can redistribute it and/or 12*724ba675SRob Herring * modify it under the terms of the GNU General Public License as 13*724ba675SRob Herring * published by the Free Software Foundation; either version 2 of the 14*724ba675SRob Herring * License, or (at your option) any later version. 15*724ba675SRob Herring * 16*724ba675SRob Herring * This file is distributed in the hope that it will be useful, 17*724ba675SRob Herring * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*724ba675SRob Herring * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*724ba675SRob Herring * GNU General Public License for more details. 20*724ba675SRob Herring * 21*724ba675SRob Herring * Or, alternatively, 22*724ba675SRob Herring * 23*724ba675SRob Herring * b) Permission is hereby granted, free of charge, to any person 24*724ba675SRob Herring * obtaining a copy of this software and associated documentation 25*724ba675SRob Herring * files (the "Software"), to deal in the Software without 26*724ba675SRob Herring * restriction, including without limitation the rights to use, 27*724ba675SRob Herring * copy, modify, merge, publish, distribute, sublicense, and/or 28*724ba675SRob Herring * sell copies of the Software, and to permit persons to whom the 29*724ba675SRob Herring * Software is furnished to do so, subject to the following 30*724ba675SRob Herring * conditions: 31*724ba675SRob Herring * 32*724ba675SRob Herring * The above copyright notice and this permission notice shall be 33*724ba675SRob Herring * included in all copies or substantial portions of the Software. 34*724ba675SRob Herring * 35*724ba675SRob Herring * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36*724ba675SRob Herring * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37*724ba675SRob Herring * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38*724ba675SRob Herring * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39*724ba675SRob Herring * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40*724ba675SRob Herring * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41*724ba675SRob Herring * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42*724ba675SRob Herring * OTHER DEALINGS IN THE SOFTWARE. 43*724ba675SRob Herring */ 44*724ba675SRob Herring 45*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 46*724ba675SRob Herring 47*724ba675SRob Herring#include <dt-bindings/clock/sun8i-a83t-ccu.h> 48*724ba675SRob Herring#include <dt-bindings/clock/sun8i-de2.h> 49*724ba675SRob Herring#include <dt-bindings/clock/sun8i-r-ccu.h> 50*724ba675SRob Herring#include <dt-bindings/reset/sun8i-a83t-ccu.h> 51*724ba675SRob Herring#include <dt-bindings/reset/sun8i-de2.h> 52*724ba675SRob Herring#include <dt-bindings/reset/sun8i-r-ccu.h> 53*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h> 54*724ba675SRob Herring 55*724ba675SRob Herring/ { 56*724ba675SRob Herring interrupt-parent = <&gic>; 57*724ba675SRob Herring #address-cells = <1>; 58*724ba675SRob Herring #size-cells = <1>; 59*724ba675SRob Herring 60*724ba675SRob Herring cpus { 61*724ba675SRob Herring #address-cells = <1>; 62*724ba675SRob Herring #size-cells = <0>; 63*724ba675SRob Herring 64*724ba675SRob Herring cpu0: cpu@0 { 65*724ba675SRob Herring compatible = "arm,cortex-a7"; 66*724ba675SRob Herring device_type = "cpu"; 67*724ba675SRob Herring clocks = <&ccu CLK_C0CPUX>; 68*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 69*724ba675SRob Herring cci-control-port = <&cci_control0>; 70*724ba675SRob Herring enable-method = "allwinner,sun8i-a83t-smp"; 71*724ba675SRob Herring reg = <0>; 72*724ba675SRob Herring #cooling-cells = <2>; 73*724ba675SRob Herring }; 74*724ba675SRob Herring 75*724ba675SRob Herring cpu1: cpu@1 { 76*724ba675SRob Herring compatible = "arm,cortex-a7"; 77*724ba675SRob Herring device_type = "cpu"; 78*724ba675SRob Herring clocks = <&ccu CLK_C0CPUX>; 79*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 80*724ba675SRob Herring cci-control-port = <&cci_control0>; 81*724ba675SRob Herring enable-method = "allwinner,sun8i-a83t-smp"; 82*724ba675SRob Herring reg = <1>; 83*724ba675SRob Herring #cooling-cells = <2>; 84*724ba675SRob Herring }; 85*724ba675SRob Herring 86*724ba675SRob Herring cpu2: cpu@2 { 87*724ba675SRob Herring compatible = "arm,cortex-a7"; 88*724ba675SRob Herring device_type = "cpu"; 89*724ba675SRob Herring clocks = <&ccu CLK_C0CPUX>; 90*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 91*724ba675SRob Herring cci-control-port = <&cci_control0>; 92*724ba675SRob Herring enable-method = "allwinner,sun8i-a83t-smp"; 93*724ba675SRob Herring reg = <2>; 94*724ba675SRob Herring #cooling-cells = <2>; 95*724ba675SRob Herring }; 96*724ba675SRob Herring 97*724ba675SRob Herring cpu3: cpu@3 { 98*724ba675SRob Herring compatible = "arm,cortex-a7"; 99*724ba675SRob Herring device_type = "cpu"; 100*724ba675SRob Herring clocks = <&ccu CLK_C0CPUX>; 101*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 102*724ba675SRob Herring cci-control-port = <&cci_control0>; 103*724ba675SRob Herring enable-method = "allwinner,sun8i-a83t-smp"; 104*724ba675SRob Herring reg = <3>; 105*724ba675SRob Herring #cooling-cells = <2>; 106*724ba675SRob Herring }; 107*724ba675SRob Herring 108*724ba675SRob Herring cpu100: cpu@100 { 109*724ba675SRob Herring compatible = "arm,cortex-a7"; 110*724ba675SRob Herring device_type = "cpu"; 111*724ba675SRob Herring clocks = <&ccu CLK_C1CPUX>; 112*724ba675SRob Herring operating-points-v2 = <&cpu1_opp_table>; 113*724ba675SRob Herring cci-control-port = <&cci_control1>; 114*724ba675SRob Herring enable-method = "allwinner,sun8i-a83t-smp"; 115*724ba675SRob Herring reg = <0x100>; 116*724ba675SRob Herring #cooling-cells = <2>; 117*724ba675SRob Herring }; 118*724ba675SRob Herring 119*724ba675SRob Herring cpu101: cpu@101 { 120*724ba675SRob Herring compatible = "arm,cortex-a7"; 121*724ba675SRob Herring device_type = "cpu"; 122*724ba675SRob Herring clocks = <&ccu CLK_C1CPUX>; 123*724ba675SRob Herring operating-points-v2 = <&cpu1_opp_table>; 124*724ba675SRob Herring cci-control-port = <&cci_control1>; 125*724ba675SRob Herring enable-method = "allwinner,sun8i-a83t-smp"; 126*724ba675SRob Herring reg = <0x101>; 127*724ba675SRob Herring #cooling-cells = <2>; 128*724ba675SRob Herring }; 129*724ba675SRob Herring 130*724ba675SRob Herring cpu102: cpu@102 { 131*724ba675SRob Herring compatible = "arm,cortex-a7"; 132*724ba675SRob Herring device_type = "cpu"; 133*724ba675SRob Herring clocks = <&ccu CLK_C1CPUX>; 134*724ba675SRob Herring operating-points-v2 = <&cpu1_opp_table>; 135*724ba675SRob Herring cci-control-port = <&cci_control1>; 136*724ba675SRob Herring enable-method = "allwinner,sun8i-a83t-smp"; 137*724ba675SRob Herring reg = <0x102>; 138*724ba675SRob Herring #cooling-cells = <2>; 139*724ba675SRob Herring }; 140*724ba675SRob Herring 141*724ba675SRob Herring cpu103: cpu@103 { 142*724ba675SRob Herring compatible = "arm,cortex-a7"; 143*724ba675SRob Herring device_type = "cpu"; 144*724ba675SRob Herring clocks = <&ccu CLK_C1CPUX>; 145*724ba675SRob Herring operating-points-v2 = <&cpu1_opp_table>; 146*724ba675SRob Herring cci-control-port = <&cci_control1>; 147*724ba675SRob Herring enable-method = "allwinner,sun8i-a83t-smp"; 148*724ba675SRob Herring reg = <0x103>; 149*724ba675SRob Herring #cooling-cells = <2>; 150*724ba675SRob Herring }; 151*724ba675SRob Herring }; 152*724ba675SRob Herring 153*724ba675SRob Herring timer { 154*724ba675SRob Herring compatible = "arm,armv7-timer"; 155*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 156*724ba675SRob Herring <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 157*724ba675SRob Herring <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 158*724ba675SRob Herring <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 159*724ba675SRob Herring }; 160*724ba675SRob Herring 161*724ba675SRob Herring clocks { 162*724ba675SRob Herring #address-cells = <1>; 163*724ba675SRob Herring #size-cells = <1>; 164*724ba675SRob Herring ranges; 165*724ba675SRob Herring 166*724ba675SRob Herring /* TODO: PRCM block has a mux for this. */ 167*724ba675SRob Herring osc24M: osc24M_clk { 168*724ba675SRob Herring #clock-cells = <0>; 169*724ba675SRob Herring compatible = "fixed-clock"; 170*724ba675SRob Herring clock-frequency = <24000000>; 171*724ba675SRob Herring clock-accuracy = <50000>; 172*724ba675SRob Herring clock-output-names = "osc24M"; 173*724ba675SRob Herring }; 174*724ba675SRob Herring 175*724ba675SRob Herring /* 176*724ba675SRob Herring * This is called "internal OSC" in some places. 177*724ba675SRob Herring * It is an internal RC-based oscillator. 178*724ba675SRob Herring * TODO: Its controls are in the PRCM block. 179*724ba675SRob Herring */ 180*724ba675SRob Herring osc16M: osc16M_clk { 181*724ba675SRob Herring #clock-cells = <0>; 182*724ba675SRob Herring compatible = "fixed-clock"; 183*724ba675SRob Herring clock-frequency = <16000000>; 184*724ba675SRob Herring clock-output-names = "osc16M"; 185*724ba675SRob Herring }; 186*724ba675SRob Herring 187*724ba675SRob Herring osc16Md512: osc16Md512_clk { 188*724ba675SRob Herring #clock-cells = <0>; 189*724ba675SRob Herring compatible = "fixed-factor-clock"; 190*724ba675SRob Herring clock-div = <512>; 191*724ba675SRob Herring clock-mult = <1>; 192*724ba675SRob Herring clocks = <&osc16M>; 193*724ba675SRob Herring clock-output-names = "osc16M-d512"; 194*724ba675SRob Herring }; 195*724ba675SRob Herring }; 196*724ba675SRob Herring 197*724ba675SRob Herring de: display-engine { 198*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-display-engine"; 199*724ba675SRob Herring allwinner,pipelines = <&mixer0>, <&mixer1>; 200*724ba675SRob Herring status = "disabled"; 201*724ba675SRob Herring }; 202*724ba675SRob Herring 203*724ba675SRob Herring cpu0_opp_table: opp-table-cluster0 { 204*724ba675SRob Herring compatible = "operating-points-v2"; 205*724ba675SRob Herring opp-shared; 206*724ba675SRob Herring 207*724ba675SRob Herring opp-480000000 { 208*724ba675SRob Herring opp-hz = /bits/ 64 <480000000>; 209*724ba675SRob Herring opp-microvolt = <840000>; 210*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 211*724ba675SRob Herring }; 212*724ba675SRob Herring 213*724ba675SRob Herring opp-600000000 { 214*724ba675SRob Herring opp-hz = /bits/ 64 <600000000>; 215*724ba675SRob Herring opp-microvolt = <840000>; 216*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 217*724ba675SRob Herring }; 218*724ba675SRob Herring 219*724ba675SRob Herring opp-720000000 { 220*724ba675SRob Herring opp-hz = /bits/ 64 <720000000>; 221*724ba675SRob Herring opp-microvolt = <840000>; 222*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 223*724ba675SRob Herring }; 224*724ba675SRob Herring 225*724ba675SRob Herring opp-864000000 { 226*724ba675SRob Herring opp-hz = /bits/ 64 <864000000>; 227*724ba675SRob Herring opp-microvolt = <840000>; 228*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 229*724ba675SRob Herring }; 230*724ba675SRob Herring 231*724ba675SRob Herring opp-912000000 { 232*724ba675SRob Herring opp-hz = /bits/ 64 <912000000>; 233*724ba675SRob Herring opp-microvolt = <840000>; 234*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 235*724ba675SRob Herring }; 236*724ba675SRob Herring 237*724ba675SRob Herring opp-1008000000 { 238*724ba675SRob Herring opp-hz = /bits/ 64 <1008000000>; 239*724ba675SRob Herring opp-microvolt = <840000>; 240*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 241*724ba675SRob Herring }; 242*724ba675SRob Herring 243*724ba675SRob Herring opp-1128000000 { 244*724ba675SRob Herring opp-hz = /bits/ 64 <1128000000>; 245*724ba675SRob Herring opp-microvolt = <840000>; 246*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 247*724ba675SRob Herring }; 248*724ba675SRob Herring 249*724ba675SRob Herring opp-1200000000 { 250*724ba675SRob Herring opp-hz = /bits/ 64 <1200000000>; 251*724ba675SRob Herring opp-microvolt = <840000>; 252*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 253*724ba675SRob Herring }; 254*724ba675SRob Herring }; 255*724ba675SRob Herring 256*724ba675SRob Herring cpu1_opp_table: opp-table-cluster1 { 257*724ba675SRob Herring compatible = "operating-points-v2"; 258*724ba675SRob Herring opp-shared; 259*724ba675SRob Herring 260*724ba675SRob Herring opp-480000000 { 261*724ba675SRob Herring opp-hz = /bits/ 64 <480000000>; 262*724ba675SRob Herring opp-microvolt = <840000>; 263*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 264*724ba675SRob Herring }; 265*724ba675SRob Herring 266*724ba675SRob Herring opp-600000000 { 267*724ba675SRob Herring opp-hz = /bits/ 64 <600000000>; 268*724ba675SRob Herring opp-microvolt = <840000>; 269*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 270*724ba675SRob Herring }; 271*724ba675SRob Herring 272*724ba675SRob Herring opp-720000000 { 273*724ba675SRob Herring opp-hz = /bits/ 64 <720000000>; 274*724ba675SRob Herring opp-microvolt = <840000>; 275*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 276*724ba675SRob Herring }; 277*724ba675SRob Herring 278*724ba675SRob Herring opp-864000000 { 279*724ba675SRob Herring opp-hz = /bits/ 64 <864000000>; 280*724ba675SRob Herring opp-microvolt = <840000>; 281*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 282*724ba675SRob Herring }; 283*724ba675SRob Herring 284*724ba675SRob Herring opp-912000000 { 285*724ba675SRob Herring opp-hz = /bits/ 64 <912000000>; 286*724ba675SRob Herring opp-microvolt = <840000>; 287*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 288*724ba675SRob Herring }; 289*724ba675SRob Herring 290*724ba675SRob Herring opp-1008000000 { 291*724ba675SRob Herring opp-hz = /bits/ 64 <1008000000>; 292*724ba675SRob Herring opp-microvolt = <840000>; 293*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 294*724ba675SRob Herring }; 295*724ba675SRob Herring 296*724ba675SRob Herring opp-1128000000 { 297*724ba675SRob Herring opp-hz = /bits/ 64 <1128000000>; 298*724ba675SRob Herring opp-microvolt = <840000>; 299*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 300*724ba675SRob Herring }; 301*724ba675SRob Herring 302*724ba675SRob Herring opp-1200000000 { 303*724ba675SRob Herring opp-hz = /bits/ 64 <1200000000>; 304*724ba675SRob Herring opp-microvolt = <840000>; 305*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 306*724ba675SRob Herring }; 307*724ba675SRob Herring }; 308*724ba675SRob Herring 309*724ba675SRob Herring soc { 310*724ba675SRob Herring compatible = "simple-bus"; 311*724ba675SRob Herring #address-cells = <1>; 312*724ba675SRob Herring #size-cells = <1>; 313*724ba675SRob Herring ranges; 314*724ba675SRob Herring 315*724ba675SRob Herring display_clocks: clock@1000000 { 316*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-de2-clk"; 317*724ba675SRob Herring reg = <0x01000000 0x10000>; 318*724ba675SRob Herring clocks = <&ccu CLK_BUS_DE>, 319*724ba675SRob Herring <&ccu CLK_PLL_DE>; 320*724ba675SRob Herring clock-names = "bus", 321*724ba675SRob Herring "mod"; 322*724ba675SRob Herring resets = <&ccu RST_BUS_DE>; 323*724ba675SRob Herring #clock-cells = <1>; 324*724ba675SRob Herring #reset-cells = <1>; 325*724ba675SRob Herring }; 326*724ba675SRob Herring 327*724ba675SRob Herring rotate: rotate@1020000 { 328*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-de2-rotate"; 329*724ba675SRob Herring reg = <0x1020000 0x10000>; 330*724ba675SRob Herring interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 331*724ba675SRob Herring clocks = <&display_clocks CLK_BUS_ROT>, 332*724ba675SRob Herring <&display_clocks CLK_ROT>; 333*724ba675SRob Herring clock-names = "bus", 334*724ba675SRob Herring "mod"; 335*724ba675SRob Herring resets = <&display_clocks RST_ROT>; 336*724ba675SRob Herring }; 337*724ba675SRob Herring 338*724ba675SRob Herring mixer0: mixer@1100000 { 339*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-de2-mixer-0"; 340*724ba675SRob Herring reg = <0x01100000 0x100000>; 341*724ba675SRob Herring clocks = <&display_clocks CLK_BUS_MIXER0>, 342*724ba675SRob Herring <&display_clocks CLK_MIXER0>; 343*724ba675SRob Herring clock-names = "bus", 344*724ba675SRob Herring "mod"; 345*724ba675SRob Herring resets = <&display_clocks RST_MIXER0>; 346*724ba675SRob Herring 347*724ba675SRob Herring ports { 348*724ba675SRob Herring #address-cells = <1>; 349*724ba675SRob Herring #size-cells = <0>; 350*724ba675SRob Herring 351*724ba675SRob Herring mixer0_out: port@1 { 352*724ba675SRob Herring #address-cells = <1>; 353*724ba675SRob Herring #size-cells = <0>; 354*724ba675SRob Herring reg = <1>; 355*724ba675SRob Herring 356*724ba675SRob Herring mixer0_out_tcon0: endpoint@0 { 357*724ba675SRob Herring reg = <0>; 358*724ba675SRob Herring remote-endpoint = <&tcon0_in_mixer0>; 359*724ba675SRob Herring }; 360*724ba675SRob Herring 361*724ba675SRob Herring mixer0_out_tcon1: endpoint@1 { 362*724ba675SRob Herring reg = <1>; 363*724ba675SRob Herring remote-endpoint = <&tcon1_in_mixer0>; 364*724ba675SRob Herring }; 365*724ba675SRob Herring }; 366*724ba675SRob Herring }; 367*724ba675SRob Herring }; 368*724ba675SRob Herring 369*724ba675SRob Herring mixer1: mixer@1200000 { 370*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-de2-mixer-1"; 371*724ba675SRob Herring reg = <0x01200000 0x100000>; 372*724ba675SRob Herring clocks = <&display_clocks CLK_BUS_MIXER1>, 373*724ba675SRob Herring <&display_clocks CLK_MIXER1>; 374*724ba675SRob Herring clock-names = "bus", 375*724ba675SRob Herring "mod"; 376*724ba675SRob Herring resets = <&display_clocks RST_WB>; 377*724ba675SRob Herring 378*724ba675SRob Herring ports { 379*724ba675SRob Herring #address-cells = <1>; 380*724ba675SRob Herring #size-cells = <0>; 381*724ba675SRob Herring 382*724ba675SRob Herring mixer1_out: port@1 { 383*724ba675SRob Herring #address-cells = <1>; 384*724ba675SRob Herring #size-cells = <0>; 385*724ba675SRob Herring reg = <1>; 386*724ba675SRob Herring 387*724ba675SRob Herring mixer1_out_tcon0: endpoint@0 { 388*724ba675SRob Herring reg = <0>; 389*724ba675SRob Herring remote-endpoint = <&tcon0_in_mixer1>; 390*724ba675SRob Herring }; 391*724ba675SRob Herring 392*724ba675SRob Herring mixer1_out_tcon1: endpoint@1 { 393*724ba675SRob Herring reg = <1>; 394*724ba675SRob Herring remote-endpoint = <&tcon1_in_mixer1>; 395*724ba675SRob Herring }; 396*724ba675SRob Herring }; 397*724ba675SRob Herring }; 398*724ba675SRob Herring }; 399*724ba675SRob Herring 400*724ba675SRob Herring cpucfg@1700000 { 401*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-cpucfg"; 402*724ba675SRob Herring reg = <0x01700000 0x400>; 403*724ba675SRob Herring }; 404*724ba675SRob Herring 405*724ba675SRob Herring cci@1790000 { 406*724ba675SRob Herring compatible = "arm,cci-400"; 407*724ba675SRob Herring #address-cells = <1>; 408*724ba675SRob Herring #size-cells = <1>; 409*724ba675SRob Herring reg = <0x01790000 0x10000>; 410*724ba675SRob Herring ranges = <0x0 0x01790000 0x10000>; 411*724ba675SRob Herring 412*724ba675SRob Herring cci_control0: slave-if@4000 { 413*724ba675SRob Herring compatible = "arm,cci-400-ctrl-if"; 414*724ba675SRob Herring interface-type = "ace"; 415*724ba675SRob Herring reg = <0x4000 0x1000>; 416*724ba675SRob Herring }; 417*724ba675SRob Herring 418*724ba675SRob Herring cci_control1: slave-if@5000 { 419*724ba675SRob Herring compatible = "arm,cci-400-ctrl-if"; 420*724ba675SRob Herring interface-type = "ace"; 421*724ba675SRob Herring reg = <0x5000 0x1000>; 422*724ba675SRob Herring }; 423*724ba675SRob Herring 424*724ba675SRob Herring pmu@9000 { 425*724ba675SRob Herring compatible = "arm,cci-400-pmu,r1"; 426*724ba675SRob Herring reg = <0x9000 0x5000>; 427*724ba675SRob Herring interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 428*724ba675SRob Herring <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 429*724ba675SRob Herring <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 430*724ba675SRob Herring <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 431*724ba675SRob Herring <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 432*724ba675SRob Herring <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 433*724ba675SRob Herring <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 434*724ba675SRob Herring <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 435*724ba675SRob Herring }; 436*724ba675SRob Herring }; 437*724ba675SRob Herring 438*724ba675SRob Herring syscon: syscon@1c00000 { 439*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-system-controller", 440*724ba675SRob Herring "syscon"; 441*724ba675SRob Herring reg = <0x01c00000 0x1000>; 442*724ba675SRob Herring }; 443*724ba675SRob Herring 444*724ba675SRob Herring dma: dma-controller@1c02000 { 445*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-dma"; 446*724ba675SRob Herring reg = <0x01c02000 0x1000>; 447*724ba675SRob Herring interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 448*724ba675SRob Herring clocks = <&ccu CLK_BUS_DMA>; 449*724ba675SRob Herring resets = <&ccu RST_BUS_DMA>; 450*724ba675SRob Herring #dma-cells = <1>; 451*724ba675SRob Herring }; 452*724ba675SRob Herring 453*724ba675SRob Herring tcon0: lcd-controller@1c0c000 { 454*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-tcon-lcd"; 455*724ba675SRob Herring reg = <0x01c0c000 0x1000>; 456*724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 457*724ba675SRob Herring clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 458*724ba675SRob Herring clock-names = "ahb", "tcon-ch0"; 459*724ba675SRob Herring clock-output-names = "tcon-data-clock"; 460*724ba675SRob Herring #clock-cells = <0>; 461*724ba675SRob Herring resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 462*724ba675SRob Herring reset-names = "lcd", "lvds"; 463*724ba675SRob Herring 464*724ba675SRob Herring ports { 465*724ba675SRob Herring #address-cells = <1>; 466*724ba675SRob Herring #size-cells = <0>; 467*724ba675SRob Herring 468*724ba675SRob Herring tcon0_in: port@0 { 469*724ba675SRob Herring #address-cells = <1>; 470*724ba675SRob Herring #size-cells = <0>; 471*724ba675SRob Herring reg = <0>; 472*724ba675SRob Herring 473*724ba675SRob Herring tcon0_in_mixer0: endpoint@0 { 474*724ba675SRob Herring reg = <0>; 475*724ba675SRob Herring remote-endpoint = <&mixer0_out_tcon0>; 476*724ba675SRob Herring }; 477*724ba675SRob Herring 478*724ba675SRob Herring tcon0_in_mixer1: endpoint@1 { 479*724ba675SRob Herring reg = <1>; 480*724ba675SRob Herring remote-endpoint = <&mixer1_out_tcon0>; 481*724ba675SRob Herring }; 482*724ba675SRob Herring }; 483*724ba675SRob Herring 484*724ba675SRob Herring tcon0_out: port@1 { 485*724ba675SRob Herring reg = <1>; 486*724ba675SRob Herring }; 487*724ba675SRob Herring }; 488*724ba675SRob Herring }; 489*724ba675SRob Herring 490*724ba675SRob Herring tcon1: lcd-controller@1c0d000 { 491*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-tcon-tv"; 492*724ba675SRob Herring reg = <0x01c0d000 0x1000>; 493*724ba675SRob Herring interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 494*724ba675SRob Herring clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 495*724ba675SRob Herring clock-names = "ahb", "tcon-ch1"; 496*724ba675SRob Herring resets = <&ccu RST_BUS_TCON1>; 497*724ba675SRob Herring reset-names = "lcd"; 498*724ba675SRob Herring 499*724ba675SRob Herring ports { 500*724ba675SRob Herring #address-cells = <1>; 501*724ba675SRob Herring #size-cells = <0>; 502*724ba675SRob Herring 503*724ba675SRob Herring tcon1_in: port@0 { 504*724ba675SRob Herring #address-cells = <1>; 505*724ba675SRob Herring #size-cells = <0>; 506*724ba675SRob Herring reg = <0>; 507*724ba675SRob Herring 508*724ba675SRob Herring tcon1_in_mixer0: endpoint@0 { 509*724ba675SRob Herring reg = <0>; 510*724ba675SRob Herring remote-endpoint = <&mixer0_out_tcon1>; 511*724ba675SRob Herring }; 512*724ba675SRob Herring 513*724ba675SRob Herring tcon1_in_mixer1: endpoint@1 { 514*724ba675SRob Herring reg = <1>; 515*724ba675SRob Herring remote-endpoint = <&mixer1_out_tcon1>; 516*724ba675SRob Herring }; 517*724ba675SRob Herring }; 518*724ba675SRob Herring 519*724ba675SRob Herring tcon1_out: port@1 { 520*724ba675SRob Herring #address-cells = <1>; 521*724ba675SRob Herring #size-cells = <0>; 522*724ba675SRob Herring reg = <1>; 523*724ba675SRob Herring 524*724ba675SRob Herring tcon1_out_hdmi: endpoint@1 { 525*724ba675SRob Herring reg = <1>; 526*724ba675SRob Herring remote-endpoint = <&hdmi_in_tcon1>; 527*724ba675SRob Herring }; 528*724ba675SRob Herring }; 529*724ba675SRob Herring }; 530*724ba675SRob Herring }; 531*724ba675SRob Herring 532*724ba675SRob Herring mmc0: mmc@1c0f000 { 533*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-mmc", 534*724ba675SRob Herring "allwinner,sun7i-a20-mmc"; 535*724ba675SRob Herring reg = <0x01c0f000 0x1000>; 536*724ba675SRob Herring clocks = <&ccu CLK_BUS_MMC0>, 537*724ba675SRob Herring <&ccu CLK_MMC0>, 538*724ba675SRob Herring <&ccu CLK_MMC0_OUTPUT>, 539*724ba675SRob Herring <&ccu CLK_MMC0_SAMPLE>; 540*724ba675SRob Herring clock-names = "ahb", 541*724ba675SRob Herring "mmc", 542*724ba675SRob Herring "output", 543*724ba675SRob Herring "sample"; 544*724ba675SRob Herring resets = <&ccu RST_BUS_MMC0>; 545*724ba675SRob Herring reset-names = "ahb"; 546*724ba675SRob Herring interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 547*724ba675SRob Herring status = "disabled"; 548*724ba675SRob Herring #address-cells = <1>; 549*724ba675SRob Herring #size-cells = <0>; 550*724ba675SRob Herring }; 551*724ba675SRob Herring 552*724ba675SRob Herring mmc1: mmc@1c10000 { 553*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-mmc", 554*724ba675SRob Herring "allwinner,sun7i-a20-mmc"; 555*724ba675SRob Herring reg = <0x01c10000 0x1000>; 556*724ba675SRob Herring clocks = <&ccu CLK_BUS_MMC1>, 557*724ba675SRob Herring <&ccu CLK_MMC1>, 558*724ba675SRob Herring <&ccu CLK_MMC1_OUTPUT>, 559*724ba675SRob Herring <&ccu CLK_MMC1_SAMPLE>; 560*724ba675SRob Herring clock-names = "ahb", 561*724ba675SRob Herring "mmc", 562*724ba675SRob Herring "output", 563*724ba675SRob Herring "sample"; 564*724ba675SRob Herring resets = <&ccu RST_BUS_MMC1>; 565*724ba675SRob Herring reset-names = "ahb"; 566*724ba675SRob Herring interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 567*724ba675SRob Herring pinctrl-names = "default"; 568*724ba675SRob Herring pinctrl-0 = <&mmc1_pins>; 569*724ba675SRob Herring status = "disabled"; 570*724ba675SRob Herring #address-cells = <1>; 571*724ba675SRob Herring #size-cells = <0>; 572*724ba675SRob Herring }; 573*724ba675SRob Herring 574*724ba675SRob Herring mmc2: mmc@1c11000 { 575*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-emmc"; 576*724ba675SRob Herring reg = <0x01c11000 0x1000>; 577*724ba675SRob Herring clocks = <&ccu CLK_BUS_MMC2>, 578*724ba675SRob Herring <&ccu CLK_MMC2>, 579*724ba675SRob Herring <&ccu CLK_MMC2_OUTPUT>, 580*724ba675SRob Herring <&ccu CLK_MMC2_SAMPLE>; 581*724ba675SRob Herring clock-names = "ahb", 582*724ba675SRob Herring "mmc", 583*724ba675SRob Herring "output", 584*724ba675SRob Herring "sample"; 585*724ba675SRob Herring resets = <&ccu RST_BUS_MMC2>; 586*724ba675SRob Herring reset-names = "ahb"; 587*724ba675SRob Herring interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 588*724ba675SRob Herring status = "disabled"; 589*724ba675SRob Herring #address-cells = <1>; 590*724ba675SRob Herring #size-cells = <0>; 591*724ba675SRob Herring }; 592*724ba675SRob Herring 593*724ba675SRob Herring sid: eeprom@1c14000 { 594*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-sid"; 595*724ba675SRob Herring reg = <0x1c14000 0x400>; 596*724ba675SRob Herring #address-cells = <1>; 597*724ba675SRob Herring #size-cells = <1>; 598*724ba675SRob Herring 599*724ba675SRob Herring ths_calibration: thermal-sensor-calibration@34 { 600*724ba675SRob Herring reg = <0x34 8>; 601*724ba675SRob Herring }; 602*724ba675SRob Herring }; 603*724ba675SRob Herring 604*724ba675SRob Herring crypto: crypto@1c15000 { 605*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-crypto"; 606*724ba675SRob Herring reg = <0x01c15000 0x1000>; 607*724ba675SRob Herring interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 608*724ba675SRob Herring resets = <&ccu RST_BUS_SS>; 609*724ba675SRob Herring clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; 610*724ba675SRob Herring clock-names = "bus", "mod"; 611*724ba675SRob Herring }; 612*724ba675SRob Herring 613*724ba675SRob Herring msgbox: mailbox@1c17000 { 614*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-msgbox", 615*724ba675SRob Herring "allwinner,sun6i-a31-msgbox"; 616*724ba675SRob Herring reg = <0x01c17000 0x1000>; 617*724ba675SRob Herring clocks = <&ccu CLK_BUS_MSGBOX>; 618*724ba675SRob Herring resets = <&ccu RST_BUS_MSGBOX>; 619*724ba675SRob Herring interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 620*724ba675SRob Herring #mbox-cells = <1>; 621*724ba675SRob Herring }; 622*724ba675SRob Herring 623*724ba675SRob Herring usb_otg: usb@1c19000 { 624*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-musb", 625*724ba675SRob Herring "allwinner,sun8i-a33-musb"; 626*724ba675SRob Herring reg = <0x01c19000 0x0400>; 627*724ba675SRob Herring clocks = <&ccu CLK_BUS_OTG>; 628*724ba675SRob Herring resets = <&ccu RST_BUS_OTG>; 629*724ba675SRob Herring interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 630*724ba675SRob Herring interrupt-names = "mc"; 631*724ba675SRob Herring phys = <&usbphy 0>; 632*724ba675SRob Herring phy-names = "usb"; 633*724ba675SRob Herring extcon = <&usbphy 0>; 634*724ba675SRob Herring dr_mode = "otg"; 635*724ba675SRob Herring status = "disabled"; 636*724ba675SRob Herring }; 637*724ba675SRob Herring 638*724ba675SRob Herring usbphy: phy@1c19400 { 639*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-usb-phy"; 640*724ba675SRob Herring reg = <0x01c19400 0x10>, 641*724ba675SRob Herring <0x01c1a800 0x14>, 642*724ba675SRob Herring <0x01c1b800 0x14>; 643*724ba675SRob Herring reg-names = "phy_ctrl", 644*724ba675SRob Herring "pmu1", 645*724ba675SRob Herring "pmu2"; 646*724ba675SRob Herring clocks = <&ccu CLK_USB_PHY0>, 647*724ba675SRob Herring <&ccu CLK_USB_PHY1>, 648*724ba675SRob Herring <&ccu CLK_USB_HSIC>, 649*724ba675SRob Herring <&ccu CLK_USB_HSIC_12M>; 650*724ba675SRob Herring clock-names = "usb0_phy", 651*724ba675SRob Herring "usb1_phy", 652*724ba675SRob Herring "usb2_phy", 653*724ba675SRob Herring "usb2_hsic_12M"; 654*724ba675SRob Herring resets = <&ccu RST_USB_PHY0>, 655*724ba675SRob Herring <&ccu RST_USB_PHY1>, 656*724ba675SRob Herring <&ccu RST_USB_HSIC>; 657*724ba675SRob Herring reset-names = "usb0_reset", 658*724ba675SRob Herring "usb1_reset", 659*724ba675SRob Herring "usb2_reset"; 660*724ba675SRob Herring status = "disabled"; 661*724ba675SRob Herring #phy-cells = <1>; 662*724ba675SRob Herring }; 663*724ba675SRob Herring 664*724ba675SRob Herring ehci0: usb@1c1a000 { 665*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-ehci", 666*724ba675SRob Herring "generic-ehci"; 667*724ba675SRob Herring reg = <0x01c1a000 0x100>; 668*724ba675SRob Herring interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 669*724ba675SRob Herring clocks = <&ccu CLK_BUS_EHCI0>; 670*724ba675SRob Herring resets = <&ccu RST_BUS_EHCI0>; 671*724ba675SRob Herring phys = <&usbphy 1>; 672*724ba675SRob Herring phy-names = "usb"; 673*724ba675SRob Herring status = "disabled"; 674*724ba675SRob Herring }; 675*724ba675SRob Herring 676*724ba675SRob Herring ohci0: usb@1c1a400 { 677*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-ohci", 678*724ba675SRob Herring "generic-ohci"; 679*724ba675SRob Herring reg = <0x01c1a400 0x100>; 680*724ba675SRob Herring interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 681*724ba675SRob Herring clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; 682*724ba675SRob Herring resets = <&ccu RST_BUS_OHCI0>; 683*724ba675SRob Herring phys = <&usbphy 1>; 684*724ba675SRob Herring phy-names = "usb"; 685*724ba675SRob Herring status = "disabled"; 686*724ba675SRob Herring }; 687*724ba675SRob Herring 688*724ba675SRob Herring ehci1: usb@1c1b000 { 689*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-ehci", 690*724ba675SRob Herring "generic-ehci"; 691*724ba675SRob Herring reg = <0x01c1b000 0x100>; 692*724ba675SRob Herring interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 693*724ba675SRob Herring clocks = <&ccu CLK_BUS_EHCI1>; 694*724ba675SRob Herring resets = <&ccu RST_BUS_EHCI1>; 695*724ba675SRob Herring phys = <&usbphy 2>; 696*724ba675SRob Herring phy-names = "usb"; 697*724ba675SRob Herring status = "disabled"; 698*724ba675SRob Herring }; 699*724ba675SRob Herring 700*724ba675SRob Herring ccu: clock@1c20000 { 701*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-ccu"; 702*724ba675SRob Herring reg = <0x01c20000 0x400>; 703*724ba675SRob Herring clocks = <&osc24M>, <&osc16Md512>; 704*724ba675SRob Herring clock-names = "hosc", "losc"; 705*724ba675SRob Herring #clock-cells = <1>; 706*724ba675SRob Herring #reset-cells = <1>; 707*724ba675SRob Herring }; 708*724ba675SRob Herring 709*724ba675SRob Herring pio: pinctrl@1c20800 { 710*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-pinctrl"; 711*724ba675SRob Herring interrupt-parent = <&r_intc>; 712*724ba675SRob Herring interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 713*724ba675SRob Herring <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 714*724ba675SRob Herring <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 715*724ba675SRob Herring reg = <0x01c20800 0x400>; 716*724ba675SRob Herring clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>; 717*724ba675SRob Herring clock-names = "apb", "hosc", "losc"; 718*724ba675SRob Herring gpio-controller; 719*724ba675SRob Herring interrupt-controller; 720*724ba675SRob Herring #interrupt-cells = <3>; 721*724ba675SRob Herring #gpio-cells = <3>; 722*724ba675SRob Herring 723*724ba675SRob Herring /omit-if-no-ref/ 724*724ba675SRob Herring csi_8bit_parallel_pins: csi-8bit-parallel-pins { 725*724ba675SRob Herring pins = "PE0", "PE2", "PE3", "PE6", "PE7", 726*724ba675SRob Herring "PE8", "PE9", "PE10", "PE11", 727*724ba675SRob Herring "PE12", "PE13"; 728*724ba675SRob Herring function = "csi"; 729*724ba675SRob Herring }; 730*724ba675SRob Herring 731*724ba675SRob Herring /omit-if-no-ref/ 732*724ba675SRob Herring csi_mclk_pin: csi-mclk-pin { 733*724ba675SRob Herring pins = "PE1"; 734*724ba675SRob Herring function = "csi"; 735*724ba675SRob Herring }; 736*724ba675SRob Herring 737*724ba675SRob Herring emac_rgmii_pins: emac-rgmii-pins { 738*724ba675SRob Herring pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 739*724ba675SRob Herring "PD11", "PD12", "PD13", "PD14", "PD18", 740*724ba675SRob Herring "PD19", "PD21", "PD22", "PD23"; 741*724ba675SRob Herring function = "gmac"; 742*724ba675SRob Herring /* 743*724ba675SRob Herring * data lines in RGMII mode use DDR mode 744*724ba675SRob Herring * and need a higher signal drive strength 745*724ba675SRob Herring */ 746*724ba675SRob Herring drive-strength = <40>; 747*724ba675SRob Herring }; 748*724ba675SRob Herring 749*724ba675SRob Herring hdmi_pins: hdmi-pins { 750*724ba675SRob Herring pins = "PH6", "PH7", "PH8"; 751*724ba675SRob Herring function = "hdmi"; 752*724ba675SRob Herring }; 753*724ba675SRob Herring 754*724ba675SRob Herring i2c0_pins: i2c0-pins { 755*724ba675SRob Herring pins = "PH0", "PH1"; 756*724ba675SRob Herring function = "i2c0"; 757*724ba675SRob Herring }; 758*724ba675SRob Herring 759*724ba675SRob Herring i2c1_pins: i2c1-pins { 760*724ba675SRob Herring pins = "PH2", "PH3"; 761*724ba675SRob Herring function = "i2c1"; 762*724ba675SRob Herring }; 763*724ba675SRob Herring 764*724ba675SRob Herring /omit-if-no-ref/ 765*724ba675SRob Herring i2c2_pe_pins: i2c2-pe-pins { 766*724ba675SRob Herring pins = "PE14", "PE15"; 767*724ba675SRob Herring function = "i2c2"; 768*724ba675SRob Herring }; 769*724ba675SRob Herring 770*724ba675SRob Herring i2c2_ph_pins: i2c2-ph-pins { 771*724ba675SRob Herring pins = "PH4", "PH5"; 772*724ba675SRob Herring function = "i2c2"; 773*724ba675SRob Herring }; 774*724ba675SRob Herring 775*724ba675SRob Herring i2s1_pins: i2s1-pins { 776*724ba675SRob Herring /* I2S1 does not have external MCLK pin */ 777*724ba675SRob Herring pins = "PG10", "PG11", "PG12", "PG13"; 778*724ba675SRob Herring function = "i2s1"; 779*724ba675SRob Herring }; 780*724ba675SRob Herring 781*724ba675SRob Herring lcd_lvds_pins: lcd-lvds-pins { 782*724ba675SRob Herring pins = "PD18", "PD19", "PD20", "PD21", "PD22", 783*724ba675SRob Herring "PD23", "PD24", "PD25", "PD26", "PD27"; 784*724ba675SRob Herring function = "lvds0"; 785*724ba675SRob Herring }; 786*724ba675SRob Herring 787*724ba675SRob Herring mmc0_pins: mmc0-pins { 788*724ba675SRob Herring pins = "PF0", "PF1", "PF2", 789*724ba675SRob Herring "PF3", "PF4", "PF5"; 790*724ba675SRob Herring function = "mmc0"; 791*724ba675SRob Herring drive-strength = <30>; 792*724ba675SRob Herring bias-pull-up; 793*724ba675SRob Herring }; 794*724ba675SRob Herring 795*724ba675SRob Herring mmc1_pins: mmc1-pins { 796*724ba675SRob Herring pins = "PG0", "PG1", "PG2", 797*724ba675SRob Herring "PG3", "PG4", "PG5"; 798*724ba675SRob Herring function = "mmc1"; 799*724ba675SRob Herring drive-strength = <30>; 800*724ba675SRob Herring bias-pull-up; 801*724ba675SRob Herring }; 802*724ba675SRob Herring 803*724ba675SRob Herring mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { 804*724ba675SRob Herring pins = "PC5", "PC6", "PC8", "PC9", 805*724ba675SRob Herring "PC10", "PC11", "PC12", "PC13", 806*724ba675SRob Herring "PC14", "PC15", "PC16"; 807*724ba675SRob Herring function = "mmc2"; 808*724ba675SRob Herring drive-strength = <30>; 809*724ba675SRob Herring bias-pull-up; 810*724ba675SRob Herring }; 811*724ba675SRob Herring 812*724ba675SRob Herring pwm_pin: pwm-pin { 813*724ba675SRob Herring pins = "PD28"; 814*724ba675SRob Herring function = "pwm"; 815*724ba675SRob Herring }; 816*724ba675SRob Herring 817*724ba675SRob Herring spdif_tx_pin: spdif-tx-pin { 818*724ba675SRob Herring pins = "PE18"; 819*724ba675SRob Herring function = "spdif"; 820*724ba675SRob Herring }; 821*724ba675SRob Herring 822*724ba675SRob Herring uart0_pb_pins: uart0-pb-pins { 823*724ba675SRob Herring pins = "PB9", "PB10"; 824*724ba675SRob Herring function = "uart0"; 825*724ba675SRob Herring }; 826*724ba675SRob Herring 827*724ba675SRob Herring uart0_pf_pins: uart0-pf-pins { 828*724ba675SRob Herring pins = "PF2", "PF4"; 829*724ba675SRob Herring function = "uart0"; 830*724ba675SRob Herring }; 831*724ba675SRob Herring 832*724ba675SRob Herring uart1_pins: uart1-pins { 833*724ba675SRob Herring pins = "PG6", "PG7"; 834*724ba675SRob Herring function = "uart1"; 835*724ba675SRob Herring }; 836*724ba675SRob Herring 837*724ba675SRob Herring uart1_rts_cts_pins: uart1-rts-cts-pins { 838*724ba675SRob Herring pins = "PG8", "PG9"; 839*724ba675SRob Herring function = "uart1"; 840*724ba675SRob Herring }; 841*724ba675SRob Herring 842*724ba675SRob Herring /omit-if-no-ref/ 843*724ba675SRob Herring uart2_pb_pins: uart2-pb-pins { 844*724ba675SRob Herring pins = "PB0", "PB1"; 845*724ba675SRob Herring function = "uart2"; 846*724ba675SRob Herring }; 847*724ba675SRob Herring }; 848*724ba675SRob Herring 849*724ba675SRob Herring timer@1c20c00 { 850*724ba675SRob Herring compatible = "allwinner,sun8i-a23-timer"; 851*724ba675SRob Herring reg = <0x01c20c00 0xa0>; 852*724ba675SRob Herring interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 853*724ba675SRob Herring <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 854*724ba675SRob Herring clocks = <&osc24M>; 855*724ba675SRob Herring }; 856*724ba675SRob Herring 857*724ba675SRob Herring watchdog@1c20ca0 { 858*724ba675SRob Herring compatible = "allwinner,sun6i-a31-wdt"; 859*724ba675SRob Herring reg = <0x01c20ca0 0x20>; 860*724ba675SRob Herring interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 861*724ba675SRob Herring clocks = <&osc24M>; 862*724ba675SRob Herring }; 863*724ba675SRob Herring 864*724ba675SRob Herring spdif: spdif@1c21000 { 865*724ba675SRob Herring #sound-dai-cells = <0>; 866*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-spdif", 867*724ba675SRob Herring "allwinner,sun8i-h3-spdif"; 868*724ba675SRob Herring reg = <0x01c21000 0x400>; 869*724ba675SRob Herring interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 870*724ba675SRob Herring clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 871*724ba675SRob Herring resets = <&ccu RST_BUS_SPDIF>; 872*724ba675SRob Herring clock-names = "apb", "spdif"; 873*724ba675SRob Herring dmas = <&dma 2>; 874*724ba675SRob Herring dma-names = "tx"; 875*724ba675SRob Herring pinctrl-names = "default"; 876*724ba675SRob Herring pinctrl-0 = <&spdif_tx_pin>; 877*724ba675SRob Herring status = "disabled"; 878*724ba675SRob Herring }; 879*724ba675SRob Herring 880*724ba675SRob Herring i2s0: i2s@1c22000 { 881*724ba675SRob Herring #sound-dai-cells = <0>; 882*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-i2s"; 883*724ba675SRob Herring reg = <0x01c22000 0x400>; 884*724ba675SRob Herring interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 885*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 886*724ba675SRob Herring clock-names = "apb", "mod"; 887*724ba675SRob Herring dmas = <&dma 3>, <&dma 3>; 888*724ba675SRob Herring resets = <&ccu RST_BUS_I2S0>; 889*724ba675SRob Herring dma-names = "rx", "tx"; 890*724ba675SRob Herring status = "disabled"; 891*724ba675SRob Herring }; 892*724ba675SRob Herring 893*724ba675SRob Herring i2s1: i2s@1c22400 { 894*724ba675SRob Herring #sound-dai-cells = <0>; 895*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-i2s"; 896*724ba675SRob Herring reg = <0x01c22400 0x400>; 897*724ba675SRob Herring interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 898*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 899*724ba675SRob Herring clock-names = "apb", "mod"; 900*724ba675SRob Herring dmas = <&dma 4>, <&dma 4>; 901*724ba675SRob Herring resets = <&ccu RST_BUS_I2S1>; 902*724ba675SRob Herring dma-names = "rx", "tx"; 903*724ba675SRob Herring pinctrl-names = "default"; 904*724ba675SRob Herring pinctrl-0 = <&i2s1_pins>; 905*724ba675SRob Herring status = "disabled"; 906*724ba675SRob Herring }; 907*724ba675SRob Herring 908*724ba675SRob Herring i2s2: i2s@1c22800 { 909*724ba675SRob Herring #sound-dai-cells = <0>; 910*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-i2s"; 911*724ba675SRob Herring reg = <0x01c22800 0x400>; 912*724ba675SRob Herring interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 913*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 914*724ba675SRob Herring clock-names = "apb", "mod"; 915*724ba675SRob Herring dmas = <&dma 27>; 916*724ba675SRob Herring resets = <&ccu RST_BUS_I2S2>; 917*724ba675SRob Herring dma-names = "tx"; 918*724ba675SRob Herring status = "disabled"; 919*724ba675SRob Herring }; 920*724ba675SRob Herring 921*724ba675SRob Herring pwm: pwm@1c21400 { 922*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-pwm", 923*724ba675SRob Herring "allwinner,sun8i-h3-pwm"; 924*724ba675SRob Herring reg = <0x01c21400 0x400>; 925*724ba675SRob Herring clocks = <&osc24M>; 926*724ba675SRob Herring #pwm-cells = <3>; 927*724ba675SRob Herring status = "disabled"; 928*724ba675SRob Herring }; 929*724ba675SRob Herring 930*724ba675SRob Herring uart0: serial@1c28000 { 931*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 932*724ba675SRob Herring reg = <0x01c28000 0x400>; 933*724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 934*724ba675SRob Herring reg-shift = <2>; 935*724ba675SRob Herring reg-io-width = <4>; 936*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART0>; 937*724ba675SRob Herring resets = <&ccu RST_BUS_UART0>; 938*724ba675SRob Herring status = "disabled"; 939*724ba675SRob Herring }; 940*724ba675SRob Herring 941*724ba675SRob Herring uart1: serial@1c28400 { 942*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 943*724ba675SRob Herring reg = <0x01c28400 0x400>; 944*724ba675SRob Herring interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 945*724ba675SRob Herring reg-shift = <2>; 946*724ba675SRob Herring reg-io-width = <4>; 947*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART1>; 948*724ba675SRob Herring resets = <&ccu RST_BUS_UART1>; 949*724ba675SRob Herring status = "disabled"; 950*724ba675SRob Herring }; 951*724ba675SRob Herring 952*724ba675SRob Herring uart2: serial@1c28800 { 953*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 954*724ba675SRob Herring reg = <0x01c28800 0x400>; 955*724ba675SRob Herring interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 956*724ba675SRob Herring reg-shift = <2>; 957*724ba675SRob Herring reg-io-width = <4>; 958*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART2>; 959*724ba675SRob Herring resets = <&ccu RST_BUS_UART2>; 960*724ba675SRob Herring status = "disabled"; 961*724ba675SRob Herring }; 962*724ba675SRob Herring 963*724ba675SRob Herring uart3: serial@1c28c00 { 964*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 965*724ba675SRob Herring reg = <0x01c28c00 0x400>; 966*724ba675SRob Herring interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 967*724ba675SRob Herring reg-shift = <2>; 968*724ba675SRob Herring reg-io-width = <4>; 969*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART3>; 970*724ba675SRob Herring resets = <&ccu RST_BUS_UART3>; 971*724ba675SRob Herring status = "disabled"; 972*724ba675SRob Herring }; 973*724ba675SRob Herring 974*724ba675SRob Herring uart4: serial@1c29000 { 975*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 976*724ba675SRob Herring reg = <0x01c29000 0x400>; 977*724ba675SRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 978*724ba675SRob Herring reg-shift = <2>; 979*724ba675SRob Herring reg-io-width = <4>; 980*724ba675SRob Herring clocks = <&ccu CLK_BUS_UART4>; 981*724ba675SRob Herring resets = <&ccu RST_BUS_UART4>; 982*724ba675SRob Herring status = "disabled"; 983*724ba675SRob Herring }; 984*724ba675SRob Herring 985*724ba675SRob Herring i2c0: i2c@1c2ac00 { 986*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-i2c", 987*724ba675SRob Herring "allwinner,sun6i-a31-i2c"; 988*724ba675SRob Herring reg = <0x01c2ac00 0x400>; 989*724ba675SRob Herring interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 990*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C0>; 991*724ba675SRob Herring resets = <&ccu RST_BUS_I2C0>; 992*724ba675SRob Herring pinctrl-names = "default"; 993*724ba675SRob Herring pinctrl-0 = <&i2c0_pins>; 994*724ba675SRob Herring status = "disabled"; 995*724ba675SRob Herring #address-cells = <1>; 996*724ba675SRob Herring #size-cells = <0>; 997*724ba675SRob Herring }; 998*724ba675SRob Herring 999*724ba675SRob Herring i2c1: i2c@1c2b000 { 1000*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-i2c", 1001*724ba675SRob Herring "allwinner,sun6i-a31-i2c"; 1002*724ba675SRob Herring reg = <0x01c2b000 0x400>; 1003*724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1004*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C1>; 1005*724ba675SRob Herring resets = <&ccu RST_BUS_I2C1>; 1006*724ba675SRob Herring pinctrl-names = "default"; 1007*724ba675SRob Herring pinctrl-0 = <&i2c1_pins>; 1008*724ba675SRob Herring status = "disabled"; 1009*724ba675SRob Herring #address-cells = <1>; 1010*724ba675SRob Herring #size-cells = <0>; 1011*724ba675SRob Herring }; 1012*724ba675SRob Herring 1013*724ba675SRob Herring i2c2: i2c@1c2b400 { 1014*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-i2c", 1015*724ba675SRob Herring "allwinner,sun6i-a31-i2c"; 1016*724ba675SRob Herring reg = <0x01c2b400 0x400>; 1017*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1018*724ba675SRob Herring clocks = <&ccu CLK_BUS_I2C2>; 1019*724ba675SRob Herring resets = <&ccu RST_BUS_I2C2>; 1020*724ba675SRob Herring status = "disabled"; 1021*724ba675SRob Herring #address-cells = <1>; 1022*724ba675SRob Herring #size-cells = <0>; 1023*724ba675SRob Herring }; 1024*724ba675SRob Herring 1025*724ba675SRob Herring emac: ethernet@1c30000 { 1026*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-emac"; 1027*724ba675SRob Herring syscon = <&syscon>; 1028*724ba675SRob Herring reg = <0x01c30000 0x104>; 1029*724ba675SRob Herring interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1030*724ba675SRob Herring interrupt-names = "macirq"; 1031*724ba675SRob Herring clocks = <&ccu CLK_BUS_EMAC>; 1032*724ba675SRob Herring clock-names = "stmmaceth"; 1033*724ba675SRob Herring resets = <&ccu RST_BUS_EMAC>; 1034*724ba675SRob Herring reset-names = "stmmaceth"; 1035*724ba675SRob Herring status = "disabled"; 1036*724ba675SRob Herring 1037*724ba675SRob Herring mdio: mdio { 1038*724ba675SRob Herring compatible = "snps,dwmac-mdio"; 1039*724ba675SRob Herring #address-cells = <1>; 1040*724ba675SRob Herring #size-cells = <0>; 1041*724ba675SRob Herring }; 1042*724ba675SRob Herring }; 1043*724ba675SRob Herring 1044*724ba675SRob Herring gic: interrupt-controller@1c81000 { 1045*724ba675SRob Herring compatible = "arm,gic-400"; 1046*724ba675SRob Herring reg = <0x01c81000 0x1000>, 1047*724ba675SRob Herring <0x01c82000 0x2000>, 1048*724ba675SRob Herring <0x01c84000 0x2000>, 1049*724ba675SRob Herring <0x01c86000 0x2000>; 1050*724ba675SRob Herring interrupt-controller; 1051*724ba675SRob Herring #interrupt-cells = <3>; 1052*724ba675SRob Herring interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1053*724ba675SRob Herring }; 1054*724ba675SRob Herring 1055*724ba675SRob Herring csi: camera@1cb0000 { 1056*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-csi"; 1057*724ba675SRob Herring reg = <0x01cb0000 0x1000>; 1058*724ba675SRob Herring interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1059*724ba675SRob Herring clocks = <&ccu CLK_BUS_CSI>, 1060*724ba675SRob Herring <&ccu CLK_CSI_SCLK>, 1061*724ba675SRob Herring <&ccu CLK_DRAM_CSI>; 1062*724ba675SRob Herring clock-names = "bus", "mod", "ram"; 1063*724ba675SRob Herring resets = <&ccu RST_BUS_CSI>; 1064*724ba675SRob Herring status = "disabled"; 1065*724ba675SRob Herring }; 1066*724ba675SRob Herring 1067*724ba675SRob Herring hdmi: hdmi@1ee0000 { 1068*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-dw-hdmi"; 1069*724ba675SRob Herring reg = <0x01ee0000 0x10000>; 1070*724ba675SRob Herring reg-io-width = <1>; 1071*724ba675SRob Herring interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1072*724ba675SRob Herring clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 1073*724ba675SRob Herring <&ccu CLK_HDMI>; 1074*724ba675SRob Herring clock-names = "iahb", "isfr", "tmds"; 1075*724ba675SRob Herring resets = <&ccu RST_BUS_HDMI1>; 1076*724ba675SRob Herring reset-names = "ctrl"; 1077*724ba675SRob Herring phys = <&hdmi_phy>; 1078*724ba675SRob Herring phy-names = "phy"; 1079*724ba675SRob Herring pinctrl-names = "default"; 1080*724ba675SRob Herring pinctrl-0 = <&hdmi_pins>; 1081*724ba675SRob Herring status = "disabled"; 1082*724ba675SRob Herring 1083*724ba675SRob Herring ports { 1084*724ba675SRob Herring #address-cells = <1>; 1085*724ba675SRob Herring #size-cells = <0>; 1086*724ba675SRob Herring 1087*724ba675SRob Herring hdmi_in: port@0 { 1088*724ba675SRob Herring reg = <0>; 1089*724ba675SRob Herring 1090*724ba675SRob Herring hdmi_in_tcon1: endpoint { 1091*724ba675SRob Herring remote-endpoint = <&tcon1_out_hdmi>; 1092*724ba675SRob Herring }; 1093*724ba675SRob Herring }; 1094*724ba675SRob Herring 1095*724ba675SRob Herring hdmi_out: port@1 { 1096*724ba675SRob Herring reg = <1>; 1097*724ba675SRob Herring }; 1098*724ba675SRob Herring }; 1099*724ba675SRob Herring }; 1100*724ba675SRob Herring 1101*724ba675SRob Herring hdmi_phy: hdmi-phy@1ef0000 { 1102*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-hdmi-phy"; 1103*724ba675SRob Herring reg = <0x01ef0000 0x10000>; 1104*724ba675SRob Herring clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 1105*724ba675SRob Herring clock-names = "bus", "mod"; 1106*724ba675SRob Herring resets = <&ccu RST_BUS_HDMI0>; 1107*724ba675SRob Herring reset-names = "phy"; 1108*724ba675SRob Herring #phy-cells = <0>; 1109*724ba675SRob Herring }; 1110*724ba675SRob Herring 1111*724ba675SRob Herring r_intc: interrupt-controller@1f00c00 { 1112*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-r-intc", 1113*724ba675SRob Herring "allwinner,sun6i-a31-r-intc"; 1114*724ba675SRob Herring interrupt-controller; 1115*724ba675SRob Herring #interrupt-cells = <3>; 1116*724ba675SRob Herring reg = <0x01f00c00 0x400>; 1117*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1118*724ba675SRob Herring }; 1119*724ba675SRob Herring 1120*724ba675SRob Herring r_ccu: clock@1f01400 { 1121*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-r-ccu"; 1122*724ba675SRob Herring reg = <0x01f01400 0x400>; 1123*724ba675SRob Herring clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, 1124*724ba675SRob Herring <&ccu CLK_PLL_PERIPH>; 1125*724ba675SRob Herring clock-names = "hosc", "losc", "iosc", "pll-periph"; 1126*724ba675SRob Herring #clock-cells = <1>; 1127*724ba675SRob Herring #reset-cells = <1>; 1128*724ba675SRob Herring }; 1129*724ba675SRob Herring 1130*724ba675SRob Herring r_cpucfg@1f01c00 { 1131*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-r-cpucfg"; 1132*724ba675SRob Herring reg = <0x1f01c00 0x400>; 1133*724ba675SRob Herring }; 1134*724ba675SRob Herring 1135*724ba675SRob Herring r_cir: ir@1f02000 { 1136*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-ir", 1137*724ba675SRob Herring "allwinner,sun6i-a31-ir"; 1138*724ba675SRob Herring clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1139*724ba675SRob Herring clock-names = "apb", "ir"; 1140*724ba675SRob Herring resets = <&r_ccu RST_APB0_IR>; 1141*724ba675SRob Herring interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1142*724ba675SRob Herring reg = <0x01f02000 0x400>; 1143*724ba675SRob Herring pinctrl-names = "default"; 1144*724ba675SRob Herring pinctrl-0 = <&r_cir_pin>; 1145*724ba675SRob Herring status = "disabled"; 1146*724ba675SRob Herring }; 1147*724ba675SRob Herring 1148*724ba675SRob Herring r_lradc: lradc@1f03c00 { 1149*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-r-lradc"; 1150*724ba675SRob Herring reg = <0x01f03c00 0x100>; 1151*724ba675SRob Herring interrupt-parent = <&r_intc>; 1152*724ba675SRob Herring interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1153*724ba675SRob Herring status = "disabled"; 1154*724ba675SRob Herring }; 1155*724ba675SRob Herring 1156*724ba675SRob Herring r_pio: pinctrl@1f02c00 { 1157*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-r-pinctrl"; 1158*724ba675SRob Herring reg = <0x01f02c00 0x400>; 1159*724ba675SRob Herring interrupt-parent = <&r_intc>; 1160*724ba675SRob Herring interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1161*724ba675SRob Herring clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, 1162*724ba675SRob Herring <&osc16Md512>; 1163*724ba675SRob Herring clock-names = "apb", "hosc", "losc"; 1164*724ba675SRob Herring gpio-controller; 1165*724ba675SRob Herring #gpio-cells = <3>; 1166*724ba675SRob Herring interrupt-controller; 1167*724ba675SRob Herring #interrupt-cells = <3>; 1168*724ba675SRob Herring 1169*724ba675SRob Herring r_cir_pin: r-cir-pin { 1170*724ba675SRob Herring pins = "PL12"; 1171*724ba675SRob Herring function = "s_cir_rx"; 1172*724ba675SRob Herring }; 1173*724ba675SRob Herring 1174*724ba675SRob Herring r_rsb_pins: r-rsb-pins { 1175*724ba675SRob Herring pins = "PL0", "PL1"; 1176*724ba675SRob Herring function = "s_rsb"; 1177*724ba675SRob Herring drive-strength = <20>; 1178*724ba675SRob Herring bias-pull-up; 1179*724ba675SRob Herring }; 1180*724ba675SRob Herring }; 1181*724ba675SRob Herring 1182*724ba675SRob Herring r_rsb: rsb@1f03400 { 1183*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-rsb", 1184*724ba675SRob Herring "allwinner,sun8i-a23-rsb"; 1185*724ba675SRob Herring reg = <0x01f03400 0x400>; 1186*724ba675SRob Herring interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1187*724ba675SRob Herring clocks = <&r_ccu CLK_APB0_RSB>; 1188*724ba675SRob Herring clock-frequency = <3000000>; 1189*724ba675SRob Herring resets = <&r_ccu RST_APB0_RSB>; 1190*724ba675SRob Herring pinctrl-names = "default"; 1191*724ba675SRob Herring pinctrl-0 = <&r_rsb_pins>; 1192*724ba675SRob Herring status = "disabled"; 1193*724ba675SRob Herring #address-cells = <1>; 1194*724ba675SRob Herring #size-cells = <0>; 1195*724ba675SRob Herring }; 1196*724ba675SRob Herring 1197*724ba675SRob Herring ths: thermal-sensor@1f04000 { 1198*724ba675SRob Herring compatible = "allwinner,sun8i-a83t-ths"; 1199*724ba675SRob Herring reg = <0x01f04000 0x100>; 1200*724ba675SRob Herring interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1201*724ba675SRob Herring nvmem-cells = <&ths_calibration>; 1202*724ba675SRob Herring nvmem-cell-names = "calibration"; 1203*724ba675SRob Herring #thermal-sensor-cells = <1>; 1204*724ba675SRob Herring }; 1205*724ba675SRob Herring }; 1206*724ba675SRob Herring 1207*724ba675SRob Herring thermal-zones { 1208*724ba675SRob Herring cpu0_thermal: cpu0-thermal { 1209*724ba675SRob Herring polling-delay-passive = <0>; 1210*724ba675SRob Herring polling-delay = <0>; 1211*724ba675SRob Herring thermal-sensors = <&ths 0>; 1212*724ba675SRob Herring 1213*724ba675SRob Herring trips { 1214*724ba675SRob Herring cpu0_hot: cpu-hot { 1215*724ba675SRob Herring temperature = <80000>; 1216*724ba675SRob Herring hysteresis = <2000>; 1217*724ba675SRob Herring type = "passive"; 1218*724ba675SRob Herring }; 1219*724ba675SRob Herring 1220*724ba675SRob Herring cpu0_very_hot: cpu-very-hot { 1221*724ba675SRob Herring temperature = <100000>; 1222*724ba675SRob Herring hysteresis = <0>; 1223*724ba675SRob Herring type = "critical"; 1224*724ba675SRob Herring }; 1225*724ba675SRob Herring }; 1226*724ba675SRob Herring 1227*724ba675SRob Herring cooling-maps { 1228*724ba675SRob Herring cpu-hot-limit { 1229*724ba675SRob Herring trip = <&cpu0_hot>; 1230*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1231*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1232*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1233*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1234*724ba675SRob Herring }; 1235*724ba675SRob Herring }; 1236*724ba675SRob Herring }; 1237*724ba675SRob Herring 1238*724ba675SRob Herring cpu1_thermal: cpu1-thermal { 1239*724ba675SRob Herring polling-delay-passive = <0>; 1240*724ba675SRob Herring polling-delay = <0>; 1241*724ba675SRob Herring thermal-sensors = <&ths 1>; 1242*724ba675SRob Herring 1243*724ba675SRob Herring trips { 1244*724ba675SRob Herring cpu1_hot: cpu-hot { 1245*724ba675SRob Herring temperature = <80000>; 1246*724ba675SRob Herring hysteresis = <2000>; 1247*724ba675SRob Herring type = "passive"; 1248*724ba675SRob Herring }; 1249*724ba675SRob Herring 1250*724ba675SRob Herring cpu1_very_hot: cpu-very-hot { 1251*724ba675SRob Herring temperature = <100000>; 1252*724ba675SRob Herring hysteresis = <0>; 1253*724ba675SRob Herring type = "critical"; 1254*724ba675SRob Herring }; 1255*724ba675SRob Herring }; 1256*724ba675SRob Herring 1257*724ba675SRob Herring cooling-maps { 1258*724ba675SRob Herring cpu-hot-limit { 1259*724ba675SRob Herring trip = <&cpu1_hot>; 1260*724ba675SRob Herring cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1261*724ba675SRob Herring <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1262*724ba675SRob Herring <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1263*724ba675SRob Herring <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1264*724ba675SRob Herring }; 1265*724ba675SRob Herring }; 1266*724ba675SRob Herring }; 1267*724ba675SRob Herring 1268*724ba675SRob Herring gpu_thermal: gpu-thermal { 1269*724ba675SRob Herring polling-delay-passive = <0>; 1270*724ba675SRob Herring polling-delay = <0>; 1271*724ba675SRob Herring thermal-sensors = <&ths 2>; 1272*724ba675SRob Herring }; 1273*724ba675SRob Herring }; 1274*724ba675SRob Herring}; 1275