1*724ba675SRob Herring/* 2*724ba675SRob Herring * Copyright 2014 Chen-Yu Tsai 3*724ba675SRob Herring * 4*724ba675SRob Herring * Chen-Yu Tsai <wens@csie.org> 5*724ba675SRob Herring * 6*724ba675SRob Herring * This file is dual-licensed: you can use it either under the terms 7*724ba675SRob Herring * of the GPL or the X11 license, at your option. Note that this dual 8*724ba675SRob Herring * licensing only applies to this file, and not this project as a 9*724ba675SRob Herring * whole. 10*724ba675SRob Herring * 11*724ba675SRob Herring * a) This file is free software; you can redistribute it and/or 12*724ba675SRob Herring * modify it under the terms of the GNU General Public License as 13*724ba675SRob Herring * published by the Free Software Foundation; either version 2 of the 14*724ba675SRob Herring * License, or (at your option) any later version. 15*724ba675SRob Herring * 16*724ba675SRob Herring * This file is distributed in the hope that it will be useful, 17*724ba675SRob Herring * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*724ba675SRob Herring * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*724ba675SRob Herring * GNU General Public License for more details. 20*724ba675SRob Herring * 21*724ba675SRob Herring * Or, alternatively, 22*724ba675SRob Herring * 23*724ba675SRob Herring * b) Permission is hereby granted, free of charge, to any person 24*724ba675SRob Herring * obtaining a copy of this software and associated documentation 25*724ba675SRob Herring * files (the "Software"), to deal in the Software without 26*724ba675SRob Herring * restriction, including without limitation the rights to use, 27*724ba675SRob Herring * copy, modify, merge, publish, distribute, sublicense, and/or 28*724ba675SRob Herring * sell copies of the Software, and to permit persons to whom the 29*724ba675SRob Herring * Software is furnished to do so, subject to the following 30*724ba675SRob Herring * conditions: 31*724ba675SRob Herring * 32*724ba675SRob Herring * The above copyright notice and this permission notice shall be 33*724ba675SRob Herring * included in all copies or substantial portions of the Software. 34*724ba675SRob Herring * 35*724ba675SRob Herring * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36*724ba675SRob Herring * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37*724ba675SRob Herring * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38*724ba675SRob Herring * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39*724ba675SRob Herring * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40*724ba675SRob Herring * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41*724ba675SRob Herring * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42*724ba675SRob Herring * OTHER DEALINGS IN THE SOFTWARE. 43*724ba675SRob Herring */ 44*724ba675SRob Herring 45*724ba675SRob Herring#include "sun8i-a23-a33.dtsi" 46*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h> 47*724ba675SRob Herring 48*724ba675SRob Herring/ { 49*724ba675SRob Herring cpu0_opp_table: opp-table-cpu { 50*724ba675SRob Herring compatible = "operating-points-v2"; 51*724ba675SRob Herring opp-shared; 52*724ba675SRob Herring 53*724ba675SRob Herring opp-120000000 { 54*724ba675SRob Herring opp-hz = /bits/ 64 <120000000>; 55*724ba675SRob Herring opp-microvolt = <1040000>; 56*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 57*724ba675SRob Herring }; 58*724ba675SRob Herring 59*724ba675SRob Herring opp-240000000 { 60*724ba675SRob Herring opp-hz = /bits/ 64 <240000000>; 61*724ba675SRob Herring opp-microvolt = <1040000>; 62*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 63*724ba675SRob Herring }; 64*724ba675SRob Herring 65*724ba675SRob Herring opp-312000000 { 66*724ba675SRob Herring opp-hz = /bits/ 64 <312000000>; 67*724ba675SRob Herring opp-microvolt = <1040000>; 68*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring opp-408000000 { 72*724ba675SRob Herring opp-hz = /bits/ 64 <408000000>; 73*724ba675SRob Herring opp-microvolt = <1040000>; 74*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 75*724ba675SRob Herring }; 76*724ba675SRob Herring 77*724ba675SRob Herring opp-480000000 { 78*724ba675SRob Herring opp-hz = /bits/ 64 <480000000>; 79*724ba675SRob Herring opp-microvolt = <1040000>; 80*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 81*724ba675SRob Herring }; 82*724ba675SRob Herring 83*724ba675SRob Herring opp-504000000 { 84*724ba675SRob Herring opp-hz = /bits/ 64 <504000000>; 85*724ba675SRob Herring opp-microvolt = <1040000>; 86*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 87*724ba675SRob Herring }; 88*724ba675SRob Herring 89*724ba675SRob Herring opp-600000000 { 90*724ba675SRob Herring opp-hz = /bits/ 64 <600000000>; 91*724ba675SRob Herring opp-microvolt = <1040000>; 92*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 93*724ba675SRob Herring }; 94*724ba675SRob Herring 95*724ba675SRob Herring opp-648000000 { 96*724ba675SRob Herring opp-hz = /bits/ 64 <648000000>; 97*724ba675SRob Herring opp-microvolt = <1040000>; 98*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 99*724ba675SRob Herring }; 100*724ba675SRob Herring 101*724ba675SRob Herring opp-720000000 { 102*724ba675SRob Herring opp-hz = /bits/ 64 <720000000>; 103*724ba675SRob Herring opp-microvolt = <1100000>; 104*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 105*724ba675SRob Herring }; 106*724ba675SRob Herring 107*724ba675SRob Herring opp-816000000 { 108*724ba675SRob Herring opp-hz = /bits/ 64 <816000000>; 109*724ba675SRob Herring opp-microvolt = <1100000>; 110*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 111*724ba675SRob Herring }; 112*724ba675SRob Herring 113*724ba675SRob Herring opp-912000000 { 114*724ba675SRob Herring opp-hz = /bits/ 64 <912000000>; 115*724ba675SRob Herring opp-microvolt = <1200000>; 116*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 117*724ba675SRob Herring }; 118*724ba675SRob Herring 119*724ba675SRob Herring opp-1008000000 { 120*724ba675SRob Herring opp-hz = /bits/ 64 <1008000000>; 121*724ba675SRob Herring opp-microvolt = <1200000>; 122*724ba675SRob Herring clock-latency-ns = <244144>; /* 8 32k periods */ 123*724ba675SRob Herring }; 124*724ba675SRob Herring }; 125*724ba675SRob Herring 126*724ba675SRob Herring cpus { 127*724ba675SRob Herring cpu@0 { 128*724ba675SRob Herring clocks = <&ccu CLK_CPUX>; 129*724ba675SRob Herring clock-names = "cpu"; 130*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 131*724ba675SRob Herring #cooling-cells = <2>; 132*724ba675SRob Herring }; 133*724ba675SRob Herring 134*724ba675SRob Herring cpu1: cpu@1 { 135*724ba675SRob Herring clocks = <&ccu CLK_CPUX>; 136*724ba675SRob Herring clock-names = "cpu"; 137*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 138*724ba675SRob Herring #cooling-cells = <2>; 139*724ba675SRob Herring }; 140*724ba675SRob Herring 141*724ba675SRob Herring cpu2: cpu@2 { 142*724ba675SRob Herring compatible = "arm,cortex-a7"; 143*724ba675SRob Herring device_type = "cpu"; 144*724ba675SRob Herring reg = <2>; 145*724ba675SRob Herring clocks = <&ccu CLK_CPUX>; 146*724ba675SRob Herring clock-names = "cpu"; 147*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 148*724ba675SRob Herring #cooling-cells = <2>; 149*724ba675SRob Herring }; 150*724ba675SRob Herring 151*724ba675SRob Herring cpu3: cpu@3 { 152*724ba675SRob Herring compatible = "arm,cortex-a7"; 153*724ba675SRob Herring device_type = "cpu"; 154*724ba675SRob Herring reg = <3>; 155*724ba675SRob Herring clocks = <&ccu CLK_CPUX>; 156*724ba675SRob Herring clock-names = "cpu"; 157*724ba675SRob Herring operating-points-v2 = <&cpu0_opp_table>; 158*724ba675SRob Herring #cooling-cells = <2>; 159*724ba675SRob Herring }; 160*724ba675SRob Herring }; 161*724ba675SRob Herring 162*724ba675SRob Herring iio-hwmon { 163*724ba675SRob Herring compatible = "iio-hwmon"; 164*724ba675SRob Herring io-channels = <&ths>; 165*724ba675SRob Herring }; 166*724ba675SRob Herring 167*724ba675SRob Herring mali_opp_table: opp-table-gpu { 168*724ba675SRob Herring compatible = "operating-points-v2"; 169*724ba675SRob Herring 170*724ba675SRob Herring opp-144000000 { 171*724ba675SRob Herring opp-hz = /bits/ 64 <144000000>; 172*724ba675SRob Herring }; 173*724ba675SRob Herring 174*724ba675SRob Herring opp-240000000 { 175*724ba675SRob Herring opp-hz = /bits/ 64 <240000000>; 176*724ba675SRob Herring }; 177*724ba675SRob Herring 178*724ba675SRob Herring opp-384000000 { 179*724ba675SRob Herring opp-hz = /bits/ 64 <384000000>; 180*724ba675SRob Herring }; 181*724ba675SRob Herring }; 182*724ba675SRob Herring 183*724ba675SRob Herring sound: sound { 184*724ba675SRob Herring compatible = "simple-audio-card"; 185*724ba675SRob Herring simple-audio-card,name = "sun8i-a33-audio"; 186*724ba675SRob Herring simple-audio-card,format = "i2s"; 187*724ba675SRob Herring simple-audio-card,frame-master = <&link_codec>; 188*724ba675SRob Herring simple-audio-card,bitclock-master = <&link_codec>; 189*724ba675SRob Herring simple-audio-card,mclk-fs = <128>; 190*724ba675SRob Herring simple-audio-card,aux-devs = <&codec_analog>; 191*724ba675SRob Herring simple-audio-card,routing = 192*724ba675SRob Herring "Left DAC", "DACL", 193*724ba675SRob Herring "Right DAC", "DACR"; 194*724ba675SRob Herring status = "disabled"; 195*724ba675SRob Herring 196*724ba675SRob Herring simple-audio-card,cpu { 197*724ba675SRob Herring sound-dai = <&dai>; 198*724ba675SRob Herring }; 199*724ba675SRob Herring 200*724ba675SRob Herring link_codec: simple-audio-card,codec { 201*724ba675SRob Herring sound-dai = <&codec 0>; 202*724ba675SRob Herring }; 203*724ba675SRob Herring }; 204*724ba675SRob Herring 205*724ba675SRob Herring soc { 206*724ba675SRob Herring video-codec@1c0e000 { 207*724ba675SRob Herring compatible = "allwinner,sun8i-a33-video-engine"; 208*724ba675SRob Herring reg = <0x01c0e000 0x1000>; 209*724ba675SRob Herring clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 210*724ba675SRob Herring <&ccu CLK_DRAM_VE>; 211*724ba675SRob Herring clock-names = "ahb", "mod", "ram"; 212*724ba675SRob Herring resets = <&ccu RST_BUS_VE>; 213*724ba675SRob Herring interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 214*724ba675SRob Herring allwinner,sram = <&ve_sram 1>; 215*724ba675SRob Herring }; 216*724ba675SRob Herring 217*724ba675SRob Herring crypto: crypto-engine@1c15000 { 218*724ba675SRob Herring compatible = "allwinner,sun8i-a33-crypto"; 219*724ba675SRob Herring reg = <0x01c15000 0x1000>; 220*724ba675SRob Herring interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 221*724ba675SRob Herring clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; 222*724ba675SRob Herring clock-names = "ahb", "mod"; 223*724ba675SRob Herring resets = <&ccu RST_BUS_SS>; 224*724ba675SRob Herring reset-names = "ahb"; 225*724ba675SRob Herring }; 226*724ba675SRob Herring 227*724ba675SRob Herring dai: dai@1c22c00 { 228*724ba675SRob Herring #sound-dai-cells = <0>; 229*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2s"; 230*724ba675SRob Herring reg = <0x01c22c00 0x200>; 231*724ba675SRob Herring interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 232*724ba675SRob Herring clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 233*724ba675SRob Herring clock-names = "apb", "mod"; 234*724ba675SRob Herring resets = <&ccu RST_BUS_CODEC>; 235*724ba675SRob Herring dmas = <&dma 15>, <&dma 15>; 236*724ba675SRob Herring dma-names = "rx", "tx"; 237*724ba675SRob Herring status = "disabled"; 238*724ba675SRob Herring }; 239*724ba675SRob Herring 240*724ba675SRob Herring codec: codec@1c22e00 { 241*724ba675SRob Herring #sound-dai-cells = <1>; 242*724ba675SRob Herring compatible = "allwinner,sun8i-a33-codec"; 243*724ba675SRob Herring reg = <0x01c22e00 0x400>; 244*724ba675SRob Herring interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 245*724ba675SRob Herring clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 246*724ba675SRob Herring clock-names = "bus", "mod"; 247*724ba675SRob Herring status = "disabled"; 248*724ba675SRob Herring }; 249*724ba675SRob Herring 250*724ba675SRob Herring ths: ths@1c25000 { 251*724ba675SRob Herring compatible = "allwinner,sun8i-a33-ths"; 252*724ba675SRob Herring reg = <0x01c25000 0x100>; 253*724ba675SRob Herring #thermal-sensor-cells = <0>; 254*724ba675SRob Herring #io-channel-cells = <0>; 255*724ba675SRob Herring }; 256*724ba675SRob Herring 257*724ba675SRob Herring dsi: dsi@1ca0000 { 258*724ba675SRob Herring compatible = "allwinner,sun6i-a31-mipi-dsi"; 259*724ba675SRob Herring reg = <0x01ca0000 0x1000>; 260*724ba675SRob Herring interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 261*724ba675SRob Herring clocks = <&ccu CLK_BUS_MIPI_DSI>, 262*724ba675SRob Herring <&ccu CLK_DSI_SCLK>; 263*724ba675SRob Herring clock-names = "bus", "mod"; 264*724ba675SRob Herring resets = <&ccu RST_BUS_MIPI_DSI>; 265*724ba675SRob Herring phys = <&dphy>; 266*724ba675SRob Herring phy-names = "dphy"; 267*724ba675SRob Herring status = "disabled"; 268*724ba675SRob Herring #address-cells = <1>; 269*724ba675SRob Herring #size-cells = <0>; 270*724ba675SRob Herring 271*724ba675SRob Herring port { 272*724ba675SRob Herring dsi_in_tcon0: endpoint { 273*724ba675SRob Herring remote-endpoint = <&tcon0_out_dsi>; 274*724ba675SRob Herring }; 275*724ba675SRob Herring }; 276*724ba675SRob Herring }; 277*724ba675SRob Herring 278*724ba675SRob Herring dphy: d-phy@1ca1000 { 279*724ba675SRob Herring compatible = "allwinner,sun6i-a31-mipi-dphy"; 280*724ba675SRob Herring reg = <0x01ca1000 0x1000>; 281*724ba675SRob Herring interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 282*724ba675SRob Herring clocks = <&ccu CLK_BUS_MIPI_DSI>, 283*724ba675SRob Herring <&ccu CLK_DSI_DPHY>; 284*724ba675SRob Herring clock-names = "bus", "mod"; 285*724ba675SRob Herring resets = <&ccu RST_BUS_MIPI_DSI>; 286*724ba675SRob Herring status = "disabled"; 287*724ba675SRob Herring #phy-cells = <0>; 288*724ba675SRob Herring }; 289*724ba675SRob Herring }; 290*724ba675SRob Herring 291*724ba675SRob Herring thermal-zones { 292*724ba675SRob Herring cpu-thermal { 293*724ba675SRob Herring /* milliseconds */ 294*724ba675SRob Herring polling-delay-passive = <250>; 295*724ba675SRob Herring polling-delay = <1000>; 296*724ba675SRob Herring thermal-sensors = <&ths>; 297*724ba675SRob Herring 298*724ba675SRob Herring cooling-maps { 299*724ba675SRob Herring map0 { 300*724ba675SRob Herring trip = <&cpu_alert0>; 301*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 302*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 303*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 304*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 305*724ba675SRob Herring }; 306*724ba675SRob Herring map1 { 307*724ba675SRob Herring trip = <&cpu_alert1>; 308*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 309*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 310*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 311*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 312*724ba675SRob Herring }; 313*724ba675SRob Herring 314*724ba675SRob Herring map2 { 315*724ba675SRob Herring trip = <&gpu_alert0>; 316*724ba675SRob Herring cooling-device = <&mali 1 THERMAL_NO_LIMIT>; 317*724ba675SRob Herring }; 318*724ba675SRob Herring 319*724ba675SRob Herring map3 { 320*724ba675SRob Herring trip = <&gpu_alert1>; 321*724ba675SRob Herring cooling-device = <&mali 2 THERMAL_NO_LIMIT>; 322*724ba675SRob Herring }; 323*724ba675SRob Herring }; 324*724ba675SRob Herring 325*724ba675SRob Herring trips { 326*724ba675SRob Herring cpu_alert0: cpu_alert0 { 327*724ba675SRob Herring /* milliCelsius */ 328*724ba675SRob Herring temperature = <75000>; 329*724ba675SRob Herring hysteresis = <2000>; 330*724ba675SRob Herring type = "passive"; 331*724ba675SRob Herring }; 332*724ba675SRob Herring 333*724ba675SRob Herring gpu_alert0: gpu_alert0 { 334*724ba675SRob Herring /* milliCelsius */ 335*724ba675SRob Herring temperature = <85000>; 336*724ba675SRob Herring hysteresis = <2000>; 337*724ba675SRob Herring type = "passive"; 338*724ba675SRob Herring }; 339*724ba675SRob Herring 340*724ba675SRob Herring cpu_alert1: cpu_alert1 { 341*724ba675SRob Herring /* milliCelsius */ 342*724ba675SRob Herring temperature = <90000>; 343*724ba675SRob Herring hysteresis = <2000>; 344*724ba675SRob Herring type = "hot"; 345*724ba675SRob Herring }; 346*724ba675SRob Herring 347*724ba675SRob Herring gpu_alert1: gpu_alert1 { 348*724ba675SRob Herring /* milliCelsius */ 349*724ba675SRob Herring temperature = <95000>; 350*724ba675SRob Herring hysteresis = <2000>; 351*724ba675SRob Herring type = "hot"; 352*724ba675SRob Herring }; 353*724ba675SRob Herring 354*724ba675SRob Herring cpu_crit: cpu_crit { 355*724ba675SRob Herring /* milliCelsius */ 356*724ba675SRob Herring temperature = <110000>; 357*724ba675SRob Herring hysteresis = <2000>; 358*724ba675SRob Herring type = "critical"; 359*724ba675SRob Herring }; 360*724ba675SRob Herring }; 361*724ba675SRob Herring }; 362*724ba675SRob Herring }; 363*724ba675SRob Herring}; 364*724ba675SRob Herring 365*724ba675SRob Herring&be0 { 366*724ba675SRob Herring compatible = "allwinner,sun8i-a33-display-backend"; 367*724ba675SRob Herring /* A33 has an extra "SAT" module packed inside the display backend */ 368*724ba675SRob Herring reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; 369*724ba675SRob Herring reg-names = "be", "sat"; 370*724ba675SRob Herring clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, 371*724ba675SRob Herring <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; 372*724ba675SRob Herring clock-names = "ahb", "mod", 373*724ba675SRob Herring "ram", "sat"; 374*724ba675SRob Herring resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; 375*724ba675SRob Herring reset-names = "be", "sat"; 376*724ba675SRob Herring}; 377*724ba675SRob Herring 378*724ba675SRob Herring&ccu { 379*724ba675SRob Herring compatible = "allwinner,sun8i-a33-ccu"; 380*724ba675SRob Herring}; 381*724ba675SRob Herring 382*724ba675SRob Herring&de { 383*724ba675SRob Herring compatible = "allwinner,sun8i-a33-display-engine"; 384*724ba675SRob Herring}; 385*724ba675SRob Herring 386*724ba675SRob Herring&drc0 { 387*724ba675SRob Herring compatible = "allwinner,sun8i-a33-drc"; 388*724ba675SRob Herring}; 389*724ba675SRob Herring 390*724ba675SRob Herring&fe0 { 391*724ba675SRob Herring compatible = "allwinner,sun8i-a33-display-frontend"; 392*724ba675SRob Herring}; 393*724ba675SRob Herring 394*724ba675SRob Herring&mali { 395*724ba675SRob Herring operating-points-v2 = <&mali_opp_table>; 396*724ba675SRob Herring}; 397*724ba675SRob Herring 398*724ba675SRob Herring&pio { 399*724ba675SRob Herring compatible = "allwinner,sun8i-a33-pinctrl"; 400*724ba675SRob Herring interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 401*724ba675SRob Herring <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 402*724ba675SRob Herring 403*724ba675SRob Herring uart0_pb_pins: uart0-pb-pins { 404*724ba675SRob Herring pins = "PB0", "PB1"; 405*724ba675SRob Herring function = "uart0"; 406*724ba675SRob Herring }; 407*724ba675SRob Herring 408*724ba675SRob Herring}; 409*724ba675SRob Herring 410*724ba675SRob Herring&tcon0 { 411*724ba675SRob Herring compatible = "allwinner,sun8i-a33-tcon"; 412*724ba675SRob Herring}; 413*724ba675SRob Herring 414*724ba675SRob Herring&tcon0_out { 415*724ba675SRob Herring #address-cells = <1>; 416*724ba675SRob Herring #size-cells = <0>; 417*724ba675SRob Herring 418*724ba675SRob Herring tcon0_out_dsi: endpoint@1 { 419*724ba675SRob Herring reg = <1>; 420*724ba675SRob Herring remote-endpoint = <&dsi_in_tcon0>; 421*724ba675SRob Herring }; 422*724ba675SRob Herring}; 423*724ba675SRob Herring 424*724ba675SRob Herring&usb_otg { 425*724ba675SRob Herring compatible = "allwinner,sun8i-a33-musb"; 426*724ba675SRob Herring}; 427*724ba675SRob Herring 428*724ba675SRob Herring&usbphy { 429*724ba675SRob Herring compatible = "allwinner,sun8i-a33-usb-phy"; 430*724ba675SRob Herring reg = <0x01c19400 0x14>, <0x01c1a800 0x4>; 431*724ba675SRob Herring reg-names = "phy_ctrl", "pmu1"; 432*724ba675SRob Herring}; 433