1*724ba675SRob Herring/* 2*724ba675SRob Herring * Copyright 2013 Maxime Ripard 3*724ba675SRob Herring * 4*724ba675SRob Herring * Maxime Ripard <maxime.ripard@free-electrons.com> 5*724ba675SRob Herring * 6*724ba675SRob Herring * This file is dual-licensed: you can use it either under the terms 7*724ba675SRob Herring * of the GPL or the X11 license, at your option. Note that this dual 8*724ba675SRob Herring * licensing only applies to this file, and not this project as a 9*724ba675SRob Herring * whole. 10*724ba675SRob Herring * 11*724ba675SRob Herring * a) This file is free software; you can redistribute it and/or 12*724ba675SRob Herring * modify it under the terms of the GNU General Public License as 13*724ba675SRob Herring * published by the Free Software Foundation; either version 2 of the 14*724ba675SRob Herring * License, or (at your option) any later version. 15*724ba675SRob Herring * 16*724ba675SRob Herring * This file is distributed in the hope that it will be useful, 17*724ba675SRob Herring * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*724ba675SRob Herring * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*724ba675SRob Herring * GNU General Public License for more details. 20*724ba675SRob Herring * 21*724ba675SRob Herring * Or, alternatively, 22*724ba675SRob Herring * 23*724ba675SRob Herring * b) Permission is hereby granted, free of charge, to any person 24*724ba675SRob Herring * obtaining a copy of this software and associated documentation 25*724ba675SRob Herring * files (the "Software"), to deal in the Software without 26*724ba675SRob Herring * restriction, including without limitation the rights to use, 27*724ba675SRob Herring * copy, modify, merge, publish, distribute, sublicense, and/or 28*724ba675SRob Herring * sell copies of the Software, and to permit persons to whom the 29*724ba675SRob Herring * Software is furnished to do so, subject to the following 30*724ba675SRob Herring * conditions: 31*724ba675SRob Herring * 32*724ba675SRob Herring * The above copyright notice and this permission notice shall be 33*724ba675SRob Herring * included in all copies or substantial portions of the Software. 34*724ba675SRob Herring * 35*724ba675SRob Herring * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36*724ba675SRob Herring * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37*724ba675SRob Herring * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38*724ba675SRob Herring * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39*724ba675SRob Herring * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40*724ba675SRob Herring * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41*724ba675SRob Herring * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42*724ba675SRob Herring * OTHER DEALINGS IN THE SOFTWARE. 43*724ba675SRob Herring */ 44*724ba675SRob Herring 45*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 46*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h> 47*724ba675SRob Herring 48*724ba675SRob Herring#include <dt-bindings/clock/sun6i-a31-ccu.h> 49*724ba675SRob Herring#include <dt-bindings/clock/sun6i-rtc.h> 50*724ba675SRob Herring#include <dt-bindings/reset/sun6i-a31-ccu.h> 51*724ba675SRob Herring 52*724ba675SRob Herring/ { 53*724ba675SRob Herring interrupt-parent = <&gic>; 54*724ba675SRob Herring #address-cells = <1>; 55*724ba675SRob Herring #size-cells = <1>; 56*724ba675SRob Herring 57*724ba675SRob Herring aliases { 58*724ba675SRob Herring ethernet0 = &gmac; 59*724ba675SRob Herring }; 60*724ba675SRob Herring 61*724ba675SRob Herring chosen { 62*724ba675SRob Herring #address-cells = <1>; 63*724ba675SRob Herring #size-cells = <1>; 64*724ba675SRob Herring ranges; 65*724ba675SRob Herring 66*724ba675SRob Herring simplefb_hdmi: framebuffer-lcd0-hdmi { 67*724ba675SRob Herring compatible = "allwinner,simple-framebuffer", 68*724ba675SRob Herring "simple-framebuffer"; 69*724ba675SRob Herring allwinner,pipeline = "de_be0-lcd0-hdmi"; 70*724ba675SRob Herring clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, 71*724ba675SRob Herring <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, 72*724ba675SRob Herring <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, 73*724ba675SRob Herring <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; 74*724ba675SRob Herring status = "disabled"; 75*724ba675SRob Herring }; 76*724ba675SRob Herring 77*724ba675SRob Herring simplefb_lcd: framebuffer-lcd0 { 78*724ba675SRob Herring compatible = "allwinner,simple-framebuffer", 79*724ba675SRob Herring "simple-framebuffer"; 80*724ba675SRob Herring allwinner,pipeline = "de_be0-lcd0"; 81*724ba675SRob Herring clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, 82*724ba675SRob Herring <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, 83*724ba675SRob Herring <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; 84*724ba675SRob Herring status = "disabled"; 85*724ba675SRob Herring }; 86*724ba675SRob Herring }; 87*724ba675SRob Herring 88*724ba675SRob Herring timer { 89*724ba675SRob Herring compatible = "arm,armv7-timer"; 90*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 91*724ba675SRob Herring <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 92*724ba675SRob Herring <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 93*724ba675SRob Herring <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 94*724ba675SRob Herring clock-frequency = <24000000>; 95*724ba675SRob Herring arm,cpu-registers-not-fw-configured; 96*724ba675SRob Herring }; 97*724ba675SRob Herring 98*724ba675SRob Herring cpus { 99*724ba675SRob Herring enable-method = "allwinner,sun6i-a31"; 100*724ba675SRob Herring #address-cells = <1>; 101*724ba675SRob Herring #size-cells = <0>; 102*724ba675SRob Herring 103*724ba675SRob Herring cpu0: cpu@0 { 104*724ba675SRob Herring compatible = "arm,cortex-a7"; 105*724ba675SRob Herring device_type = "cpu"; 106*724ba675SRob Herring reg = <0>; 107*724ba675SRob Herring clocks = <&ccu CLK_CPU>; 108*724ba675SRob Herring clock-latency = <244144>; /* 8 32k periods */ 109*724ba675SRob Herring operating-points = 110*724ba675SRob Herring /* kHz uV */ 111*724ba675SRob Herring <1008000 1200000>, 112*724ba675SRob Herring <864000 1200000>, 113*724ba675SRob Herring <720000 1100000>, 114*724ba675SRob Herring <480000 1000000>; 115*724ba675SRob Herring #cooling-cells = <2>; 116*724ba675SRob Herring }; 117*724ba675SRob Herring 118*724ba675SRob Herring cpu1: cpu@1 { 119*724ba675SRob Herring compatible = "arm,cortex-a7"; 120*724ba675SRob Herring device_type = "cpu"; 121*724ba675SRob Herring reg = <1>; 122*724ba675SRob Herring clocks = <&ccu CLK_CPU>; 123*724ba675SRob Herring clock-latency = <244144>; /* 8 32k periods */ 124*724ba675SRob Herring operating-points = 125*724ba675SRob Herring /* kHz uV */ 126*724ba675SRob Herring <1008000 1200000>, 127*724ba675SRob Herring <864000 1200000>, 128*724ba675SRob Herring <720000 1100000>, 129*724ba675SRob Herring <480000 1000000>; 130*724ba675SRob Herring #cooling-cells = <2>; 131*724ba675SRob Herring }; 132*724ba675SRob Herring 133*724ba675SRob Herring cpu2: cpu@2 { 134*724ba675SRob Herring compatible = "arm,cortex-a7"; 135*724ba675SRob Herring device_type = "cpu"; 136*724ba675SRob Herring reg = <2>; 137*724ba675SRob Herring clocks = <&ccu CLK_CPU>; 138*724ba675SRob Herring clock-latency = <244144>; /* 8 32k periods */ 139*724ba675SRob Herring operating-points = 140*724ba675SRob Herring /* kHz uV */ 141*724ba675SRob Herring <1008000 1200000>, 142*724ba675SRob Herring <864000 1200000>, 143*724ba675SRob Herring <720000 1100000>, 144*724ba675SRob Herring <480000 1000000>; 145*724ba675SRob Herring #cooling-cells = <2>; 146*724ba675SRob Herring }; 147*724ba675SRob Herring 148*724ba675SRob Herring cpu3: cpu@3 { 149*724ba675SRob Herring compatible = "arm,cortex-a7"; 150*724ba675SRob Herring device_type = "cpu"; 151*724ba675SRob Herring reg = <3>; 152*724ba675SRob Herring clocks = <&ccu CLK_CPU>; 153*724ba675SRob Herring clock-latency = <244144>; /* 8 32k periods */ 154*724ba675SRob Herring operating-points = 155*724ba675SRob Herring /* kHz uV */ 156*724ba675SRob Herring <1008000 1200000>, 157*724ba675SRob Herring <864000 1200000>, 158*724ba675SRob Herring <720000 1100000>, 159*724ba675SRob Herring <480000 1000000>; 160*724ba675SRob Herring #cooling-cells = <2>; 161*724ba675SRob Herring }; 162*724ba675SRob Herring }; 163*724ba675SRob Herring 164*724ba675SRob Herring thermal-zones { 165*724ba675SRob Herring cpu-thermal { 166*724ba675SRob Herring /* milliseconds */ 167*724ba675SRob Herring polling-delay-passive = <250>; 168*724ba675SRob Herring polling-delay = <1000>; 169*724ba675SRob Herring thermal-sensors = <&rtp>; 170*724ba675SRob Herring 171*724ba675SRob Herring cooling-maps { 172*724ba675SRob Herring map0 { 173*724ba675SRob Herring trip = <&cpu_alert0>; 174*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 175*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 176*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 177*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 178*724ba675SRob Herring }; 179*724ba675SRob Herring }; 180*724ba675SRob Herring 181*724ba675SRob Herring trips { 182*724ba675SRob Herring cpu_alert0: cpu_alert0 { 183*724ba675SRob Herring /* milliCelsius */ 184*724ba675SRob Herring temperature = <70000>; 185*724ba675SRob Herring hysteresis = <2000>; 186*724ba675SRob Herring type = "passive"; 187*724ba675SRob Herring }; 188*724ba675SRob Herring 189*724ba675SRob Herring cpu_crit: cpu_crit { 190*724ba675SRob Herring /* milliCelsius */ 191*724ba675SRob Herring temperature = <100000>; 192*724ba675SRob Herring hysteresis = <2000>; 193*724ba675SRob Herring type = "critical"; 194*724ba675SRob Herring }; 195*724ba675SRob Herring }; 196*724ba675SRob Herring }; 197*724ba675SRob Herring }; 198*724ba675SRob Herring 199*724ba675SRob Herring pmu { 200*724ba675SRob Herring compatible = "arm,cortex-a7-pmu"; 201*724ba675SRob Herring interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 202*724ba675SRob Herring <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 203*724ba675SRob Herring <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 204*724ba675SRob Herring <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 205*724ba675SRob Herring }; 206*724ba675SRob Herring 207*724ba675SRob Herring clocks { 208*724ba675SRob Herring #address-cells = <1>; 209*724ba675SRob Herring #size-cells = <1>; 210*724ba675SRob Herring ranges; 211*724ba675SRob Herring 212*724ba675SRob Herring osc24M: clk-24M { 213*724ba675SRob Herring #clock-cells = <0>; 214*724ba675SRob Herring compatible = "fixed-clock"; 215*724ba675SRob Herring clock-frequency = <24000000>; 216*724ba675SRob Herring clock-accuracy = <50000>; 217*724ba675SRob Herring clock-output-names = "osc24M"; 218*724ba675SRob Herring }; 219*724ba675SRob Herring 220*724ba675SRob Herring osc32k: clk-32k { 221*724ba675SRob Herring #clock-cells = <0>; 222*724ba675SRob Herring compatible = "fixed-clock"; 223*724ba675SRob Herring clock-frequency = <32768>; 224*724ba675SRob Herring clock-accuracy = <50000>; 225*724ba675SRob Herring clock-output-names = "ext_osc32k"; 226*724ba675SRob Herring }; 227*724ba675SRob Herring 228*724ba675SRob Herring /* 229*724ba675SRob Herring * The following two are dummy clocks, placeholders 230*724ba675SRob Herring * used in the gmac_tx clock. The gmac driver will 231*724ba675SRob Herring * choose one parent depending on the PHY interface 232*724ba675SRob Herring * mode, using clk_set_rate auto-reparenting. 233*724ba675SRob Herring * 234*724ba675SRob Herring * The actual TX clock rate is not controlled by the 235*724ba675SRob Herring * gmac_tx clock. 236*724ba675SRob Herring */ 237*724ba675SRob Herring mii_phy_tx_clk: clk-mii-phy-tx { 238*724ba675SRob Herring #clock-cells = <0>; 239*724ba675SRob Herring compatible = "fixed-clock"; 240*724ba675SRob Herring clock-frequency = <25000000>; 241*724ba675SRob Herring clock-output-names = "mii_phy_tx"; 242*724ba675SRob Herring }; 243*724ba675SRob Herring 244*724ba675SRob Herring gmac_int_tx_clk: clk-gmac-int-tx { 245*724ba675SRob Herring #clock-cells = <0>; 246*724ba675SRob Herring compatible = "fixed-clock"; 247*724ba675SRob Herring clock-frequency = <125000000>; 248*724ba675SRob Herring clock-output-names = "gmac_int_tx"; 249*724ba675SRob Herring }; 250*724ba675SRob Herring 251*724ba675SRob Herring gmac_tx_clk: clk@1c200d0 { 252*724ba675SRob Herring #clock-cells = <0>; 253*724ba675SRob Herring compatible = "allwinner,sun7i-a20-gmac-clk"; 254*724ba675SRob Herring reg = <0x01c200d0 0x4>; 255*724ba675SRob Herring clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 256*724ba675SRob Herring clock-output-names = "gmac_tx"; 257*724ba675SRob Herring }; 258*724ba675SRob Herring }; 259*724ba675SRob Herring 260*724ba675SRob Herring de: display-engine { 261*724ba675SRob Herring compatible = "allwinner,sun6i-a31-display-engine"; 262*724ba675SRob Herring allwinner,pipelines = <&fe0>, <&fe1>; 263*724ba675SRob Herring status = "disabled"; 264*724ba675SRob Herring }; 265*724ba675SRob Herring 266*724ba675SRob Herring soc { 267*724ba675SRob Herring compatible = "simple-bus"; 268*724ba675SRob Herring #address-cells = <1>; 269*724ba675SRob Herring #size-cells = <1>; 270*724ba675SRob Herring ranges; 271*724ba675SRob Herring 272*724ba675SRob Herring dma: dma-controller@1c02000 { 273*724ba675SRob Herring compatible = "allwinner,sun6i-a31-dma"; 274*724ba675SRob Herring reg = <0x01c02000 0x1000>; 275*724ba675SRob Herring interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 276*724ba675SRob Herring clocks = <&ccu CLK_AHB1_DMA>; 277*724ba675SRob Herring resets = <&ccu RST_AHB1_DMA>; 278*724ba675SRob Herring #dma-cells = <1>; 279*724ba675SRob Herring }; 280*724ba675SRob Herring 281*724ba675SRob Herring tcon0: lcd-controller@1c0c000 { 282*724ba675SRob Herring compatible = "allwinner,sun6i-a31-tcon"; 283*724ba675SRob Herring reg = <0x01c0c000 0x1000>; 284*724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 285*724ba675SRob Herring dmas = <&dma 11>; 286*724ba675SRob Herring resets = <&ccu RST_AHB1_LCD0>, 287*724ba675SRob Herring <&ccu RST_AHB1_LVDS>; 288*724ba675SRob Herring reset-names = "lcd", 289*724ba675SRob Herring "lvds"; 290*724ba675SRob Herring clocks = <&ccu CLK_AHB1_LCD0>, 291*724ba675SRob Herring <&ccu CLK_LCD0_CH0>, 292*724ba675SRob Herring <&ccu CLK_LCD0_CH1>, 293*724ba675SRob Herring <&ccu 15>; 294*724ba675SRob Herring clock-names = "ahb", 295*724ba675SRob Herring "tcon-ch0", 296*724ba675SRob Herring "tcon-ch1", 297*724ba675SRob Herring "lvds-alt"; 298*724ba675SRob Herring clock-output-names = "tcon0-pixel-clock"; 299*724ba675SRob Herring #clock-cells = <0>; 300*724ba675SRob Herring 301*724ba675SRob Herring ports { 302*724ba675SRob Herring #address-cells = <1>; 303*724ba675SRob Herring #size-cells = <0>; 304*724ba675SRob Herring 305*724ba675SRob Herring tcon0_in: port@0 { 306*724ba675SRob Herring #address-cells = <1>; 307*724ba675SRob Herring #size-cells = <0>; 308*724ba675SRob Herring reg = <0>; 309*724ba675SRob Herring 310*724ba675SRob Herring tcon0_in_drc0: endpoint@0 { 311*724ba675SRob Herring reg = <0>; 312*724ba675SRob Herring remote-endpoint = <&drc0_out_tcon0>; 313*724ba675SRob Herring }; 314*724ba675SRob Herring 315*724ba675SRob Herring tcon0_in_drc1: endpoint@1 { 316*724ba675SRob Herring reg = <1>; 317*724ba675SRob Herring remote-endpoint = <&drc1_out_tcon0>; 318*724ba675SRob Herring }; 319*724ba675SRob Herring }; 320*724ba675SRob Herring 321*724ba675SRob Herring tcon0_out: port@1 { 322*724ba675SRob Herring #address-cells = <1>; 323*724ba675SRob Herring #size-cells = <0>; 324*724ba675SRob Herring reg = <1>; 325*724ba675SRob Herring 326*724ba675SRob Herring tcon0_out_hdmi: endpoint@1 { 327*724ba675SRob Herring reg = <1>; 328*724ba675SRob Herring remote-endpoint = <&hdmi_in_tcon0>; 329*724ba675SRob Herring allwinner,tcon-channel = <1>; 330*724ba675SRob Herring }; 331*724ba675SRob Herring }; 332*724ba675SRob Herring }; 333*724ba675SRob Herring }; 334*724ba675SRob Herring 335*724ba675SRob Herring tcon1: lcd-controller@1c0d000 { 336*724ba675SRob Herring compatible = "allwinner,sun6i-a31-tcon"; 337*724ba675SRob Herring reg = <0x01c0d000 0x1000>; 338*724ba675SRob Herring interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 339*724ba675SRob Herring dmas = <&dma 12>; 340*724ba675SRob Herring resets = <&ccu RST_AHB1_LCD1>, 341*724ba675SRob Herring <&ccu RST_AHB1_LVDS>; 342*724ba675SRob Herring reset-names = "lcd", "lvds"; 343*724ba675SRob Herring clocks = <&ccu CLK_AHB1_LCD1>, 344*724ba675SRob Herring <&ccu CLK_LCD1_CH0>, 345*724ba675SRob Herring <&ccu CLK_LCD1_CH1>, 346*724ba675SRob Herring <&ccu 15>; 347*724ba675SRob Herring clock-names = "ahb", 348*724ba675SRob Herring "tcon-ch0", 349*724ba675SRob Herring "tcon-ch1", 350*724ba675SRob Herring "lvds-alt"; 351*724ba675SRob Herring clock-output-names = "tcon1-pixel-clock"; 352*724ba675SRob Herring #clock-cells = <0>; 353*724ba675SRob Herring 354*724ba675SRob Herring ports { 355*724ba675SRob Herring #address-cells = <1>; 356*724ba675SRob Herring #size-cells = <0>; 357*724ba675SRob Herring 358*724ba675SRob Herring tcon1_in: port@0 { 359*724ba675SRob Herring #address-cells = <1>; 360*724ba675SRob Herring #size-cells = <0>; 361*724ba675SRob Herring reg = <0>; 362*724ba675SRob Herring 363*724ba675SRob Herring tcon1_in_drc0: endpoint@0 { 364*724ba675SRob Herring reg = <0>; 365*724ba675SRob Herring remote-endpoint = <&drc0_out_tcon1>; 366*724ba675SRob Herring }; 367*724ba675SRob Herring 368*724ba675SRob Herring tcon1_in_drc1: endpoint@1 { 369*724ba675SRob Herring reg = <1>; 370*724ba675SRob Herring remote-endpoint = <&drc1_out_tcon1>; 371*724ba675SRob Herring }; 372*724ba675SRob Herring }; 373*724ba675SRob Herring 374*724ba675SRob Herring tcon1_out: port@1 { 375*724ba675SRob Herring #address-cells = <1>; 376*724ba675SRob Herring #size-cells = <0>; 377*724ba675SRob Herring reg = <1>; 378*724ba675SRob Herring 379*724ba675SRob Herring tcon1_out_hdmi: endpoint@1 { 380*724ba675SRob Herring reg = <1>; 381*724ba675SRob Herring remote-endpoint = <&hdmi_in_tcon1>; 382*724ba675SRob Herring allwinner,tcon-channel = <1>; 383*724ba675SRob Herring }; 384*724ba675SRob Herring }; 385*724ba675SRob Herring }; 386*724ba675SRob Herring }; 387*724ba675SRob Herring 388*724ba675SRob Herring mmc0: mmc@1c0f000 { 389*724ba675SRob Herring compatible = "allwinner,sun7i-a20-mmc"; 390*724ba675SRob Herring reg = <0x01c0f000 0x1000>; 391*724ba675SRob Herring clocks = <&ccu CLK_AHB1_MMC0>, 392*724ba675SRob Herring <&ccu CLK_MMC0>, 393*724ba675SRob Herring <&ccu CLK_MMC0_OUTPUT>, 394*724ba675SRob Herring <&ccu CLK_MMC0_SAMPLE>; 395*724ba675SRob Herring clock-names = "ahb", 396*724ba675SRob Herring "mmc", 397*724ba675SRob Herring "output", 398*724ba675SRob Herring "sample"; 399*724ba675SRob Herring resets = <&ccu RST_AHB1_MMC0>; 400*724ba675SRob Herring reset-names = "ahb"; 401*724ba675SRob Herring interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 402*724ba675SRob Herring pinctrl-names = "default"; 403*724ba675SRob Herring pinctrl-0 = <&mmc0_pins>; 404*724ba675SRob Herring status = "disabled"; 405*724ba675SRob Herring #address-cells = <1>; 406*724ba675SRob Herring #size-cells = <0>; 407*724ba675SRob Herring }; 408*724ba675SRob Herring 409*724ba675SRob Herring mmc1: mmc@1c10000 { 410*724ba675SRob Herring compatible = "allwinner,sun7i-a20-mmc"; 411*724ba675SRob Herring reg = <0x01c10000 0x1000>; 412*724ba675SRob Herring clocks = <&ccu CLK_AHB1_MMC1>, 413*724ba675SRob Herring <&ccu CLK_MMC1>, 414*724ba675SRob Herring <&ccu CLK_MMC1_OUTPUT>, 415*724ba675SRob Herring <&ccu CLK_MMC1_SAMPLE>; 416*724ba675SRob Herring clock-names = "ahb", 417*724ba675SRob Herring "mmc", 418*724ba675SRob Herring "output", 419*724ba675SRob Herring "sample"; 420*724ba675SRob Herring resets = <&ccu RST_AHB1_MMC1>; 421*724ba675SRob Herring reset-names = "ahb"; 422*724ba675SRob Herring interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 423*724ba675SRob Herring pinctrl-names = "default"; 424*724ba675SRob Herring pinctrl-0 = <&mmc1_pins>; 425*724ba675SRob Herring status = "disabled"; 426*724ba675SRob Herring #address-cells = <1>; 427*724ba675SRob Herring #size-cells = <0>; 428*724ba675SRob Herring }; 429*724ba675SRob Herring 430*724ba675SRob Herring mmc2: mmc@1c11000 { 431*724ba675SRob Herring compatible = "allwinner,sun7i-a20-mmc"; 432*724ba675SRob Herring reg = <0x01c11000 0x1000>; 433*724ba675SRob Herring clocks = <&ccu CLK_AHB1_MMC2>, 434*724ba675SRob Herring <&ccu CLK_MMC2>, 435*724ba675SRob Herring <&ccu CLK_MMC2_OUTPUT>, 436*724ba675SRob Herring <&ccu CLK_MMC2_SAMPLE>; 437*724ba675SRob Herring clock-names = "ahb", 438*724ba675SRob Herring "mmc", 439*724ba675SRob Herring "output", 440*724ba675SRob Herring "sample"; 441*724ba675SRob Herring resets = <&ccu RST_AHB1_MMC2>; 442*724ba675SRob Herring reset-names = "ahb"; 443*724ba675SRob Herring interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 444*724ba675SRob Herring status = "disabled"; 445*724ba675SRob Herring #address-cells = <1>; 446*724ba675SRob Herring #size-cells = <0>; 447*724ba675SRob Herring }; 448*724ba675SRob Herring 449*724ba675SRob Herring mmc3: mmc@1c12000 { 450*724ba675SRob Herring compatible = "allwinner,sun7i-a20-mmc"; 451*724ba675SRob Herring reg = <0x01c12000 0x1000>; 452*724ba675SRob Herring clocks = <&ccu CLK_AHB1_MMC3>, 453*724ba675SRob Herring <&ccu CLK_MMC3>, 454*724ba675SRob Herring <&ccu CLK_MMC3_OUTPUT>, 455*724ba675SRob Herring <&ccu CLK_MMC3_SAMPLE>; 456*724ba675SRob Herring clock-names = "ahb", 457*724ba675SRob Herring "mmc", 458*724ba675SRob Herring "output", 459*724ba675SRob Herring "sample"; 460*724ba675SRob Herring resets = <&ccu RST_AHB1_MMC3>; 461*724ba675SRob Herring reset-names = "ahb"; 462*724ba675SRob Herring interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 463*724ba675SRob Herring status = "disabled"; 464*724ba675SRob Herring #address-cells = <1>; 465*724ba675SRob Herring #size-cells = <0>; 466*724ba675SRob Herring }; 467*724ba675SRob Herring 468*724ba675SRob Herring hdmi: hdmi@1c16000 { 469*724ba675SRob Herring compatible = "allwinner,sun6i-a31-hdmi"; 470*724ba675SRob Herring reg = <0x01c16000 0x1000>; 471*724ba675SRob Herring interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 472*724ba675SRob Herring clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, 473*724ba675SRob Herring <&ccu CLK_HDMI_DDC>, 474*724ba675SRob Herring <&ccu CLK_PLL_VIDEO0_2X>, 475*724ba675SRob Herring <&ccu CLK_PLL_VIDEO1_2X>; 476*724ba675SRob Herring clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; 477*724ba675SRob Herring resets = <&ccu RST_AHB1_HDMI>; 478*724ba675SRob Herring dma-names = "ddc-tx", "ddc-rx", "audio-tx"; 479*724ba675SRob Herring dmas = <&dma 13>, <&dma 13>, <&dma 14>; 480*724ba675SRob Herring status = "disabled"; 481*724ba675SRob Herring 482*724ba675SRob Herring ports { 483*724ba675SRob Herring #address-cells = <1>; 484*724ba675SRob Herring #size-cells = <0>; 485*724ba675SRob Herring 486*724ba675SRob Herring hdmi_in: port@0 { 487*724ba675SRob Herring #address-cells = <1>; 488*724ba675SRob Herring #size-cells = <0>; 489*724ba675SRob Herring reg = <0>; 490*724ba675SRob Herring 491*724ba675SRob Herring hdmi_in_tcon0: endpoint@0 { 492*724ba675SRob Herring reg = <0>; 493*724ba675SRob Herring remote-endpoint = <&tcon0_out_hdmi>; 494*724ba675SRob Herring }; 495*724ba675SRob Herring 496*724ba675SRob Herring hdmi_in_tcon1: endpoint@1 { 497*724ba675SRob Herring reg = <1>; 498*724ba675SRob Herring remote-endpoint = <&tcon1_out_hdmi>; 499*724ba675SRob Herring }; 500*724ba675SRob Herring }; 501*724ba675SRob Herring 502*724ba675SRob Herring hdmi_out: port@1 { 503*724ba675SRob Herring reg = <1>; 504*724ba675SRob Herring }; 505*724ba675SRob Herring }; 506*724ba675SRob Herring }; 507*724ba675SRob Herring 508*724ba675SRob Herring usb_otg: usb@1c19000 { 509*724ba675SRob Herring compatible = "allwinner,sun6i-a31-musb"; 510*724ba675SRob Herring reg = <0x01c19000 0x0400>; 511*724ba675SRob Herring clocks = <&ccu CLK_AHB1_OTG>; 512*724ba675SRob Herring resets = <&ccu RST_AHB1_OTG>; 513*724ba675SRob Herring interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 514*724ba675SRob Herring interrupt-names = "mc"; 515*724ba675SRob Herring phys = <&usbphy 0>; 516*724ba675SRob Herring phy-names = "usb"; 517*724ba675SRob Herring extcon = <&usbphy 0>; 518*724ba675SRob Herring dr_mode = "otg"; 519*724ba675SRob Herring status = "disabled"; 520*724ba675SRob Herring }; 521*724ba675SRob Herring 522*724ba675SRob Herring usbphy: phy@1c19400 { 523*724ba675SRob Herring compatible = "allwinner,sun6i-a31-usb-phy"; 524*724ba675SRob Herring reg = <0x01c19400 0x10>, 525*724ba675SRob Herring <0x01c1a800 0x4>, 526*724ba675SRob Herring <0x01c1b800 0x4>; 527*724ba675SRob Herring reg-names = "phy_ctrl", 528*724ba675SRob Herring "pmu1", 529*724ba675SRob Herring "pmu2"; 530*724ba675SRob Herring clocks = <&ccu CLK_USB_PHY0>, 531*724ba675SRob Herring <&ccu CLK_USB_PHY1>, 532*724ba675SRob Herring <&ccu CLK_USB_PHY2>; 533*724ba675SRob Herring clock-names = "usb0_phy", 534*724ba675SRob Herring "usb1_phy", 535*724ba675SRob Herring "usb2_phy"; 536*724ba675SRob Herring resets = <&ccu RST_USB_PHY0>, 537*724ba675SRob Herring <&ccu RST_USB_PHY1>, 538*724ba675SRob Herring <&ccu RST_USB_PHY2>; 539*724ba675SRob Herring reset-names = "usb0_reset", 540*724ba675SRob Herring "usb1_reset", 541*724ba675SRob Herring "usb2_reset"; 542*724ba675SRob Herring status = "disabled"; 543*724ba675SRob Herring #phy-cells = <1>; 544*724ba675SRob Herring }; 545*724ba675SRob Herring 546*724ba675SRob Herring ehci0: usb@1c1a000 { 547*724ba675SRob Herring compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 548*724ba675SRob Herring reg = <0x01c1a000 0x100>; 549*724ba675SRob Herring interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 550*724ba675SRob Herring clocks = <&ccu CLK_AHB1_EHCI0>; 551*724ba675SRob Herring resets = <&ccu RST_AHB1_EHCI0>; 552*724ba675SRob Herring phys = <&usbphy 1>; 553*724ba675SRob Herring phy-names = "usb"; 554*724ba675SRob Herring status = "disabled"; 555*724ba675SRob Herring }; 556*724ba675SRob Herring 557*724ba675SRob Herring ohci0: usb@1c1a400 { 558*724ba675SRob Herring compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 559*724ba675SRob Herring reg = <0x01c1a400 0x100>; 560*724ba675SRob Herring interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 561*724ba675SRob Herring clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; 562*724ba675SRob Herring resets = <&ccu RST_AHB1_OHCI0>; 563*724ba675SRob Herring phys = <&usbphy 1>; 564*724ba675SRob Herring phy-names = "usb"; 565*724ba675SRob Herring status = "disabled"; 566*724ba675SRob Herring }; 567*724ba675SRob Herring 568*724ba675SRob Herring ehci1: usb@1c1b000 { 569*724ba675SRob Herring compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 570*724ba675SRob Herring reg = <0x01c1b000 0x100>; 571*724ba675SRob Herring interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 572*724ba675SRob Herring clocks = <&ccu CLK_AHB1_EHCI1>; 573*724ba675SRob Herring resets = <&ccu RST_AHB1_EHCI1>; 574*724ba675SRob Herring phys = <&usbphy 2>; 575*724ba675SRob Herring phy-names = "usb"; 576*724ba675SRob Herring status = "disabled"; 577*724ba675SRob Herring }; 578*724ba675SRob Herring 579*724ba675SRob Herring ohci1: usb@1c1b400 { 580*724ba675SRob Herring compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 581*724ba675SRob Herring reg = <0x01c1b400 0x100>; 582*724ba675SRob Herring interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 583*724ba675SRob Herring clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; 584*724ba675SRob Herring resets = <&ccu RST_AHB1_OHCI1>; 585*724ba675SRob Herring phys = <&usbphy 2>; 586*724ba675SRob Herring phy-names = "usb"; 587*724ba675SRob Herring status = "disabled"; 588*724ba675SRob Herring }; 589*724ba675SRob Herring 590*724ba675SRob Herring ohci2: usb@1c1c400 { 591*724ba675SRob Herring compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 592*724ba675SRob Herring reg = <0x01c1c400 0x100>; 593*724ba675SRob Herring interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 594*724ba675SRob Herring clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; 595*724ba675SRob Herring resets = <&ccu RST_AHB1_OHCI2>; 596*724ba675SRob Herring status = "disabled"; 597*724ba675SRob Herring }; 598*724ba675SRob Herring 599*724ba675SRob Herring ccu: clock@1c20000 { 600*724ba675SRob Herring compatible = "allwinner,sun6i-a31-ccu"; 601*724ba675SRob Herring reg = <0x01c20000 0x400>; 602*724ba675SRob Herring clocks = <&osc24M>, <&rtc CLK_OSC32K>; 603*724ba675SRob Herring clock-names = "hosc", "losc"; 604*724ba675SRob Herring #clock-cells = <1>; 605*724ba675SRob Herring #reset-cells = <1>; 606*724ba675SRob Herring }; 607*724ba675SRob Herring 608*724ba675SRob Herring pio: pinctrl@1c20800 { 609*724ba675SRob Herring compatible = "allwinner,sun6i-a31-pinctrl"; 610*724ba675SRob Herring reg = <0x01c20800 0x400>; 611*724ba675SRob Herring interrupt-parent = <&r_intc>; 612*724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 613*724ba675SRob Herring <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 614*724ba675SRob Herring <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 615*724ba675SRob Herring <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 616*724ba675SRob Herring clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, 617*724ba675SRob Herring <&rtc CLK_OSC32K>; 618*724ba675SRob Herring clock-names = "apb", "hosc", "losc"; 619*724ba675SRob Herring gpio-controller; 620*724ba675SRob Herring interrupt-controller; 621*724ba675SRob Herring #interrupt-cells = <3>; 622*724ba675SRob Herring #gpio-cells = <3>; 623*724ba675SRob Herring 624*724ba675SRob Herring gmac_gmii_pins: gmac-gmii-pins { 625*724ba675SRob Herring pins = "PA0", "PA1", "PA2", "PA3", 626*724ba675SRob Herring "PA4", "PA5", "PA6", "PA7", 627*724ba675SRob Herring "PA8", "PA9", "PA10", "PA11", 628*724ba675SRob Herring "PA12", "PA13", "PA14", "PA15", 629*724ba675SRob Herring "PA16", "PA17", "PA18", "PA19", 630*724ba675SRob Herring "PA20", "PA21", "PA22", "PA23", 631*724ba675SRob Herring "PA24", "PA25", "PA26", "PA27"; 632*724ba675SRob Herring function = "gmac"; 633*724ba675SRob Herring /* 634*724ba675SRob Herring * data lines in GMII mode run at 125MHz and 635*724ba675SRob Herring * might need a higher signal drive strength 636*724ba675SRob Herring */ 637*724ba675SRob Herring drive-strength = <30>; 638*724ba675SRob Herring }; 639*724ba675SRob Herring 640*724ba675SRob Herring gmac_mii_pins: gmac-mii-pins { 641*724ba675SRob Herring pins = "PA0", "PA1", "PA2", "PA3", 642*724ba675SRob Herring "PA8", "PA9", "PA11", 643*724ba675SRob Herring "PA12", "PA13", "PA14", "PA19", 644*724ba675SRob Herring "PA20", "PA21", "PA22", "PA23", 645*724ba675SRob Herring "PA24", "PA26", "PA27"; 646*724ba675SRob Herring function = "gmac"; 647*724ba675SRob Herring }; 648*724ba675SRob Herring 649*724ba675SRob Herring gmac_rgmii_pins: gmac-rgmii-pins { 650*724ba675SRob Herring pins = "PA0", "PA1", "PA2", "PA3", 651*724ba675SRob Herring "PA9", "PA10", "PA11", 652*724ba675SRob Herring "PA12", "PA13", "PA14", "PA19", 653*724ba675SRob Herring "PA20", "PA25", "PA26", "PA27"; 654*724ba675SRob Herring function = "gmac"; 655*724ba675SRob Herring /* 656*724ba675SRob Herring * data lines in RGMII mode use DDR mode 657*724ba675SRob Herring * and need a higher signal drive strength 658*724ba675SRob Herring */ 659*724ba675SRob Herring drive-strength = <40>; 660*724ba675SRob Herring }; 661*724ba675SRob Herring 662*724ba675SRob Herring i2c0_pins: i2c0-pins { 663*724ba675SRob Herring pins = "PH14", "PH15"; 664*724ba675SRob Herring function = "i2c0"; 665*724ba675SRob Herring }; 666*724ba675SRob Herring 667*724ba675SRob Herring i2c1_pins: i2c1-pins { 668*724ba675SRob Herring pins = "PH16", "PH17"; 669*724ba675SRob Herring function = "i2c1"; 670*724ba675SRob Herring }; 671*724ba675SRob Herring 672*724ba675SRob Herring i2c2_pins: i2c2-pins { 673*724ba675SRob Herring pins = "PH18", "PH19"; 674*724ba675SRob Herring function = "i2c2"; 675*724ba675SRob Herring }; 676*724ba675SRob Herring 677*724ba675SRob Herring lcd0_rgb888_pins: lcd0-rgb888-pins { 678*724ba675SRob Herring pins = "PD0", "PD1", "PD2", "PD3", 679*724ba675SRob Herring "PD4", "PD5", "PD6", "PD7", 680*724ba675SRob Herring "PD8", "PD9", "PD10", "PD11", 681*724ba675SRob Herring "PD12", "PD13", "PD14", "PD15", 682*724ba675SRob Herring "PD16", "PD17", "PD18", "PD19", 683*724ba675SRob Herring "PD20", "PD21", "PD22", "PD23", 684*724ba675SRob Herring "PD24", "PD25", "PD26", "PD27"; 685*724ba675SRob Herring function = "lcd0"; 686*724ba675SRob Herring }; 687*724ba675SRob Herring 688*724ba675SRob Herring mmc0_pins: mmc0-pins { 689*724ba675SRob Herring pins = "PF0", "PF1", "PF2", 690*724ba675SRob Herring "PF3", "PF4", "PF5"; 691*724ba675SRob Herring function = "mmc0"; 692*724ba675SRob Herring drive-strength = <30>; 693*724ba675SRob Herring bias-pull-up; 694*724ba675SRob Herring }; 695*724ba675SRob Herring 696*724ba675SRob Herring mmc1_pins: mmc1-pins { 697*724ba675SRob Herring pins = "PG0", "PG1", "PG2", "PG3", 698*724ba675SRob Herring "PG4", "PG5"; 699*724ba675SRob Herring function = "mmc1"; 700*724ba675SRob Herring drive-strength = <30>; 701*724ba675SRob Herring bias-pull-up; 702*724ba675SRob Herring }; 703*724ba675SRob Herring 704*724ba675SRob Herring mmc2_4bit_pins: mmc2-4bit-pins { 705*724ba675SRob Herring pins = "PC6", "PC7", "PC8", "PC9", 706*724ba675SRob Herring "PC10", "PC11"; 707*724ba675SRob Herring function = "mmc2"; 708*724ba675SRob Herring drive-strength = <30>; 709*724ba675SRob Herring bias-pull-up; 710*724ba675SRob Herring }; 711*724ba675SRob Herring 712*724ba675SRob Herring mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins { 713*724ba675SRob Herring pins = "PC6", "PC7", "PC8", "PC9", 714*724ba675SRob Herring "PC10", "PC11", "PC12", 715*724ba675SRob Herring "PC13", "PC14", "PC15", 716*724ba675SRob Herring "PC24"; 717*724ba675SRob Herring function = "mmc2"; 718*724ba675SRob Herring drive-strength = <30>; 719*724ba675SRob Herring bias-pull-up; 720*724ba675SRob Herring }; 721*724ba675SRob Herring 722*724ba675SRob Herring mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins { 723*724ba675SRob Herring pins = "PC6", "PC7", "PC8", "PC9", 724*724ba675SRob Herring "PC10", "PC11", "PC12", 725*724ba675SRob Herring "PC13", "PC14", "PC15", 726*724ba675SRob Herring "PC24"; 727*724ba675SRob Herring function = "mmc3"; 728*724ba675SRob Herring drive-strength = <40>; 729*724ba675SRob Herring bias-pull-up; 730*724ba675SRob Herring }; 731*724ba675SRob Herring 732*724ba675SRob Herring spdif_tx_pin: spdif-tx-pin { 733*724ba675SRob Herring pins = "PH28"; 734*724ba675SRob Herring function = "spdif"; 735*724ba675SRob Herring }; 736*724ba675SRob Herring 737*724ba675SRob Herring uart0_ph_pins: uart0-ph-pins { 738*724ba675SRob Herring pins = "PH20", "PH21"; 739*724ba675SRob Herring function = "uart0"; 740*724ba675SRob Herring }; 741*724ba675SRob Herring }; 742*724ba675SRob Herring 743*724ba675SRob Herring timer@1c20c00 { 744*724ba675SRob Herring compatible = "allwinner,sun4i-a10-timer"; 745*724ba675SRob Herring reg = <0x01c20c00 0xa0>; 746*724ba675SRob Herring interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 747*724ba675SRob Herring <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 748*724ba675SRob Herring <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 749*724ba675SRob Herring <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 750*724ba675SRob Herring <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 751*724ba675SRob Herring <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 752*724ba675SRob Herring clocks = <&osc24M>; 753*724ba675SRob Herring }; 754*724ba675SRob Herring 755*724ba675SRob Herring wdt1: watchdog@1c20ca0 { 756*724ba675SRob Herring compatible = "allwinner,sun6i-a31-wdt"; 757*724ba675SRob Herring reg = <0x01c20ca0 0x20>; 758*724ba675SRob Herring interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 759*724ba675SRob Herring clocks = <&osc24M>; 760*724ba675SRob Herring }; 761*724ba675SRob Herring 762*724ba675SRob Herring spdif: spdif@1c21000 { 763*724ba675SRob Herring #sound-dai-cells = <0>; 764*724ba675SRob Herring compatible = "allwinner,sun6i-a31-spdif"; 765*724ba675SRob Herring reg = <0x01c21000 0x400>; 766*724ba675SRob Herring interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 767*724ba675SRob Herring clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>; 768*724ba675SRob Herring resets = <&ccu RST_APB1_SPDIF>; 769*724ba675SRob Herring clock-names = "apb", "spdif"; 770*724ba675SRob Herring dmas = <&dma 2>, <&dma 2>; 771*724ba675SRob Herring dma-names = "rx", "tx"; 772*724ba675SRob Herring status = "disabled"; 773*724ba675SRob Herring }; 774*724ba675SRob Herring 775*724ba675SRob Herring i2s0: i2s@1c22000 { 776*724ba675SRob Herring #sound-dai-cells = <0>; 777*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2s"; 778*724ba675SRob Herring reg = <0x01c22000 0x400>; 779*724ba675SRob Herring interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 780*724ba675SRob Herring clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>; 781*724ba675SRob Herring resets = <&ccu RST_APB1_DAUDIO0>; 782*724ba675SRob Herring clock-names = "apb", "mod"; 783*724ba675SRob Herring dmas = <&dma 3>, <&dma 3>; 784*724ba675SRob Herring dma-names = "rx", "tx"; 785*724ba675SRob Herring status = "disabled"; 786*724ba675SRob Herring }; 787*724ba675SRob Herring 788*724ba675SRob Herring i2s1: i2s@1c22400 { 789*724ba675SRob Herring #sound-dai-cells = <0>; 790*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2s"; 791*724ba675SRob Herring reg = <0x01c22400 0x400>; 792*724ba675SRob Herring interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 793*724ba675SRob Herring clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>; 794*724ba675SRob Herring resets = <&ccu RST_APB1_DAUDIO1>; 795*724ba675SRob Herring clock-names = "apb", "mod"; 796*724ba675SRob Herring dmas = <&dma 4>, <&dma 4>; 797*724ba675SRob Herring dma-names = "rx", "tx"; 798*724ba675SRob Herring status = "disabled"; 799*724ba675SRob Herring }; 800*724ba675SRob Herring 801*724ba675SRob Herring lradc: lradc@1c22800 { 802*724ba675SRob Herring compatible = "allwinner,sun4i-a10-lradc-keys"; 803*724ba675SRob Herring reg = <0x01c22800 0x100>; 804*724ba675SRob Herring interrupt-parent = <&r_intc>; 805*724ba675SRob Herring interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 806*724ba675SRob Herring status = "disabled"; 807*724ba675SRob Herring }; 808*724ba675SRob Herring 809*724ba675SRob Herring rtp: rtp@1c25000 { 810*724ba675SRob Herring compatible = "allwinner,sun6i-a31-ts"; 811*724ba675SRob Herring reg = <0x01c25000 0x100>; 812*724ba675SRob Herring interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 813*724ba675SRob Herring #thermal-sensor-cells = <0>; 814*724ba675SRob Herring }; 815*724ba675SRob Herring 816*724ba675SRob Herring uart0: serial@1c28000 { 817*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 818*724ba675SRob Herring reg = <0x01c28000 0x400>; 819*724ba675SRob Herring interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 820*724ba675SRob Herring reg-shift = <2>; 821*724ba675SRob Herring reg-io-width = <4>; 822*724ba675SRob Herring clocks = <&ccu CLK_APB2_UART0>; 823*724ba675SRob Herring resets = <&ccu RST_APB2_UART0>; 824*724ba675SRob Herring dmas = <&dma 6>, <&dma 6>; 825*724ba675SRob Herring dma-names = "tx", "rx"; 826*724ba675SRob Herring status = "disabled"; 827*724ba675SRob Herring }; 828*724ba675SRob Herring 829*724ba675SRob Herring uart1: serial@1c28400 { 830*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 831*724ba675SRob Herring reg = <0x01c28400 0x400>; 832*724ba675SRob Herring interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 833*724ba675SRob Herring reg-shift = <2>; 834*724ba675SRob Herring reg-io-width = <4>; 835*724ba675SRob Herring clocks = <&ccu CLK_APB2_UART1>; 836*724ba675SRob Herring resets = <&ccu RST_APB2_UART1>; 837*724ba675SRob Herring dmas = <&dma 7>, <&dma 7>; 838*724ba675SRob Herring dma-names = "tx", "rx"; 839*724ba675SRob Herring status = "disabled"; 840*724ba675SRob Herring }; 841*724ba675SRob Herring 842*724ba675SRob Herring uart2: serial@1c28800 { 843*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 844*724ba675SRob Herring reg = <0x01c28800 0x400>; 845*724ba675SRob Herring interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 846*724ba675SRob Herring reg-shift = <2>; 847*724ba675SRob Herring reg-io-width = <4>; 848*724ba675SRob Herring clocks = <&ccu CLK_APB2_UART2>; 849*724ba675SRob Herring resets = <&ccu RST_APB2_UART2>; 850*724ba675SRob Herring dmas = <&dma 8>, <&dma 8>; 851*724ba675SRob Herring dma-names = "tx", "rx"; 852*724ba675SRob Herring status = "disabled"; 853*724ba675SRob Herring }; 854*724ba675SRob Herring 855*724ba675SRob Herring uart3: serial@1c28c00 { 856*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 857*724ba675SRob Herring reg = <0x01c28c00 0x400>; 858*724ba675SRob Herring interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 859*724ba675SRob Herring reg-shift = <2>; 860*724ba675SRob Herring reg-io-width = <4>; 861*724ba675SRob Herring clocks = <&ccu CLK_APB2_UART3>; 862*724ba675SRob Herring resets = <&ccu RST_APB2_UART3>; 863*724ba675SRob Herring dmas = <&dma 9>, <&dma 9>; 864*724ba675SRob Herring dma-names = "tx", "rx"; 865*724ba675SRob Herring status = "disabled"; 866*724ba675SRob Herring }; 867*724ba675SRob Herring 868*724ba675SRob Herring uart4: serial@1c29000 { 869*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 870*724ba675SRob Herring reg = <0x01c29000 0x400>; 871*724ba675SRob Herring interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 872*724ba675SRob Herring reg-shift = <2>; 873*724ba675SRob Herring reg-io-width = <4>; 874*724ba675SRob Herring clocks = <&ccu CLK_APB2_UART4>; 875*724ba675SRob Herring resets = <&ccu RST_APB2_UART4>; 876*724ba675SRob Herring dmas = <&dma 10>, <&dma 10>; 877*724ba675SRob Herring dma-names = "tx", "rx"; 878*724ba675SRob Herring status = "disabled"; 879*724ba675SRob Herring }; 880*724ba675SRob Herring 881*724ba675SRob Herring uart5: serial@1c29400 { 882*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 883*724ba675SRob Herring reg = <0x01c29400 0x400>; 884*724ba675SRob Herring interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 885*724ba675SRob Herring reg-shift = <2>; 886*724ba675SRob Herring reg-io-width = <4>; 887*724ba675SRob Herring clocks = <&ccu CLK_APB2_UART5>; 888*724ba675SRob Herring resets = <&ccu RST_APB2_UART5>; 889*724ba675SRob Herring dmas = <&dma 22>, <&dma 22>; 890*724ba675SRob Herring dma-names = "tx", "rx"; 891*724ba675SRob Herring status = "disabled"; 892*724ba675SRob Herring }; 893*724ba675SRob Herring 894*724ba675SRob Herring i2c0: i2c@1c2ac00 { 895*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 896*724ba675SRob Herring reg = <0x01c2ac00 0x400>; 897*724ba675SRob Herring interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 898*724ba675SRob Herring clocks = <&ccu CLK_APB2_I2C0>; 899*724ba675SRob Herring resets = <&ccu RST_APB2_I2C0>; 900*724ba675SRob Herring pinctrl-names = "default"; 901*724ba675SRob Herring pinctrl-0 = <&i2c0_pins>; 902*724ba675SRob Herring status = "disabled"; 903*724ba675SRob Herring #address-cells = <1>; 904*724ba675SRob Herring #size-cells = <0>; 905*724ba675SRob Herring }; 906*724ba675SRob Herring 907*724ba675SRob Herring i2c1: i2c@1c2b000 { 908*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 909*724ba675SRob Herring reg = <0x01c2b000 0x400>; 910*724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 911*724ba675SRob Herring clocks = <&ccu CLK_APB2_I2C1>; 912*724ba675SRob Herring resets = <&ccu RST_APB2_I2C1>; 913*724ba675SRob Herring pinctrl-names = "default"; 914*724ba675SRob Herring pinctrl-0 = <&i2c1_pins>; 915*724ba675SRob Herring status = "disabled"; 916*724ba675SRob Herring #address-cells = <1>; 917*724ba675SRob Herring #size-cells = <0>; 918*724ba675SRob Herring }; 919*724ba675SRob Herring 920*724ba675SRob Herring i2c2: i2c@1c2b400 { 921*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 922*724ba675SRob Herring reg = <0x01c2b400 0x400>; 923*724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 924*724ba675SRob Herring clocks = <&ccu CLK_APB2_I2C2>; 925*724ba675SRob Herring resets = <&ccu RST_APB2_I2C2>; 926*724ba675SRob Herring pinctrl-names = "default"; 927*724ba675SRob Herring pinctrl-0 = <&i2c2_pins>; 928*724ba675SRob Herring status = "disabled"; 929*724ba675SRob Herring #address-cells = <1>; 930*724ba675SRob Herring #size-cells = <0>; 931*724ba675SRob Herring }; 932*724ba675SRob Herring 933*724ba675SRob Herring i2c3: i2c@1c2b800 { 934*724ba675SRob Herring compatible = "allwinner,sun6i-a31-i2c"; 935*724ba675SRob Herring reg = <0x01c2b800 0x400>; 936*724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 937*724ba675SRob Herring clocks = <&ccu CLK_APB2_I2C3>; 938*724ba675SRob Herring resets = <&ccu RST_APB2_I2C3>; 939*724ba675SRob Herring status = "disabled"; 940*724ba675SRob Herring #address-cells = <1>; 941*724ba675SRob Herring #size-cells = <0>; 942*724ba675SRob Herring }; 943*724ba675SRob Herring 944*724ba675SRob Herring gmac: ethernet@1c30000 { 945*724ba675SRob Herring compatible = "allwinner,sun7i-a20-gmac"; 946*724ba675SRob Herring reg = <0x01c30000 0x1054>; 947*724ba675SRob Herring interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 948*724ba675SRob Herring interrupt-names = "macirq"; 949*724ba675SRob Herring clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; 950*724ba675SRob Herring clock-names = "stmmaceth", "allwinner_gmac_tx"; 951*724ba675SRob Herring resets = <&ccu RST_AHB1_EMAC>; 952*724ba675SRob Herring reset-names = "stmmaceth"; 953*724ba675SRob Herring snps,pbl = <2>; 954*724ba675SRob Herring snps,fixed-burst; 955*724ba675SRob Herring snps,force_sf_dma_mode; 956*724ba675SRob Herring status = "disabled"; 957*724ba675SRob Herring 958*724ba675SRob Herring mdio: mdio { 959*724ba675SRob Herring compatible = "snps,dwmac-mdio"; 960*724ba675SRob Herring #address-cells = <1>; 961*724ba675SRob Herring #size-cells = <0>; 962*724ba675SRob Herring }; 963*724ba675SRob Herring }; 964*724ba675SRob Herring 965*724ba675SRob Herring crypto: crypto-engine@1c15000 { 966*724ba675SRob Herring compatible = "allwinner,sun6i-a31-crypto", 967*724ba675SRob Herring "allwinner,sun4i-a10-crypto"; 968*724ba675SRob Herring reg = <0x01c15000 0x1000>; 969*724ba675SRob Herring interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 970*724ba675SRob Herring clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; 971*724ba675SRob Herring clock-names = "ahb", "mod"; 972*724ba675SRob Herring resets = <&ccu RST_AHB1_SS>; 973*724ba675SRob Herring reset-names = "ahb"; 974*724ba675SRob Herring }; 975*724ba675SRob Herring 976*724ba675SRob Herring codec: codec@1c22c00 { 977*724ba675SRob Herring #sound-dai-cells = <0>; 978*724ba675SRob Herring compatible = "allwinner,sun6i-a31-codec"; 979*724ba675SRob Herring reg = <0x01c22c00 0x400>; 980*724ba675SRob Herring interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 981*724ba675SRob Herring clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; 982*724ba675SRob Herring clock-names = "apb", "codec"; 983*724ba675SRob Herring resets = <&ccu RST_APB1_CODEC>; 984*724ba675SRob Herring dmas = <&dma 15>, <&dma 15>; 985*724ba675SRob Herring dma-names = "rx", "tx"; 986*724ba675SRob Herring status = "disabled"; 987*724ba675SRob Herring }; 988*724ba675SRob Herring 989*724ba675SRob Herring timer@1c60000 { 990*724ba675SRob Herring compatible = "allwinner,sun6i-a31-hstimer", 991*724ba675SRob Herring "allwinner,sun7i-a20-hstimer"; 992*724ba675SRob Herring reg = <0x01c60000 0x1000>; 993*724ba675SRob Herring interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 994*724ba675SRob Herring <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 995*724ba675SRob Herring <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 996*724ba675SRob Herring <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 997*724ba675SRob Herring clocks = <&ccu CLK_AHB1_HSTIMER>; 998*724ba675SRob Herring resets = <&ccu RST_AHB1_HSTIMER>; 999*724ba675SRob Herring }; 1000*724ba675SRob Herring 1001*724ba675SRob Herring spi0: spi@1c68000 { 1002*724ba675SRob Herring compatible = "allwinner,sun6i-a31-spi"; 1003*724ba675SRob Herring reg = <0x01c68000 0x1000>; 1004*724ba675SRob Herring interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1005*724ba675SRob Herring clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; 1006*724ba675SRob Herring clock-names = "ahb", "mod"; 1007*724ba675SRob Herring dmas = <&dma 23>, <&dma 23>; 1008*724ba675SRob Herring dma-names = "rx", "tx"; 1009*724ba675SRob Herring resets = <&ccu RST_AHB1_SPI0>; 1010*724ba675SRob Herring status = "disabled"; 1011*724ba675SRob Herring #address-cells = <1>; 1012*724ba675SRob Herring #size-cells = <0>; 1013*724ba675SRob Herring }; 1014*724ba675SRob Herring 1015*724ba675SRob Herring spi1: spi@1c69000 { 1016*724ba675SRob Herring compatible = "allwinner,sun6i-a31-spi"; 1017*724ba675SRob Herring reg = <0x01c69000 0x1000>; 1018*724ba675SRob Herring interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1019*724ba675SRob Herring clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; 1020*724ba675SRob Herring clock-names = "ahb", "mod"; 1021*724ba675SRob Herring dmas = <&dma 24>, <&dma 24>; 1022*724ba675SRob Herring dma-names = "rx", "tx"; 1023*724ba675SRob Herring resets = <&ccu RST_AHB1_SPI1>; 1024*724ba675SRob Herring status = "disabled"; 1025*724ba675SRob Herring #address-cells = <1>; 1026*724ba675SRob Herring #size-cells = <0>; 1027*724ba675SRob Herring }; 1028*724ba675SRob Herring 1029*724ba675SRob Herring spi2: spi@1c6a000 { 1030*724ba675SRob Herring compatible = "allwinner,sun6i-a31-spi"; 1031*724ba675SRob Herring reg = <0x01c6a000 0x1000>; 1032*724ba675SRob Herring interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1033*724ba675SRob Herring clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; 1034*724ba675SRob Herring clock-names = "ahb", "mod"; 1035*724ba675SRob Herring dmas = <&dma 25>, <&dma 25>; 1036*724ba675SRob Herring dma-names = "rx", "tx"; 1037*724ba675SRob Herring resets = <&ccu RST_AHB1_SPI2>; 1038*724ba675SRob Herring status = "disabled"; 1039*724ba675SRob Herring #address-cells = <1>; 1040*724ba675SRob Herring #size-cells = <0>; 1041*724ba675SRob Herring }; 1042*724ba675SRob Herring 1043*724ba675SRob Herring spi3: spi@1c6b000 { 1044*724ba675SRob Herring compatible = "allwinner,sun6i-a31-spi"; 1045*724ba675SRob Herring reg = <0x01c6b000 0x1000>; 1046*724ba675SRob Herring interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1047*724ba675SRob Herring clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; 1048*724ba675SRob Herring clock-names = "ahb", "mod"; 1049*724ba675SRob Herring dmas = <&dma 26>, <&dma 26>; 1050*724ba675SRob Herring dma-names = "rx", "tx"; 1051*724ba675SRob Herring resets = <&ccu RST_AHB1_SPI3>; 1052*724ba675SRob Herring status = "disabled"; 1053*724ba675SRob Herring #address-cells = <1>; 1054*724ba675SRob Herring #size-cells = <0>; 1055*724ba675SRob Herring }; 1056*724ba675SRob Herring 1057*724ba675SRob Herring gic: interrupt-controller@1c81000 { 1058*724ba675SRob Herring compatible = "arm,gic-400"; 1059*724ba675SRob Herring reg = <0x01c81000 0x1000>, 1060*724ba675SRob Herring <0x01c82000 0x2000>, 1061*724ba675SRob Herring <0x01c84000 0x2000>, 1062*724ba675SRob Herring <0x01c86000 0x2000>; 1063*724ba675SRob Herring interrupt-controller; 1064*724ba675SRob Herring #interrupt-cells = <3>; 1065*724ba675SRob Herring interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1066*724ba675SRob Herring }; 1067*724ba675SRob Herring 1068*724ba675SRob Herring fe0: display-frontend@1e00000 { 1069*724ba675SRob Herring compatible = "allwinner,sun6i-a31-display-frontend"; 1070*724ba675SRob Herring reg = <0x01e00000 0x20000>; 1071*724ba675SRob Herring interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1072*724ba675SRob Herring clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>, 1073*724ba675SRob Herring <&ccu CLK_DRAM_FE0>; 1074*724ba675SRob Herring clock-names = "ahb", "mod", 1075*724ba675SRob Herring "ram"; 1076*724ba675SRob Herring resets = <&ccu RST_AHB1_FE0>; 1077*724ba675SRob Herring 1078*724ba675SRob Herring ports { 1079*724ba675SRob Herring #address-cells = <1>; 1080*724ba675SRob Herring #size-cells = <0>; 1081*724ba675SRob Herring 1082*724ba675SRob Herring fe0_out: port@1 { 1083*724ba675SRob Herring #address-cells = <1>; 1084*724ba675SRob Herring #size-cells = <0>; 1085*724ba675SRob Herring reg = <1>; 1086*724ba675SRob Herring 1087*724ba675SRob Herring fe0_out_be0: endpoint@0 { 1088*724ba675SRob Herring reg = <0>; 1089*724ba675SRob Herring remote-endpoint = <&be0_in_fe0>; 1090*724ba675SRob Herring }; 1091*724ba675SRob Herring 1092*724ba675SRob Herring fe0_out_be1: endpoint@1 { 1093*724ba675SRob Herring reg = <1>; 1094*724ba675SRob Herring remote-endpoint = <&be1_in_fe0>; 1095*724ba675SRob Herring }; 1096*724ba675SRob Herring }; 1097*724ba675SRob Herring }; 1098*724ba675SRob Herring }; 1099*724ba675SRob Herring 1100*724ba675SRob Herring fe1: display-frontend@1e20000 { 1101*724ba675SRob Herring compatible = "allwinner,sun6i-a31-display-frontend"; 1102*724ba675SRob Herring reg = <0x01e20000 0x20000>; 1103*724ba675SRob Herring interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1104*724ba675SRob Herring clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>, 1105*724ba675SRob Herring <&ccu CLK_DRAM_FE1>; 1106*724ba675SRob Herring clock-names = "ahb", "mod", 1107*724ba675SRob Herring "ram"; 1108*724ba675SRob Herring resets = <&ccu RST_AHB1_FE1>; 1109*724ba675SRob Herring 1110*724ba675SRob Herring ports { 1111*724ba675SRob Herring #address-cells = <1>; 1112*724ba675SRob Herring #size-cells = <0>; 1113*724ba675SRob Herring 1114*724ba675SRob Herring fe1_out: port@1 { 1115*724ba675SRob Herring #address-cells = <1>; 1116*724ba675SRob Herring #size-cells = <0>; 1117*724ba675SRob Herring reg = <1>; 1118*724ba675SRob Herring 1119*724ba675SRob Herring fe1_out_be0: endpoint@0 { 1120*724ba675SRob Herring reg = <0>; 1121*724ba675SRob Herring remote-endpoint = <&be0_in_fe1>; 1122*724ba675SRob Herring }; 1123*724ba675SRob Herring 1124*724ba675SRob Herring fe1_out_be1: endpoint@1 { 1125*724ba675SRob Herring reg = <1>; 1126*724ba675SRob Herring remote-endpoint = <&be1_in_fe1>; 1127*724ba675SRob Herring }; 1128*724ba675SRob Herring }; 1129*724ba675SRob Herring }; 1130*724ba675SRob Herring }; 1131*724ba675SRob Herring 1132*724ba675SRob Herring be1: display-backend@1e40000 { 1133*724ba675SRob Herring compatible = "allwinner,sun6i-a31-display-backend"; 1134*724ba675SRob Herring reg = <0x01e40000 0x10000>; 1135*724ba675SRob Herring interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1136*724ba675SRob Herring clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>, 1137*724ba675SRob Herring <&ccu CLK_DRAM_BE1>; 1138*724ba675SRob Herring clock-names = "ahb", "mod", 1139*724ba675SRob Herring "ram"; 1140*724ba675SRob Herring resets = <&ccu RST_AHB1_BE1>; 1141*724ba675SRob Herring 1142*724ba675SRob Herring ports { 1143*724ba675SRob Herring #address-cells = <1>; 1144*724ba675SRob Herring #size-cells = <0>; 1145*724ba675SRob Herring 1146*724ba675SRob Herring be1_in: port@0 { 1147*724ba675SRob Herring #address-cells = <1>; 1148*724ba675SRob Herring #size-cells = <0>; 1149*724ba675SRob Herring reg = <0>; 1150*724ba675SRob Herring 1151*724ba675SRob Herring be1_in_fe0: endpoint@0 { 1152*724ba675SRob Herring reg = <0>; 1153*724ba675SRob Herring remote-endpoint = <&fe0_out_be1>; 1154*724ba675SRob Herring }; 1155*724ba675SRob Herring 1156*724ba675SRob Herring be1_in_fe1: endpoint@1 { 1157*724ba675SRob Herring reg = <1>; 1158*724ba675SRob Herring remote-endpoint = <&fe1_out_be1>; 1159*724ba675SRob Herring }; 1160*724ba675SRob Herring }; 1161*724ba675SRob Herring 1162*724ba675SRob Herring be1_out: port@1 { 1163*724ba675SRob Herring #address-cells = <1>; 1164*724ba675SRob Herring #size-cells = <0>; 1165*724ba675SRob Herring reg = <1>; 1166*724ba675SRob Herring 1167*724ba675SRob Herring be1_out_drc1: endpoint@1 { 1168*724ba675SRob Herring reg = <1>; 1169*724ba675SRob Herring remote-endpoint = <&drc1_in_be1>; 1170*724ba675SRob Herring }; 1171*724ba675SRob Herring }; 1172*724ba675SRob Herring }; 1173*724ba675SRob Herring }; 1174*724ba675SRob Herring 1175*724ba675SRob Herring drc1: drc@1e50000 { 1176*724ba675SRob Herring compatible = "allwinner,sun6i-a31-drc"; 1177*724ba675SRob Herring reg = <0x01e50000 0x10000>; 1178*724ba675SRob Herring interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1179*724ba675SRob Herring clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>, 1180*724ba675SRob Herring <&ccu CLK_DRAM_DRC1>; 1181*724ba675SRob Herring clock-names = "ahb", "mod", 1182*724ba675SRob Herring "ram"; 1183*724ba675SRob Herring resets = <&ccu RST_AHB1_DRC1>; 1184*724ba675SRob Herring 1185*724ba675SRob Herring ports { 1186*724ba675SRob Herring #address-cells = <1>; 1187*724ba675SRob Herring #size-cells = <0>; 1188*724ba675SRob Herring 1189*724ba675SRob Herring drc1_in: port@0 { 1190*724ba675SRob Herring #address-cells = <1>; 1191*724ba675SRob Herring #size-cells = <0>; 1192*724ba675SRob Herring reg = <0>; 1193*724ba675SRob Herring 1194*724ba675SRob Herring drc1_in_be1: endpoint@1 { 1195*724ba675SRob Herring reg = <1>; 1196*724ba675SRob Herring remote-endpoint = <&be1_out_drc1>; 1197*724ba675SRob Herring }; 1198*724ba675SRob Herring }; 1199*724ba675SRob Herring 1200*724ba675SRob Herring drc1_out: port@1 { 1201*724ba675SRob Herring #address-cells = <1>; 1202*724ba675SRob Herring #size-cells = <0>; 1203*724ba675SRob Herring reg = <1>; 1204*724ba675SRob Herring 1205*724ba675SRob Herring drc1_out_tcon0: endpoint@0 { 1206*724ba675SRob Herring reg = <0>; 1207*724ba675SRob Herring remote-endpoint = <&tcon0_in_drc1>; 1208*724ba675SRob Herring }; 1209*724ba675SRob Herring 1210*724ba675SRob Herring drc1_out_tcon1: endpoint@1 { 1211*724ba675SRob Herring reg = <1>; 1212*724ba675SRob Herring remote-endpoint = <&tcon1_in_drc1>; 1213*724ba675SRob Herring }; 1214*724ba675SRob Herring }; 1215*724ba675SRob Herring }; 1216*724ba675SRob Herring }; 1217*724ba675SRob Herring 1218*724ba675SRob Herring be0: display-backend@1e60000 { 1219*724ba675SRob Herring compatible = "allwinner,sun6i-a31-display-backend"; 1220*724ba675SRob Herring reg = <0x01e60000 0x10000>; 1221*724ba675SRob Herring interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1222*724ba675SRob Herring clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>, 1223*724ba675SRob Herring <&ccu CLK_DRAM_BE0>; 1224*724ba675SRob Herring clock-names = "ahb", "mod", 1225*724ba675SRob Herring "ram"; 1226*724ba675SRob Herring resets = <&ccu RST_AHB1_BE0>; 1227*724ba675SRob Herring 1228*724ba675SRob Herring ports { 1229*724ba675SRob Herring #address-cells = <1>; 1230*724ba675SRob Herring #size-cells = <0>; 1231*724ba675SRob Herring 1232*724ba675SRob Herring be0_in: port@0 { 1233*724ba675SRob Herring #address-cells = <1>; 1234*724ba675SRob Herring #size-cells = <0>; 1235*724ba675SRob Herring reg = <0>; 1236*724ba675SRob Herring 1237*724ba675SRob Herring be0_in_fe0: endpoint@0 { 1238*724ba675SRob Herring reg = <0>; 1239*724ba675SRob Herring remote-endpoint = <&fe0_out_be0>; 1240*724ba675SRob Herring }; 1241*724ba675SRob Herring 1242*724ba675SRob Herring be0_in_fe1: endpoint@1 { 1243*724ba675SRob Herring reg = <1>; 1244*724ba675SRob Herring remote-endpoint = <&fe1_out_be0>; 1245*724ba675SRob Herring }; 1246*724ba675SRob Herring }; 1247*724ba675SRob Herring 1248*724ba675SRob Herring be0_out: port@1 { 1249*724ba675SRob Herring reg = <1>; 1250*724ba675SRob Herring 1251*724ba675SRob Herring be0_out_drc0: endpoint { 1252*724ba675SRob Herring remote-endpoint = <&drc0_in_be0>; 1253*724ba675SRob Herring }; 1254*724ba675SRob Herring }; 1255*724ba675SRob Herring }; 1256*724ba675SRob Herring }; 1257*724ba675SRob Herring 1258*724ba675SRob Herring drc0: drc@1e70000 { 1259*724ba675SRob Herring compatible = "allwinner,sun6i-a31-drc"; 1260*724ba675SRob Herring reg = <0x01e70000 0x10000>; 1261*724ba675SRob Herring interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1262*724ba675SRob Herring clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, 1263*724ba675SRob Herring <&ccu CLK_DRAM_DRC0>; 1264*724ba675SRob Herring clock-names = "ahb", "mod", 1265*724ba675SRob Herring "ram"; 1266*724ba675SRob Herring resets = <&ccu RST_AHB1_DRC0>; 1267*724ba675SRob Herring 1268*724ba675SRob Herring ports { 1269*724ba675SRob Herring #address-cells = <1>; 1270*724ba675SRob Herring #size-cells = <0>; 1271*724ba675SRob Herring 1272*724ba675SRob Herring drc0_in: port@0 { 1273*724ba675SRob Herring reg = <0>; 1274*724ba675SRob Herring 1275*724ba675SRob Herring drc0_in_be0: endpoint { 1276*724ba675SRob Herring remote-endpoint = <&be0_out_drc0>; 1277*724ba675SRob Herring }; 1278*724ba675SRob Herring }; 1279*724ba675SRob Herring 1280*724ba675SRob Herring drc0_out: port@1 { 1281*724ba675SRob Herring #address-cells = <1>; 1282*724ba675SRob Herring #size-cells = <0>; 1283*724ba675SRob Herring reg = <1>; 1284*724ba675SRob Herring 1285*724ba675SRob Herring drc0_out_tcon0: endpoint@0 { 1286*724ba675SRob Herring reg = <0>; 1287*724ba675SRob Herring remote-endpoint = <&tcon0_in_drc0>; 1288*724ba675SRob Herring }; 1289*724ba675SRob Herring 1290*724ba675SRob Herring drc0_out_tcon1: endpoint@1 { 1291*724ba675SRob Herring reg = <1>; 1292*724ba675SRob Herring remote-endpoint = <&tcon1_in_drc0>; 1293*724ba675SRob Herring }; 1294*724ba675SRob Herring }; 1295*724ba675SRob Herring }; 1296*724ba675SRob Herring }; 1297*724ba675SRob Herring 1298*724ba675SRob Herring rtc: rtc@1f00000 { 1299*724ba675SRob Herring #clock-cells = <1>; 1300*724ba675SRob Herring compatible = "allwinner,sun6i-a31-rtc"; 1301*724ba675SRob Herring reg = <0x01f00000 0x54>; 1302*724ba675SRob Herring interrupt-parent = <&r_intc>; 1303*724ba675SRob Herring interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1304*724ba675SRob Herring <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1305*724ba675SRob Herring clocks = <&osc32k>; 1306*724ba675SRob Herring clock-output-names = "osc32k"; 1307*724ba675SRob Herring }; 1308*724ba675SRob Herring 1309*724ba675SRob Herring r_intc: interrupt-controller@1f00c00 { 1310*724ba675SRob Herring compatible = "allwinner,sun6i-a31-r-intc"; 1311*724ba675SRob Herring interrupt-controller; 1312*724ba675SRob Herring #interrupt-cells = <3>; 1313*724ba675SRob Herring reg = <0x01f00c00 0x400>; 1314*724ba675SRob Herring interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1315*724ba675SRob Herring }; 1316*724ba675SRob Herring 1317*724ba675SRob Herring prcm@1f01400 { 1318*724ba675SRob Herring compatible = "allwinner,sun6i-a31-prcm"; 1319*724ba675SRob Herring reg = <0x01f01400 0x200>; 1320*724ba675SRob Herring 1321*724ba675SRob Herring ar100: ar100_clk { 1322*724ba675SRob Herring compatible = "allwinner,sun6i-a31-ar100-clk"; 1323*724ba675SRob Herring #clock-cells = <0>; 1324*724ba675SRob Herring clocks = <&rtc CLK_OSC32K>, <&osc24M>, 1325*724ba675SRob Herring <&ccu CLK_PLL_PERIPH>, 1326*724ba675SRob Herring <&ccu CLK_PLL_PERIPH>; 1327*724ba675SRob Herring clock-output-names = "ar100"; 1328*724ba675SRob Herring }; 1329*724ba675SRob Herring 1330*724ba675SRob Herring ahb0: ahb0_clk { 1331*724ba675SRob Herring compatible = "fixed-factor-clock"; 1332*724ba675SRob Herring #clock-cells = <0>; 1333*724ba675SRob Herring clock-div = <1>; 1334*724ba675SRob Herring clock-mult = <1>; 1335*724ba675SRob Herring clocks = <&ar100>; 1336*724ba675SRob Herring clock-output-names = "ahb0"; 1337*724ba675SRob Herring }; 1338*724ba675SRob Herring 1339*724ba675SRob Herring apb0: apb0_clk { 1340*724ba675SRob Herring compatible = "allwinner,sun6i-a31-apb0-clk"; 1341*724ba675SRob Herring #clock-cells = <0>; 1342*724ba675SRob Herring clocks = <&ahb0>; 1343*724ba675SRob Herring clock-output-names = "apb0"; 1344*724ba675SRob Herring }; 1345*724ba675SRob Herring 1346*724ba675SRob Herring apb0_gates: apb0_gates_clk { 1347*724ba675SRob Herring compatible = "allwinner,sun6i-a31-apb0-gates-clk"; 1348*724ba675SRob Herring #clock-cells = <1>; 1349*724ba675SRob Herring clocks = <&apb0>; 1350*724ba675SRob Herring clock-output-names = "apb0_pio", "apb0_ir", 1351*724ba675SRob Herring "apb0_timer", "apb0_p2wi", 1352*724ba675SRob Herring "apb0_uart", "apb0_1wire", 1353*724ba675SRob Herring "apb0_i2c"; 1354*724ba675SRob Herring }; 1355*724ba675SRob Herring 1356*724ba675SRob Herring ir_clk: ir_clk { 1357*724ba675SRob Herring #clock-cells = <0>; 1358*724ba675SRob Herring compatible = "allwinner,sun4i-a10-mod0-clk"; 1359*724ba675SRob Herring clocks = <&rtc CLK_OSC32K>, <&osc24M>; 1360*724ba675SRob Herring clock-output-names = "ir"; 1361*724ba675SRob Herring }; 1362*724ba675SRob Herring 1363*724ba675SRob Herring apb0_rst: apb0_rst { 1364*724ba675SRob Herring compatible = "allwinner,sun6i-a31-clock-reset"; 1365*724ba675SRob Herring #reset-cells = <1>; 1366*724ba675SRob Herring }; 1367*724ba675SRob Herring }; 1368*724ba675SRob Herring 1369*724ba675SRob Herring cpucfg@1f01c00 { 1370*724ba675SRob Herring compatible = "allwinner,sun6i-a31-cpuconfig"; 1371*724ba675SRob Herring reg = <0x01f01c00 0x300>; 1372*724ba675SRob Herring }; 1373*724ba675SRob Herring 1374*724ba675SRob Herring ir: ir@1f02000 { 1375*724ba675SRob Herring compatible = "allwinner,sun6i-a31-ir"; 1376*724ba675SRob Herring clocks = <&apb0_gates 1>, <&ir_clk>; 1377*724ba675SRob Herring clock-names = "apb", "ir"; 1378*724ba675SRob Herring resets = <&apb0_rst 1>; 1379*724ba675SRob Herring interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1380*724ba675SRob Herring reg = <0x01f02000 0x40>; 1381*724ba675SRob Herring status = "disabled"; 1382*724ba675SRob Herring }; 1383*724ba675SRob Herring 1384*724ba675SRob Herring r_pio: pinctrl@1f02c00 { 1385*724ba675SRob Herring compatible = "allwinner,sun6i-a31-r-pinctrl"; 1386*724ba675SRob Herring reg = <0x01f02c00 0x400>; 1387*724ba675SRob Herring interrupt-parent = <&r_intc>; 1388*724ba675SRob Herring interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1389*724ba675SRob Herring <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1390*724ba675SRob Herring clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; 1391*724ba675SRob Herring clock-names = "apb", "hosc", "losc"; 1392*724ba675SRob Herring gpio-controller; 1393*724ba675SRob Herring interrupt-controller; 1394*724ba675SRob Herring #interrupt-cells = <3>; 1395*724ba675SRob Herring #gpio-cells = <3>; 1396*724ba675SRob Herring 1397*724ba675SRob Herring s_ir_rx_pin: s-ir-rx-pin { 1398*724ba675SRob Herring pins = "PL4"; 1399*724ba675SRob Herring function = "s_ir"; 1400*724ba675SRob Herring }; 1401*724ba675SRob Herring 1402*724ba675SRob Herring s_p2wi_pins: s-p2wi-pins { 1403*724ba675SRob Herring pins = "PL0", "PL1"; 1404*724ba675SRob Herring function = "s_p2wi"; 1405*724ba675SRob Herring }; 1406*724ba675SRob Herring }; 1407*724ba675SRob Herring 1408*724ba675SRob Herring p2wi: i2c@1f03400 { 1409*724ba675SRob Herring compatible = "allwinner,sun6i-a31-p2wi"; 1410*724ba675SRob Herring reg = <0x01f03400 0x400>; 1411*724ba675SRob Herring interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1412*724ba675SRob Herring clocks = <&apb0_gates 3>; 1413*724ba675SRob Herring clock-frequency = <100000>; 1414*724ba675SRob Herring resets = <&apb0_rst 3>; 1415*724ba675SRob Herring pinctrl-names = "default"; 1416*724ba675SRob Herring pinctrl-0 = <&s_p2wi_pins>; 1417*724ba675SRob Herring status = "disabled"; 1418*724ba675SRob Herring #address-cells = <1>; 1419*724ba675SRob Herring #size-cells = <0>; 1420*724ba675SRob Herring }; 1421*724ba675SRob Herring }; 1422*724ba675SRob Herring}; 1423