12924cd18SRuud Derwig/* 22924cd18SRuud Derwig * Support for peripherals on the AXS10x mainboard (VDK version) 32924cd18SRuud Derwig * 42924cd18SRuud Derwig * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 52924cd18SRuud Derwig * 62924cd18SRuud Derwig * This program is free software; you can redistribute it and/or modify 72924cd18SRuud Derwig * it under the terms of the GNU General Public License version 2 as 82924cd18SRuud Derwig * published by the Free Software Foundation. 92924cd18SRuud Derwig */ 102924cd18SRuud Derwig 112924cd18SRuud Derwig/ { 122924cd18SRuud Derwig axs10x_mb_vdk { 132924cd18SRuud Derwig compatible = "simple-bus"; 142924cd18SRuud Derwig #address-cells = <1>; 152924cd18SRuud Derwig #size-cells = <1>; 162924cd18SRuud Derwig ranges = <0x00000000 0xe0000000 0x10000000>; 172924cd18SRuud Derwig interrupt-parent = <&mb_intc>; 182924cd18SRuud Derwig 192924cd18SRuud Derwig clocks { 202924cd18SRuud Derwig apbclk: apbclk { 212924cd18SRuud Derwig compatible = "fixed-clock"; 222924cd18SRuud Derwig clock-frequency = <50000000>; 232924cd18SRuud Derwig #clock-cells = <0>; 242924cd18SRuud Derwig }; 252924cd18SRuud Derwig 26d9174e72SAlexey Brodkin mmcclk: mmcclk { 27d9174e72SAlexey Brodkin compatible = "fixed-clock"; 28d9174e72SAlexey Brodkin clock-frequency = <50000000>; 29d9174e72SAlexey Brodkin #clock-cells = <0>; 30d9174e72SAlexey Brodkin }; 31d9174e72SAlexey Brodkin 32c8f1daa8SAlexey Brodkin pguclk: pguclk { 33c8f1daa8SAlexey Brodkin #clock-cells = <0>; 34c8f1daa8SAlexey Brodkin compatible = "fixed-clock"; 35c8f1daa8SAlexey Brodkin clock-frequency = <25175000>; 36c8f1daa8SAlexey Brodkin }; 372924cd18SRuud Derwig }; 382924cd18SRuud Derwig 392924cd18SRuud Derwig ethernet@0x18000 { 402924cd18SRuud Derwig #interrupt-cells = <1>; 412924cd18SRuud Derwig compatible = "snps,dwmac"; 422924cd18SRuud Derwig reg = < 0x18000 0x2000 >; 432924cd18SRuud Derwig interrupts = < 4 >; 442924cd18SRuud Derwig interrupt-names = "macirq"; 452924cd18SRuud Derwig phy-mode = "rgmii"; 462924cd18SRuud Derwig snps,phy-addr = < 0 >; // VDK model phy address is 0 472924cd18SRuud Derwig snps,pbl = < 32 >; 482924cd18SRuud Derwig clocks = <&apbclk>; 492924cd18SRuud Derwig clock-names = "stmmaceth"; 502924cd18SRuud Derwig }; 512924cd18SRuud Derwig 522924cd18SRuud Derwig ehci@0x40000 { 532924cd18SRuud Derwig compatible = "generic-ehci"; 542924cd18SRuud Derwig reg = < 0x40000 0x100 >; 552924cd18SRuud Derwig interrupts = < 8 >; 562924cd18SRuud Derwig }; 572924cd18SRuud Derwig 582924cd18SRuud Derwig uart@0x20000 { 592924cd18SRuud Derwig compatible = "snps,dw-apb-uart"; 602924cd18SRuud Derwig reg = <0x20000 0x100>; 612924cd18SRuud Derwig clock-frequency = <2403200>; 622924cd18SRuud Derwig interrupts = <17>; 632924cd18SRuud Derwig baud = <115200>; 642924cd18SRuud Derwig reg-shift = <2>; 652924cd18SRuud Derwig reg-io-width = <4>; 662924cd18SRuud Derwig }; 672924cd18SRuud Derwig 682924cd18SRuud Derwig uart@0x21000 { 692924cd18SRuud Derwig compatible = "snps,dw-apb-uart"; 702924cd18SRuud Derwig reg = <0x21000 0x100>; 712924cd18SRuud Derwig clock-frequency = <2403200>; 722924cd18SRuud Derwig interrupts = <18>; 732924cd18SRuud Derwig baud = <115200>; 742924cd18SRuud Derwig reg-shift = <2>; 752924cd18SRuud Derwig reg-io-width = <4>; 762924cd18SRuud Derwig }; 772924cd18SRuud Derwig 782924cd18SRuud Derwig uart@0x22000 { 792924cd18SRuud Derwig compatible = "snps,dw-apb-uart"; 802924cd18SRuud Derwig reg = <0x22000 0x100>; 812924cd18SRuud Derwig clock-frequency = <2403200>; 822924cd18SRuud Derwig interrupts = <19>; 832924cd18SRuud Derwig baud = <115200>; 842924cd18SRuud Derwig reg-shift = <2>; 852924cd18SRuud Derwig reg-io-width = <4>; 862924cd18SRuud Derwig }; 872924cd18SRuud Derwig 882924cd18SRuud Derwig/* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */ 89c8f1daa8SAlexey Brodkin pgu@17000 { 90c8f1daa8SAlexey Brodkin compatible = "snps,arcpgu"; 912924cd18SRuud Derwig reg = <0x17000 0x400>; 92c8f1daa8SAlexey Brodkin clocks = <&pguclk>; 93c8f1daa8SAlexey Brodkin clock-names = "pxlclk"; 942924cd18SRuud Derwig }; 952924cd18SRuud Derwig 962924cd18SRuud Derwig/* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */ 972924cd18SRuud Derwig ps2: ps2@e0017400 { 982924cd18SRuud Derwig compatible = "snps,arc_ps2"; 992924cd18SRuud Derwig reg = <0x17400 0x14>; 1002924cd18SRuud Derwig interrupts = <5>; 1012924cd18SRuud Derwig interrupt-names = "arc_ps2_irq"; 1022924cd18SRuud Derwig }; 103d9174e72SAlexey Brodkin 104d9174e72SAlexey Brodkin mmc@0x15000 { 105d9174e72SAlexey Brodkin compatible = "snps,dw-mshc"; 106d9174e72SAlexey Brodkin reg = <0x15000 0x400>; 107d9174e72SAlexey Brodkin num-slots = <1>; 108d9174e72SAlexey Brodkin fifo-depth = <1024>; 109d9174e72SAlexey Brodkin card-detect-delay = <200>; 110d9174e72SAlexey Brodkin clocks = <&apbclk>, <&mmcclk>; 111d9174e72SAlexey Brodkin clock-names = "biu", "ciu"; 112d9174e72SAlexey Brodkin interrupts = <7>; 113d9174e72SAlexey Brodkin bus-width = <4>; 114d9174e72SAlexey Brodkin }; 115ae9955aeSAlexey Brodkin }; 116cf16bf77SAlexey Brodkin 117ae9955aeSAlexey Brodkin /* 118ae9955aeSAlexey Brodkin * Embedded Vision subsystem UIO mappings; only relevant for EV VDK 119ae9955aeSAlexey Brodkin * 120ae9955aeSAlexey Brodkin * This node is intentionally put outside of MB above becase 121ae9955aeSAlexey Brodkin * it maps areas outside of MB's 0xEz-0xFz. 122ae9955aeSAlexey Brodkin */ 123cf16bf77SAlexey Brodkin uio_ev: uio@0xD0000000 { 124cf16bf77SAlexey Brodkin compatible = "generic-uio"; 125cf16bf77SAlexey Brodkin reg = <0xD0000000 0x2000 0xD1000000 0x2000 0x90000000 0x10000000 0xC0000000 0x10000000>; 126cf16bf77SAlexey Brodkin reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem"; 127ae9955aeSAlexey Brodkin interrupt-parent = <&mb_intc>; 128cf16bf77SAlexey Brodkin interrupts = <23>; 129cf16bf77SAlexey Brodkin }; 1302924cd18SRuud Derwig}; 131