1/* 2 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* 10 * Device tree for AXC003 CPU card: 11 * HS38x2 (Dual Core) with IDU intc (VDK version) 12 */ 13 14/include/ "skeleton_hs_idu.dtsi" 15 16/ { 17 compatible = "snps,arc"; 18 clock-frequency = <50000000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 cpu_card { 23 compatible = "simple-bus"; 24 #address-cells = <1>; 25 #size-cells = <1>; 26 27 ranges = <0x00000000 0xf0000000 0x10000000>; 28 29 core_intc: archs-intc@cpu { 30 compatible = "snps,archs-intc"; 31 interrupt-controller; 32 #interrupt-cells = <1>; 33 }; 34 35 idu_intc: idu-interrupt-controller { 36 compatible = "snps,archs-idu-intc"; 37 interrupt-controller; 38 interrupt-parent = <&core_intc>; 39 40 /* 41 * <hwirq distribution> 42 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 43 */ 44 #interrupt-cells = <2>; 45 46 interrupts = <24 25 26 27>; 47 }; 48 49 debug_uart: dw-apb-uart@0x5000 { 50 compatible = "snps,dw-apb-uart"; 51 reg = <0x5000 0x100>; 52 clock-frequency = <2403200>; 53 interrupt-parent = <&idu_intc>; 54 interrupts = <2 0>; 55 baud = <115200>; 56 reg-shift = <2>; 57 reg-io-width = <4>; 58 }; 59 60 }; 61 62 mb_intc: dw-apb-ictl@0xe0012000 { 63 #interrupt-cells = <1>; 64 compatible = "snps,dw-apb-ictl"; 65 reg = < 0xe0012000 0x200 >; 66 interrupt-controller; 67 interrupt-parent = <&idu_intc>; 68 interrupts = < 0 0 >; 69 }; 70 71 memory { 72 #address-cells = <1>; 73 #size-cells = <1>; 74 ranges = <0x00000000 0x80000000 0x40000000>; 75 device_type = "memory"; 76 reg = <0x80000000 0x20000000>; /* 512MiB */ 77 }; 78}; 79