12924cd18SRuud Derwig/* 22924cd18SRuud Derwig * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com) 32924cd18SRuud Derwig * 42924cd18SRuud Derwig * This program is free software; you can redistribute it and/or modify 52924cd18SRuud Derwig * it under the terms of the GNU General Public License version 2 as 62924cd18SRuud Derwig * published by the Free Software Foundation. 72924cd18SRuud Derwig */ 82924cd18SRuud Derwig 92924cd18SRuud Derwig/* 102924cd18SRuud Derwig * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version) 112924cd18SRuud Derwig */ 122924cd18SRuud Derwig 132e8cd938SVineet Gupta/include/ "skeleton_hs.dtsi" 142e8cd938SVineet Gupta 152924cd18SRuud Derwig/ { 162924cd18SRuud Derwig compatible = "snps,arc"; 172924cd18SRuud Derwig clock-frequency = <50000000>; 182924cd18SRuud Derwig #address-cells = <1>; 192924cd18SRuud Derwig #size-cells = <1>; 202924cd18SRuud Derwig 212924cd18SRuud Derwig cpu_card { 222924cd18SRuud Derwig compatible = "simple-bus"; 232924cd18SRuud Derwig #address-cells = <1>; 242924cd18SRuud Derwig #size-cells = <1>; 252924cd18SRuud Derwig 262924cd18SRuud Derwig ranges = <0x00000000 0xf0000000 0x10000000>; 272924cd18SRuud Derwig 28b3d6aba8SVineet Gupta core_clk: core_clk { 29b3d6aba8SVineet Gupta #clock-cells = <0>; 30b3d6aba8SVineet Gupta compatible = "fixed-clock"; 31b3d6aba8SVineet Gupta clock-frequency = <50000000>; 32b3d6aba8SVineet Gupta }; 33b3d6aba8SVineet Gupta 349ba7648cSVineet Gupta core_intc: archs-intc@cpu { 352924cd18SRuud Derwig compatible = "snps,archs-intc"; 362924cd18SRuud Derwig interrupt-controller; 372924cd18SRuud Derwig #interrupt-cells = <1>; 382924cd18SRuud Derwig }; 392924cd18SRuud Derwig 402924cd18SRuud Derwig debug_uart: dw-apb-uart@0x5000 { 412924cd18SRuud Derwig compatible = "snps,dw-apb-uart"; 422924cd18SRuud Derwig reg = <0x5000 0x100>; 432924cd18SRuud Derwig clock-frequency = <2403200>; 449ba7648cSVineet Gupta interrupt-parent = <&core_intc>; 452924cd18SRuud Derwig interrupts = <19>; 462924cd18SRuud Derwig baud = <115200>; 472924cd18SRuud Derwig reg-shift = <2>; 482924cd18SRuud Derwig reg-io-width = <4>; 492924cd18SRuud Derwig }; 502924cd18SRuud Derwig 512924cd18SRuud Derwig }; 522924cd18SRuud Derwig 532924cd18SRuud Derwig mb_intc: dw-apb-ictl@0xe0012000 { 542924cd18SRuud Derwig #interrupt-cells = <1>; 552924cd18SRuud Derwig compatible = "snps,dw-apb-ictl"; 562924cd18SRuud Derwig reg = < 0xe0012000 0x200 >; 572924cd18SRuud Derwig interrupt-controller; 589ba7648cSVineet Gupta interrupt-parent = <&core_intc>; 592924cd18SRuud Derwig interrupts = < 18 >; 602924cd18SRuud Derwig }; 612924cd18SRuud Derwig 622924cd18SRuud Derwig memory { 632924cd18SRuud Derwig #address-cells = <1>; 642924cd18SRuud Derwig #size-cells = <1>; 652924cd18SRuud Derwig ranges = <0x00000000 0x80000000 0x40000000>; 662924cd18SRuud Derwig device_type = "memory"; 67f759ee57SVineet Gupta reg = <0x80000000 0x20000000>; /* 512MiB */ 682924cd18SRuud Derwig }; 692924cd18SRuud Derwig}; 70