12924cd18SRuud Derwig/*
22924cd18SRuud Derwig * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com)
32924cd18SRuud Derwig *
42924cd18SRuud Derwig * This program is free software; you can redistribute it and/or modify
52924cd18SRuud Derwig * it under the terms of the GNU General Public License version 2 as
62924cd18SRuud Derwig * published by the Free Software Foundation.
72924cd18SRuud Derwig */
82924cd18SRuud Derwig
92924cd18SRuud Derwig/*
102924cd18SRuud Derwig * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version)
112924cd18SRuud Derwig */
122924cd18SRuud Derwig
132e8cd938SVineet Gupta/include/ "skeleton_hs.dtsi"
142e8cd938SVineet Gupta
152924cd18SRuud Derwig/ {
162924cd18SRuud Derwig	compatible = "snps,arc";
172924cd18SRuud Derwig	clock-frequency = <50000000>;
182924cd18SRuud Derwig	#address-cells = <1>;
192924cd18SRuud Derwig	#size-cells = <1>;
202924cd18SRuud Derwig
212924cd18SRuud Derwig	cpu_card {
222924cd18SRuud Derwig		compatible = "simple-bus";
232924cd18SRuud Derwig		#address-cells = <1>;
242924cd18SRuud Derwig		#size-cells = <1>;
252924cd18SRuud Derwig
262924cd18SRuud Derwig		ranges = <0x00000000 0xf0000000 0x10000000>;
272924cd18SRuud Derwig
289ba7648cSVineet Gupta		core_intc: archs-intc@cpu {
292924cd18SRuud Derwig			compatible = "snps,archs-intc";
302924cd18SRuud Derwig			interrupt-controller;
312924cd18SRuud Derwig			#interrupt-cells = <1>;
322924cd18SRuud Derwig		};
332924cd18SRuud Derwig
342924cd18SRuud Derwig		debug_uart: dw-apb-uart@0x5000 {
352924cd18SRuud Derwig			compatible = "snps,dw-apb-uart";
362924cd18SRuud Derwig			reg = <0x5000 0x100>;
372924cd18SRuud Derwig			clock-frequency = <2403200>;
389ba7648cSVineet Gupta			interrupt-parent = <&core_intc>;
392924cd18SRuud Derwig			interrupts = <19>;
402924cd18SRuud Derwig			baud = <115200>;
412924cd18SRuud Derwig			reg-shift = <2>;
422924cd18SRuud Derwig			reg-io-width = <4>;
432924cd18SRuud Derwig		};
442924cd18SRuud Derwig
452924cd18SRuud Derwig	};
462924cd18SRuud Derwig
472924cd18SRuud Derwig	mb_intc: dw-apb-ictl@0xe0012000 {
482924cd18SRuud Derwig		#interrupt-cells = <1>;
492924cd18SRuud Derwig		compatible = "snps,dw-apb-ictl";
502924cd18SRuud Derwig		reg = < 0xe0012000 0x200 >;
512924cd18SRuud Derwig		interrupt-controller;
529ba7648cSVineet Gupta		interrupt-parent = <&core_intc>;
532924cd18SRuud Derwig		interrupts = < 18 >;
542924cd18SRuud Derwig	};
552924cd18SRuud Derwig
562924cd18SRuud Derwig	memory {
572924cd18SRuud Derwig		#address-cells = <1>;
582924cd18SRuud Derwig		#size-cells = <1>;
592924cd18SRuud Derwig		ranges = <0x00000000 0x80000000 0x40000000>;
602924cd18SRuud Derwig		device_type = "memory";
61f759ee57SVineet Gupta		reg = <0x80000000 0x20000000>;	/* 512MiB */
622924cd18SRuud Derwig	};
632924cd18SRuud Derwig};
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