12924cd18SRuud Derwig/*
22924cd18SRuud Derwig * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com)
32924cd18SRuud Derwig *
42924cd18SRuud Derwig * This program is free software; you can redistribute it and/or modify
52924cd18SRuud Derwig * it under the terms of the GNU General Public License version 2 as
62924cd18SRuud Derwig * published by the Free Software Foundation.
72924cd18SRuud Derwig */
82924cd18SRuud Derwig
92924cd18SRuud Derwig/*
102924cd18SRuud Derwig * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version)
112924cd18SRuud Derwig */
122924cd18SRuud Derwig
132924cd18SRuud Derwig/ {
142924cd18SRuud Derwig	compatible = "snps,arc";
152924cd18SRuud Derwig	clock-frequency = <50000000>;
162924cd18SRuud Derwig	#address-cells = <1>;
172924cd18SRuud Derwig	#size-cells = <1>;
182924cd18SRuud Derwig
192924cd18SRuud Derwig	cpu_card {
202924cd18SRuud Derwig		compatible = "simple-bus";
212924cd18SRuud Derwig		#address-cells = <1>;
222924cd18SRuud Derwig		#size-cells = <1>;
232924cd18SRuud Derwig
242924cd18SRuud Derwig		ranges = <0x00000000 0xf0000000 0x10000000>;
252924cd18SRuud Derwig
262924cd18SRuud Derwig		cpu_intc: archs-intc@cpu {
272924cd18SRuud Derwig			compatible = "snps,archs-intc";
282924cd18SRuud Derwig			interrupt-controller;
292924cd18SRuud Derwig			#interrupt-cells = <1>;
302924cd18SRuud Derwig		};
312924cd18SRuud Derwig
322924cd18SRuud Derwig		debug_uart: dw-apb-uart@0x5000 {
332924cd18SRuud Derwig			compatible = "snps,dw-apb-uart";
342924cd18SRuud Derwig			reg = <0x5000 0x100>;
352924cd18SRuud Derwig			clock-frequency = <2403200>;
362924cd18SRuud Derwig			interrupt-parent = <&cpu_intc>;
372924cd18SRuud Derwig			interrupts = <19>;
382924cd18SRuud Derwig			baud = <115200>;
392924cd18SRuud Derwig			reg-shift = <2>;
402924cd18SRuud Derwig			reg-io-width = <4>;
412924cd18SRuud Derwig		};
422924cd18SRuud Derwig
432924cd18SRuud Derwig	};
442924cd18SRuud Derwig
452924cd18SRuud Derwig	mb_intc: dw-apb-ictl@0xe0012000 {
462924cd18SRuud Derwig		#interrupt-cells = <1>;
472924cd18SRuud Derwig		compatible = "snps,dw-apb-ictl";
482924cd18SRuud Derwig		reg = < 0xe0012000 0x200 >;
492924cd18SRuud Derwig		interrupt-controller;
502924cd18SRuud Derwig		interrupt-parent = <&cpu_intc>;
512924cd18SRuud Derwig		interrupts = < 18 >;
522924cd18SRuud Derwig	};
532924cd18SRuud Derwig
542924cd18SRuud Derwig	memory {
552924cd18SRuud Derwig		#address-cells = <1>;
562924cd18SRuud Derwig		#size-cells = <1>;
572924cd18SRuud Derwig		ranges = <0x00000000 0x80000000 0x40000000>;
582924cd18SRuud Derwig		device_type = "memory";
592924cd18SRuud Derwig		reg = <0x00000000 0x20000000>;	/* 512MiB */
602924cd18SRuud Derwig	};
612924cd18SRuud Derwig};
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