1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only
22924cd18SRuud Derwig/*
32924cd18SRuud Derwig * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com)
42924cd18SRuud Derwig */
52924cd18SRuud Derwig
62924cd18SRuud Derwig/*
72924cd18SRuud Derwig * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version)
82924cd18SRuud Derwig */
92924cd18SRuud Derwig
102e8cd938SVineet Gupta/include/ "skeleton_hs.dtsi"
112e8cd938SVineet Gupta
122924cd18SRuud Derwig/ {
132924cd18SRuud Derwig	compatible = "snps,arc";
142924cd18SRuud Derwig	#address-cells = <1>;
152924cd18SRuud Derwig	#size-cells = <1>;
162924cd18SRuud Derwig
172924cd18SRuud Derwig	cpu_card {
182924cd18SRuud Derwig		compatible = "simple-bus";
192924cd18SRuud Derwig		#address-cells = <1>;
202924cd18SRuud Derwig		#size-cells = <1>;
212924cd18SRuud Derwig
222924cd18SRuud Derwig		ranges = <0x00000000 0xf0000000 0x10000000>;
232924cd18SRuud Derwig
24b3d6aba8SVineet Gupta		core_clk: core_clk {
25b3d6aba8SVineet Gupta			#clock-cells = <0>;
26b3d6aba8SVineet Gupta			compatible = "fixed-clock";
27b3d6aba8SVineet Gupta			clock-frequency = <50000000>;
28b3d6aba8SVineet Gupta		};
29b3d6aba8SVineet Gupta
309ba7648cSVineet Gupta		core_intc: archs-intc@cpu {
312924cd18SRuud Derwig			compatible = "snps,archs-intc";
322924cd18SRuud Derwig			interrupt-controller;
332924cd18SRuud Derwig			#interrupt-cells = <1>;
342924cd18SRuud Derwig		};
352924cd18SRuud Derwig
36ef4c54c3SAlexey Brodkin		debug_uart: dw-apb-uart@5000 {
372924cd18SRuud Derwig			compatible = "snps,dw-apb-uart";
382924cd18SRuud Derwig			reg = <0x5000 0x100>;
392924cd18SRuud Derwig			clock-frequency = <2403200>;
409ba7648cSVineet Gupta			interrupt-parent = <&core_intc>;
412924cd18SRuud Derwig			interrupts = <19>;
422924cd18SRuud Derwig			baud = <115200>;
432924cd18SRuud Derwig			reg-shift = <2>;
442924cd18SRuud Derwig			reg-io-width = <4>;
452924cd18SRuud Derwig		};
462924cd18SRuud Derwig
472924cd18SRuud Derwig	};
482924cd18SRuud Derwig
4905b1be68SZhen Lei	mb_intc: interrupt-controller@e0012000 {
502924cd18SRuud Derwig		#interrupt-cells = <1>;
512924cd18SRuud Derwig		compatible = "snps,dw-apb-ictl";
522924cd18SRuud Derwig		reg = < 0xe0012000 0x200 >;
532924cd18SRuud Derwig		interrupt-controller;
549ba7648cSVineet Gupta		interrupt-parent = <&core_intc>;
552924cd18SRuud Derwig		interrupts = < 18 >;
562924cd18SRuud Derwig	};
572924cd18SRuud Derwig
582924cd18SRuud Derwig	memory {
592924cd18SRuud Derwig		#address-cells = <1>;
602924cd18SRuud Derwig		#size-cells = <1>;
612924cd18SRuud Derwig		ranges = <0x00000000 0x80000000 0x40000000>;
622924cd18SRuud Derwig		device_type = "memory";
63f759ee57SVineet Gupta		reg = <0x80000000 0x20000000>;	/* 512MiB */
642924cd18SRuud Derwig	};
652924cd18SRuud Derwig};
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