1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 2999159a5SVineet Gupta/* 3999159a5SVineet Gupta * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com) 4999159a5SVineet Gupta */ 5999159a5SVineet Gupta 6999159a5SVineet Gupta/* 7999159a5SVineet Gupta * Skeleton device tree; the bare minimum needed to boot; just include and 8999159a5SVineet Gupta * add a compatible value. 9999159a5SVineet Gupta */ 10999159a5SVineet Gupta 11999159a5SVineet Gupta/ { 12999159a5SVineet Gupta compatible = "snps,arc"; 13999159a5SVineet Gupta #address-cells = <1>; 14999159a5SVineet Gupta #size-cells = <1>; 15999159a5SVineet Gupta chosen { }; 16999159a5SVineet Gupta aliases { }; 17abe11ddeSVineet Gupta 18abe11ddeSVineet Gupta cpus { 19abe11ddeSVineet Gupta #address-cells = <1>; 20abe11ddeSVineet Gupta #size-cells = <0>; 21abe11ddeSVineet Gupta 22abe11ddeSVineet Gupta cpu@0 { 23abe11ddeSVineet Gupta device_type = "cpu"; 24abe11ddeSVineet Gupta compatible = "snps,arc770d"; 25abe11ddeSVineet Gupta reg = <0>; 26854c11e2SVlad Zakharov clocks = <&core_clk>; 27abe11ddeSVineet Gupta }; 28abe11ddeSVineet Gupta }; 29abe11ddeSVineet Gupta 307ec9f34aSVineet Gupta /* TIMER0 with interrupt for clockevent */ 317ec9f34aSVineet Gupta timer0 { 327ec9f34aSVineet Gupta compatible = "snps,arc-timer"; 337ec9f34aSVineet Gupta interrupts = <3>; 347ec9f34aSVineet Gupta interrupt-parent = <&core_intc>; 357ec9f34aSVineet Gupta clocks = <&core_clk>; 367ec9f34aSVineet Gupta }; 377ec9f34aSVineet Gupta 387ec9f34aSVineet Gupta /* TIMER1 for free running clocksource */ 397ec9f34aSVineet Gupta timer1 { 407ec9f34aSVineet Gupta compatible = "snps,arc-timer"; 417ec9f34aSVineet Gupta clocks = <&core_clk>; 427ec9f34aSVineet Gupta }; 437ec9f34aSVineet Gupta 44450dd430SVineet Gupta memory { 45450dd430SVineet Gupta device_type = "memory"; 46f759ee57SVineet Gupta reg = <0x80000000 0x10000000>; /* 256M */ 47450dd430SVineet Gupta }; 48999159a5SVineet Gupta}; 49