1/*
2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "skeleton.dtsi"
11
12/ {
13	compatible = "snps,nsimosci_hs";
14	clock-frequency = <5000000>;	/* 5 MHZ */
15	#address-cells = <1>;
16	#size-cells = <1>;
17	interrupt-parent = <&core_intc>;
18
19	chosen {
20		/* this is for console on serial */
21		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug";
22	};
23
24	aliases {
25		serial0 = &uart0;
26	};
27
28	fpga {
29		compatible = "simple-bus";
30		#address-cells = <1>;
31		#size-cells = <1>;
32
33		/* child and parent address space 1:1 mapped */
34		ranges;
35
36		core_intc: core-interrupt-controller {
37			compatible = "snps,archs-intc";
38			interrupt-controller;
39			#interrupt-cells = <1>;
40/*			interrupts = <16 17 18 19 20 21 22 23 24 25>; */
41		};
42
43		idu_intc: idu-interrupt-controller {
44			compatible = "snps,archs-idu-intc";
45			interrupt-controller;
46			interrupt-parent = <&core_intc>;
47
48			/*
49			 * <hwirq  distribution>
50			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
51			 */
52			#interrupt-cells = <2>;
53
54			/*
55			 * upstream irqs to core intc - downstream these are
56			 * "COMMON" irq 0,1..
57			 */
58			interrupts = <24 25 26 27 28 29 30 31>;
59		};
60
61		uart0: serial@f0000000 {
62			compatible = "ns8250";
63			reg = <0xf0000000 0x2000>;
64			interrupt-parent = <&idu_intc>;
65			interrupts = <0 0>; /* cmn irq 0 -> cpu irq 24
66						RR distribute to all cpus */
67			clock-frequency = <3686400>;
68			baud = <115200>;
69			reg-shift = <2>;
70			reg-io-width = <4>;
71			no-loopback-test = <1>;
72		};
73
74		pgu0: pgu@f9000000 {
75			compatible = "snps,arcpgufb";
76			reg = <0xf9000000 0x400>;
77		};
78
79		ps2: ps2@f9001000 {
80			compatible = "snps,arc_ps2";
81			reg = <0xf9000400 0x14>;
82			interrupts = <3 0>;
83			interrupt-parent = <&idu_intc>;
84			interrupt-names = "arc_ps2_irq";
85		};
86
87		eth0: ethernet@f0003000 {
88			compatible = "snps,oscilan";
89			reg = <0xf0003000 0x44>;
90			interrupt-parent = <&idu_intc>;
91			interrupts = <1 2>, <2 2>;
92			interrupt-names = "rx", "tx";
93		};
94
95		arcpct0: pct {
96			compatible = "snps,archs-pct";
97			#interrupt-cells = <1>;
98			interrupts = <20>;
99		};
100	};
101};
102