1a12ebe16SVineet Gupta/*
2a12ebe16SVineet Gupta * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
3a12ebe16SVineet Gupta *
4a12ebe16SVineet Gupta * This program is free software; you can redistribute it and/or modify
5a12ebe16SVineet Gupta * it under the terms of the GNU General Public License version 2 as
6a12ebe16SVineet Gupta * published by the Free Software Foundation.
7a12ebe16SVineet Gupta */
8a12ebe16SVineet Gupta/dts-v1/;
9a12ebe16SVineet Gupta
10a12ebe16SVineet Gupta/include/ "skeleton.dtsi"
11a12ebe16SVineet Gupta
12a12ebe16SVineet Gupta/ {
13a12ebe16SVineet Gupta	compatible = "snps,nsimosci_hs";
14a12ebe16SVineet Gupta	clock-frequency = <20000000>;	/* 20 MHZ */
15a12ebe16SVineet Gupta	#address-cells = <1>;
16a12ebe16SVineet Gupta	#size-cells = <1>;
17a12ebe16SVineet Gupta	interrupt-parent = <&core_intc>;
18a12ebe16SVineet Gupta
19a12ebe16SVineet Gupta	chosen {
20a12ebe16SVineet Gupta		/* this is for console on PGU */
21a12ebe16SVineet Gupta		/* bootargs = "console=tty0 consoleblank=0"; */
22a12ebe16SVineet Gupta		/* this is for console on serial */
23a12ebe16SVineet Gupta		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug";
24a12ebe16SVineet Gupta	};
25a12ebe16SVineet Gupta
26a12ebe16SVineet Gupta	aliases {
27a12ebe16SVineet Gupta		serial0 = &uart0;
28a12ebe16SVineet Gupta	};
29a12ebe16SVineet Gupta
30a12ebe16SVineet Gupta	fpga {
31a12ebe16SVineet Gupta		compatible = "simple-bus";
32a12ebe16SVineet Gupta		#address-cells = <1>;
33a12ebe16SVineet Gupta		#size-cells = <1>;
34a12ebe16SVineet Gupta
35a12ebe16SVineet Gupta		/* child and parent address space 1:1 mapped */
36a12ebe16SVineet Gupta		ranges;
37a12ebe16SVineet Gupta
38a12ebe16SVineet Gupta		core_intc: core-interrupt-controller {
39a12ebe16SVineet Gupta			compatible = "snps,archs-intc";
40a12ebe16SVineet Gupta			interrupt-controller;
41a12ebe16SVineet Gupta			#interrupt-cells = <1>;
42a12ebe16SVineet Gupta		};
43a12ebe16SVineet Gupta
44a12ebe16SVineet Gupta		uart0: serial@f0000000 {
45a12ebe16SVineet Gupta			compatible = "ns8250";
46a12ebe16SVineet Gupta			reg = <0xf0000000 0x2000>;
47a12ebe16SVineet Gupta			interrupts = <24>;
48a12ebe16SVineet Gupta			clock-frequency = <3686400>;
49a12ebe16SVineet Gupta			baud = <115200>;
50a12ebe16SVineet Gupta			reg-shift = <2>;
51a12ebe16SVineet Gupta			reg-io-width = <4>;
52a12ebe16SVineet Gupta			no-loopback-test = <1>;
53a12ebe16SVineet Gupta		};
54a12ebe16SVineet Gupta
55a12ebe16SVineet Gupta		pgu0: pgu@f9000000 {
56a12ebe16SVineet Gupta			compatible = "snps,arcpgufb";
57a12ebe16SVineet Gupta			reg = <0xf9000000 0x400>;
58a12ebe16SVineet Gupta		};
59a12ebe16SVineet Gupta
60a12ebe16SVineet Gupta		ps2: ps2@f9001000 {
61a12ebe16SVineet Gupta			compatible = "snps,arc_ps2";
62a12ebe16SVineet Gupta			reg = <0xf9000400 0x14>;
63a12ebe16SVineet Gupta			interrupts = <27>;
64a12ebe16SVineet Gupta			interrupt-names = "arc_ps2_irq";
65a12ebe16SVineet Gupta		};
66a12ebe16SVineet Gupta
67a12ebe16SVineet Gupta		eth0: ethernet@f0003000 {
68df420fd6SLada Trimasova			compatible = "ezchip,nps-mgt-enet";
69a12ebe16SVineet Gupta			reg = <0xf0003000 0x44>;
70df420fd6SLada Trimasova			interrupts = <25>;
71a12ebe16SVineet Gupta		};
72a12ebe16SVineet Gupta
73a12ebe16SVineet Gupta		arcpct0: pct {
74a12ebe16SVineet Gupta			compatible = "snps,archs-pct";
75a12ebe16SVineet Gupta			#interrupt-cells = <1>;
76a12ebe16SVineet Gupta			interrupts = <20>;
77a12ebe16SVineet Gupta		};
78a12ebe16SVineet Gupta	};
79a12ebe16SVineet Gupta};
80