1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 2a12ebe16SVineet Gupta/* 3a12ebe16SVineet Gupta * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) 4a12ebe16SVineet Gupta */ 5a12ebe16SVineet Gupta/dts-v1/; 6a12ebe16SVineet Gupta 72e8cd938SVineet Gupta/include/ "skeleton_hs.dtsi" 8a12ebe16SVineet Gupta 9a12ebe16SVineet Gupta/ { 10618a9cd0SAlexey Brodkin model = "snps,nsimosci_hs"; 11a12ebe16SVineet Gupta compatible = "snps,nsimosci_hs"; 12a12ebe16SVineet Gupta #address-cells = <1>; 13a12ebe16SVineet Gupta #size-cells = <1>; 14a12ebe16SVineet Gupta interrupt-parent = <&core_intc>; 15a12ebe16SVineet Gupta 16a12ebe16SVineet Gupta chosen { 17a12ebe16SVineet Gupta /* this is for console on PGU */ 18a12ebe16SVineet Gupta /* bootargs = "console=tty0 consoleblank=0"; */ 19a12ebe16SVineet Gupta /* this is for console on serial */ 208ff3afc1SAlexey Brodkin bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1"; 21a12ebe16SVineet Gupta }; 22a12ebe16SVineet Gupta 23a12ebe16SVineet Gupta aliases { 24a12ebe16SVineet Gupta serial0 = &uart0; 25a12ebe16SVineet Gupta }; 26a12ebe16SVineet Gupta 27a12ebe16SVineet Gupta fpga { 28a12ebe16SVineet Gupta compatible = "simple-bus"; 29a12ebe16SVineet Gupta #address-cells = <1>; 30a12ebe16SVineet Gupta #size-cells = <1>; 31a12ebe16SVineet Gupta 32a12ebe16SVineet Gupta /* child and parent address space 1:1 mapped */ 33a12ebe16SVineet Gupta ranges; 34a12ebe16SVineet Gupta 35b3d6aba8SVineet Gupta core_clk: core_clk { 36b3d6aba8SVineet Gupta #clock-cells = <0>; 37b3d6aba8SVineet Gupta compatible = "fixed-clock"; 38b3d6aba8SVineet Gupta clock-frequency = <20000000>; 39b3d6aba8SVineet Gupta }; 40b3d6aba8SVineet Gupta 41a12ebe16SVineet Gupta core_intc: core-interrupt-controller { 42a12ebe16SVineet Gupta compatible = "snps,archs-intc"; 43a12ebe16SVineet Gupta interrupt-controller; 44a12ebe16SVineet Gupta #interrupt-cells = <1>; 45a12ebe16SVineet Gupta }; 46a12ebe16SVineet Gupta 47a12ebe16SVineet Gupta uart0: serial@f0000000 { 48a12ebe16SVineet Gupta compatible = "ns8250"; 49a12ebe16SVineet Gupta reg = <0xf0000000 0x2000>; 50a12ebe16SVineet Gupta interrupts = <24>; 51a12ebe16SVineet Gupta clock-frequency = <3686400>; 52a12ebe16SVineet Gupta baud = <115200>; 53a12ebe16SVineet Gupta reg-shift = <2>; 54a12ebe16SVineet Gupta reg-io-width = <4>; 55a12ebe16SVineet Gupta no-loopback-test = <1>; 56a12ebe16SVineet Gupta }; 57a12ebe16SVineet Gupta 58830c6578SAlexey Brodkin pguclk: pguclk { 59830c6578SAlexey Brodkin #clock-cells = <0>; 60830c6578SAlexey Brodkin compatible = "fixed-clock"; 61830c6578SAlexey Brodkin clock-frequency = <25175000>; 62830c6578SAlexey Brodkin }; 63830c6578SAlexey Brodkin 64830c6578SAlexey Brodkin pgu@f9000000 { 65830c6578SAlexey Brodkin compatible = "snps,arcpgu"; 66a12ebe16SVineet Gupta reg = <0xf9000000 0x400>; 67830c6578SAlexey Brodkin clocks = <&pguclk>; 68830c6578SAlexey Brodkin clock-names = "pxlclk"; 69a12ebe16SVineet Gupta }; 70a12ebe16SVineet Gupta 71a12ebe16SVineet Gupta ps2: ps2@f9001000 { 72a12ebe16SVineet Gupta compatible = "snps,arc_ps2"; 73a12ebe16SVineet Gupta reg = <0xf9000400 0x14>; 74a12ebe16SVineet Gupta interrupts = <27>; 75a12ebe16SVineet Gupta interrupt-names = "arc_ps2_irq"; 76a12ebe16SVineet Gupta }; 77a12ebe16SVineet Gupta 78a12ebe16SVineet Gupta eth0: ethernet@f0003000 { 79df420fd6SLada Trimasova compatible = "ezchip,nps-mgt-enet"; 80a12ebe16SVineet Gupta reg = <0xf0003000 0x44>; 81df420fd6SLada Trimasova interrupts = <25>; 82a12ebe16SVineet Gupta }; 83a12ebe16SVineet Gupta 84a12ebe16SVineet Gupta arcpct0: pct { 85a12ebe16SVineet Gupta compatible = "snps,archs-pct"; 86a12ebe16SVineet Gupta #interrupt-cells = <1>; 87a12ebe16SVineet Gupta interrupts = <20>; 88a12ebe16SVineet Gupta }; 89a12ebe16SVineet Gupta }; 90a12ebe16SVineet Gupta}; 91