14988cc56SVineet Gupta/* 24988cc56SVineet Gupta * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) 34988cc56SVineet Gupta * 44988cc56SVineet Gupta * This program is free software; you can redistribute it and/or modify 54988cc56SVineet Gupta * it under the terms of the GNU General Public License version 2 as 64988cc56SVineet Gupta * published by the Free Software Foundation. 74988cc56SVineet Gupta */ 84988cc56SVineet Gupta/dts-v1/; 94988cc56SVineet Gupta 104988cc56SVineet Gupta/include/ "skeleton_hs.dtsi" 114988cc56SVineet Gupta 124988cc56SVineet Gupta/ { 134988cc56SVineet Gupta model = "snps,zebu_hs"; 144988cc56SVineet Gupta compatible = "snps,zebu_hs"; 154988cc56SVineet Gupta #address-cells = <1>; 164988cc56SVineet Gupta #size-cells = <1>; 174988cc56SVineet Gupta interrupt-parent = <&core_intc>; 184988cc56SVineet Gupta 194988cc56SVineet Gupta memory { 204988cc56SVineet Gupta device_type = "memory"; 214988cc56SVineet Gupta reg = <0x80000000 0x20000000>; /* 512 */ 224988cc56SVineet Gupta }; 234988cc56SVineet Gupta 244988cc56SVineet Gupta chosen { 254988cc56SVineet Gupta bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 264988cc56SVineet Gupta }; 274988cc56SVineet Gupta 284988cc56SVineet Gupta aliases { 294988cc56SVineet Gupta serial0 = &uart0; 304988cc56SVineet Gupta }; 314988cc56SVineet Gupta 324988cc56SVineet Gupta fpga { 334988cc56SVineet Gupta compatible = "simple-bus"; 344988cc56SVineet Gupta #address-cells = <1>; 354988cc56SVineet Gupta #size-cells = <1>; 364988cc56SVineet Gupta 374988cc56SVineet Gupta /* child and parent address space 1:1 mapped */ 384988cc56SVineet Gupta ranges; 394988cc56SVineet Gupta 404988cc56SVineet Gupta core_clk: core_clk { 414988cc56SVineet Gupta #clock-cells = <0>; 424988cc56SVineet Gupta compatible = "fixed-clock"; 434988cc56SVineet Gupta clock-frequency = <50000000>; 444988cc56SVineet Gupta }; 454988cc56SVineet Gupta 464988cc56SVineet Gupta core_intc: interrupt-controller { 474988cc56SVineet Gupta compatible = "snps,archs-intc"; 484988cc56SVineet Gupta interrupt-controller; 494988cc56SVineet Gupta #interrupt-cells = <1>; 504988cc56SVineet Gupta }; 514988cc56SVineet Gupta 524988cc56SVineet Gupta uart0: serial@f0000000 { 534988cc56SVineet Gupta compatible = "ns8250"; 544988cc56SVineet Gupta reg = <0xf0000000 0x2000>; 554988cc56SVineet Gupta interrupts = <24>; 564988cc56SVineet Gupta clock-frequency = <50000000>; 574988cc56SVineet Gupta baud = <115200>; 584988cc56SVineet Gupta reg-shift = <2>; 594988cc56SVineet Gupta reg-io-width = <4>; 604988cc56SVineet Gupta no-loopback-test = <1>; 614988cc56SVineet Gupta }; 624988cc56SVineet Gupta 634988cc56SVineet Gupta arcpct0: pct { 644988cc56SVineet Gupta compatible = "snps,archs-pct"; 654988cc56SVineet Gupta #interrupt-cells = <1>; 664988cc56SVineet Gupta interrupts = <20>; 674988cc56SVineet Gupta }; 684988cc56SVineet Gupta }; 694988cc56SVineet Gupta}; 70