1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 24988cc56SVineet Gupta/* 34988cc56SVineet Gupta * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com) 44988cc56SVineet Gupta */ 54988cc56SVineet Gupta/dts-v1/; 64988cc56SVineet Gupta 74988cc56SVineet Gupta/include/ "skeleton_hs.dtsi" 84988cc56SVineet Gupta 94988cc56SVineet Gupta/ { 104988cc56SVineet Gupta model = "snps,zebu_hs"; 114988cc56SVineet Gupta compatible = "snps,zebu_hs"; 124988cc56SVineet Gupta #address-cells = <1>; 134988cc56SVineet Gupta #size-cells = <1>; 144988cc56SVineet Gupta interrupt-parent = <&core_intc>; 154988cc56SVineet Gupta 164988cc56SVineet Gupta memory { 174988cc56SVineet Gupta device_type = "memory"; 184988cc56SVineet Gupta reg = <0x80000000 0x20000000>; /* 512 */ 194988cc56SVineet Gupta }; 204988cc56SVineet Gupta 214988cc56SVineet Gupta chosen { 224988cc56SVineet Gupta bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 234988cc56SVineet Gupta }; 244988cc56SVineet Gupta 254988cc56SVineet Gupta aliases { 264988cc56SVineet Gupta serial0 = &uart0; 274988cc56SVineet Gupta }; 284988cc56SVineet Gupta 294988cc56SVineet Gupta fpga { 304988cc56SVineet Gupta compatible = "simple-bus"; 314988cc56SVineet Gupta #address-cells = <1>; 324988cc56SVineet Gupta #size-cells = <1>; 334988cc56SVineet Gupta 344988cc56SVineet Gupta /* child and parent address space 1:1 mapped */ 354988cc56SVineet Gupta ranges; 364988cc56SVineet Gupta 374988cc56SVineet Gupta core_clk: core_clk { 384988cc56SVineet Gupta #clock-cells = <0>; 394988cc56SVineet Gupta compatible = "fixed-clock"; 404988cc56SVineet Gupta clock-frequency = <50000000>; 414988cc56SVineet Gupta }; 424988cc56SVineet Gupta 434988cc56SVineet Gupta core_intc: interrupt-controller { 444988cc56SVineet Gupta compatible = "snps,archs-intc"; 454988cc56SVineet Gupta interrupt-controller; 464988cc56SVineet Gupta #interrupt-cells = <1>; 474988cc56SVineet Gupta }; 484988cc56SVineet Gupta 494988cc56SVineet Gupta uart0: serial@f0000000 { 503696fc97SEugeniy Paltsev compatible = "ns16550a"; 514988cc56SVineet Gupta reg = <0xf0000000 0x2000>; 524988cc56SVineet Gupta interrupts = <24>; 534988cc56SVineet Gupta clock-frequency = <50000000>; 544988cc56SVineet Gupta baud = <115200>; 554988cc56SVineet Gupta reg-shift = <2>; 564988cc56SVineet Gupta reg-io-width = <4>; 574988cc56SVineet Gupta no-loopback-test = <1>; 584988cc56SVineet Gupta }; 594988cc56SVineet Gupta 604988cc56SVineet Gupta arcpct0: pct { 614988cc56SVineet Gupta compatible = "snps,archs-pct"; 624988cc56SVineet Gupta #interrupt-cells = <1>; 634988cc56SVineet Gupta interrupts = <20>; 644988cc56SVineet Gupta }; 6594b8beb9SAlexey Brodkin 6694b8beb9SAlexey Brodkin virtio0: virtio@f0100000 { 6794b8beb9SAlexey Brodkin compatible = "virtio,mmio"; 6894b8beb9SAlexey Brodkin reg = <0xf0100000 0x2000>; 6994b8beb9SAlexey Brodkin interrupts = <31>; 7094b8beb9SAlexey Brodkin }; 7194b8beb9SAlexey Brodkin 7294b8beb9SAlexey Brodkin virtio1: virtio@f0102000 { 7394b8beb9SAlexey Brodkin compatible = "virtio,mmio"; 7494b8beb9SAlexey Brodkin reg = <0xf0102000 0x2000>; 7594b8beb9SAlexey Brodkin interrupts = <32>; 7694b8beb9SAlexey Brodkin }; 7794b8beb9SAlexey Brodkin 7894b8beb9SAlexey Brodkin virtio2: virtio@f0104000 { 7994b8beb9SAlexey Brodkin compatible = "virtio,mmio"; 8094b8beb9SAlexey Brodkin reg = <0xf0104000 0x2000>; 8194b8beb9SAlexey Brodkin interrupts = <33>; 8294b8beb9SAlexey Brodkin }; 8394b8beb9SAlexey Brodkin 8494b8beb9SAlexey Brodkin virtio3: virtio@f0106000 { 8594b8beb9SAlexey Brodkin compatible = "virtio,mmio"; 8694b8beb9SAlexey Brodkin reg = <0xf0106000 0x2000>; 8794b8beb9SAlexey Brodkin interrupts = <34>; 8894b8beb9SAlexey Brodkin }; 8994b8beb9SAlexey Brodkin 9094b8beb9SAlexey Brodkin virtio4: virtio@f0108000 { 9194b8beb9SAlexey Brodkin compatible = "virtio,mmio"; 9294b8beb9SAlexey Brodkin reg = <0xf0108000 0x2000>; 9394b8beb9SAlexey Brodkin interrupts = <35>; 9494b8beb9SAlexey Brodkin }; 954988cc56SVineet Gupta }; 964988cc56SVineet Gupta}; 97