1/* 2 * Support for peripherals on the AXS10x mainboard 3 * 4 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11/ { 12 axs10x_mb { 13 compatible = "simple-bus"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 ranges = <0x00000000 0xe0000000 0x10000000>; 17 interrupt-parent = <&mb_intc>; 18 19 i2sclk: i2sclk@100a0 { 20 compatible = "snps,axs10x-i2s-pll-clock"; 21 reg = <0x100a0 0x10>; 22 clocks = <&i2spll_clk>; 23 #clock-cells = <0>; 24 }; 25 26 clocks { 27 i2spll_clk: i2spll_clk { 28 compatible = "fixed-clock"; 29 clock-frequency = <27000000>; 30 #clock-cells = <0>; 31 }; 32 33 i2cclk: i2cclk { 34 compatible = "fixed-clock"; 35 clock-frequency = <50000000>; 36 #clock-cells = <0>; 37 }; 38 39 apbclk: apbclk { 40 compatible = "fixed-clock"; 41 clock-frequency = <50000000>; 42 #clock-cells = <0>; 43 }; 44 45 mmcclk: mmcclk { 46 compatible = "fixed-clock"; 47 clock-frequency = <50000000>; 48 #clock-cells = <0>; 49 }; 50 }; 51 52 ethernet@0x18000 { 53 #interrupt-cells = <1>; 54 compatible = "snps,dwmac"; 55 reg = < 0x18000 0x2000 >; 56 interrupts = < 4 >; 57 interrupt-names = "macirq"; 58 phy-mode = "rgmii"; 59 snps,pbl = < 32 >; 60 clocks = <&apbclk>; 61 clock-names = "stmmaceth"; 62 max-speed = <100>; 63 }; 64 65 ehci@0x40000 { 66 compatible = "generic-ehci"; 67 reg = < 0x40000 0x100 >; 68 interrupts = < 8 >; 69 }; 70 71 ohci@0x60000 { 72 compatible = "generic-ohci"; 73 reg = < 0x60000 0x100 >; 74 interrupts = < 8 >; 75 }; 76 77 /* 78 * According to DW Mobile Storage databook it is required 79 * to use "Hold Register" if card is enumerated in SDR12 or 80 * SDR25 modes. 81 * 82 * Utilization of "Hold Register" is already implemented via 83 * dw_mci_pltfm_prepare_command() which in its turn gets 84 * used through dw_mci_drv_data->prepare_command call-back. 85 * This call-back is used in Altera Socfpga platform and so 86 * we may reuse it saying that we're compatible with their 87 * "altr,socfpga-dw-mshc". 88 * 89 * Most probably "Hold Register" utilization is platform- 90 * independent requirement which means that single unified 91 * "snps,dw-mshc" should be enough for all users of DW MMC once 92 * dw_mci_pltfm_prepare_command() is used in generic platform 93 * code. 94 */ 95 mmc@0x15000 { 96 compatible = "altr,socfpga-dw-mshc"; 97 reg = < 0x15000 0x400 >; 98 num-slots = < 1 >; 99 fifo-depth = < 16 >; 100 card-detect-delay = < 200 >; 101 clocks = <&apbclk>, <&mmcclk>; 102 clock-names = "biu", "ciu"; 103 interrupts = < 7 >; 104 bus-width = < 4 >; 105 }; 106 107 uart@0x20000 { 108 compatible = "snps,dw-apb-uart"; 109 reg = <0x20000 0x100>; 110 clock-frequency = <33333333>; 111 interrupts = <17>; 112 baud = <115200>; 113 reg-shift = <2>; 114 reg-io-width = <4>; 115 }; 116 117 uart@0x21000 { 118 compatible = "snps,dw-apb-uart"; 119 reg = <0x21000 0x100>; 120 clock-frequency = <33333333>; 121 interrupts = <18>; 122 baud = <115200>; 123 reg-shift = <2>; 124 reg-io-width = <4>; 125 }; 126 127 /* UART muxed with USB data port (ttyS3) */ 128 uart@0x22000 { 129 compatible = "snps,dw-apb-uart"; 130 reg = <0x22000 0x100>; 131 clock-frequency = <33333333>; 132 interrupts = <19>; 133 baud = <115200>; 134 reg-shift = <2>; 135 reg-io-width = <4>; 136 }; 137 138 i2c@0x1d000 { 139 compatible = "snps,designware-i2c"; 140 reg = <0x1d000 0x100>; 141 clock-frequency = <400000>; 142 clocks = <&i2cclk>; 143 interrupts = <14>; 144 }; 145 146 i2c@0x1e000 { 147 compatible = "snps,designware-i2c"; 148 reg = <0x1e000 0x100>; 149 clock-frequency = <400000>; 150 clocks = <&i2cclk>; 151 interrupts = <15>; 152 }; 153 154 i2c@0x1f000 { 155 compatible = "snps,designware-i2c"; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 reg = <0x1f000 0x100>; 159 clock-frequency = <400000>; 160 clocks = <&i2cclk>; 161 interrupts = <16>; 162 163 eeprom@0x54{ 164 compatible = "24c01"; 165 reg = <0x54>; 166 pagesize = <0x8>; 167 }; 168 169 eeprom@0x57{ 170 compatible = "24c04"; 171 reg = <0x57>; 172 pagesize = <0x8>; 173 }; 174 }; 175 176 gpio0:gpio@13000 { 177 compatible = "snps,dw-apb-gpio"; 178 reg = <0x13000 0x1000>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 182 gpio0_banka: gpio-controller@0 { 183 compatible = "snps,dw-apb-gpio-port"; 184 gpio-controller; 185 #gpio-cells = <2>; 186 snps,nr-gpios = <32>; 187 reg = <0>; 188 }; 189 190 gpio0_bankb: gpio-controller@1 { 191 compatible = "snps,dw-apb-gpio-port"; 192 gpio-controller; 193 #gpio-cells = <2>; 194 snps,nr-gpios = <8>; 195 reg = <1>; 196 }; 197 198 gpio0_bankc: gpio-controller@2 { 199 compatible = "snps,dw-apb-gpio-port"; 200 gpio-controller; 201 #gpio-cells = <2>; 202 snps,nr-gpios = <8>; 203 reg = <2>; 204 }; 205 }; 206 207 gpio1:gpio@14000 { 208 compatible = "snps,dw-apb-gpio"; 209 reg = <0x14000 0x1000>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 213 gpio1_banka: gpio-controller@0 { 214 compatible = "snps,dw-apb-gpio-port"; 215 gpio-controller; 216 #gpio-cells = <2>; 217 snps,nr-gpios = <30>; 218 reg = <0>; 219 }; 220 221 gpio1_bankb: gpio-controller@1 { 222 compatible = "snps,dw-apb-gpio-port"; 223 gpio-controller; 224 #gpio-cells = <2>; 225 snps,nr-gpios = <10>; 226 reg = <1>; 227 }; 228 229 gpio1_bankc: gpio-controller@2 { 230 compatible = "snps,dw-apb-gpio-port"; 231 gpio-controller; 232 #gpio-cells = <2>; 233 snps,nr-gpios = <8>; 234 reg = <2>; 235 }; 236 }; 237 }; 238}; 239