1/*
2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Device tree for AXC003 CPU card: HS38x UP configuration
11 */
12
13/include/ "skeleton_hs.dtsi"
14
15/ {
16	compatible = "snps,arc";
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	cpu_card {
21		compatible = "simple-bus";
22		#address-cells = <1>;
23		#size-cells = <1>;
24
25		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
26
27		input_clk: input-clk {
28			#clock-cells = <0>;
29			compatible = "fixed-clock";
30			clock-frequency = <33333333>;
31		};
32
33		core_clk: core-clk@80 {
34			compatible = "snps,axs10x-arc-pll-clock";
35			reg = <0x80 0x10>, <0x100 0x10>;
36			#clock-cells = <0>;
37			clocks = <&input_clk>;
38		};
39
40		core_intc: archs-intc@cpu {
41			compatible = "snps,archs-intc";
42			interrupt-controller;
43			#interrupt-cells = <1>;
44		};
45
46		/*
47		 * this GPIO block ORs all interrupts on CPU card (creg,..)
48		 * to uplink only 1 IRQ to ARC core intc
49		 */
50		dw-apb-gpio@0x2000 {
51			compatible = "snps,dw-apb-gpio";
52			reg = < 0x2000 0x80 >;
53			#address-cells = <1>;
54			#size-cells = <0>;
55
56			ictl_intc: gpio-controller@0 {
57				compatible = "snps,dw-apb-gpio-port";
58				gpio-controller;
59				#gpio-cells = <2>;
60				snps,nr-gpios = <30>;
61				reg = <0>;
62				interrupt-controller;
63				#interrupt-cells = <2>;
64				interrupt-parent = <&core_intc>;
65				interrupts = <25>;
66			};
67		};
68
69		debug_uart: dw-apb-uart@0x5000 {
70			compatible = "snps,dw-apb-uart";
71			reg = <0x5000 0x100>;
72			clock-frequency = <33333000>;
73			interrupt-parent = <&ictl_intc>;
74			interrupts = <2 4>;
75			baud = <115200>;
76			reg-shift = <2>;
77			reg-io-width = <4>;
78		};
79
80		arcpct0: pct {
81			compatible = "snps,archs-pct";
82			#interrupt-cells = <1>;
83			interrupt-parent = <&core_intc>;
84			interrupts = <20>;
85		};
86	};
87
88	/*
89	 * The DW APB ICTL intc on MB is connected to CPU intc via a
90	 * DT "invisible" DW APB GPIO block, configured to simply pass thru
91	 * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
92	 *
93	 * So here we mimic a direct connection betwen them, ignoring the
94	 * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
95	 * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
96	 *
97	 * This intc actually resides on MB, but we move it here to
98	 * avoid duplicating the MB dtsi file given that IRQ from
99	 * this intc to cpu intc are different for axs101 and axs103
100	 */
101	mb_intc: dw-apb-ictl@0xe0012000 {
102		#interrupt-cells = <1>;
103		compatible = "snps,dw-apb-ictl";
104		reg = < 0x0 0xe0012000 0x0 0x200 >;
105		interrupt-controller;
106		interrupt-parent = <&core_intc>;
107		interrupts = < 24 >;
108	};
109
110	memory {
111		device_type = "memory";
112		/* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
113		reg = <0x0 0x80000000 0x0 0x20000000	/* 512 MiB low mem */
114		       0x1 0xc0000000 0x0 0x40000000>;	/* 1 GiB highmem */
115	};
116
117	reserved-memory {
118		#address-cells = <2>;
119		#size-cells = <2>;
120		ranges;
121		/*
122		 * Move frame buffer out of IOC aperture (0x8z-0xAz).
123		 */
124		frame_buffer: frame_buffer@be000000 {
125			compatible = "shared-dma-pool";
126			reg = <0x0 0xbe000000 0x0 0x2000000>;
127			no-map;
128		};
129	};
130};
131