1/*
2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Device tree for AXC003 CPU card: HS38x UP configuration
11 */
12
13/include/ "skeleton_hs.dtsi"
14
15/ {
16	compatible = "snps,arc";
17	clock-frequency = <90000000>;
18	#address-cells = <1>;
19	#size-cells = <1>;
20
21	cpu_card {
22		compatible = "simple-bus";
23		#address-cells = <1>;
24		#size-cells = <1>;
25
26		ranges = <0x00000000 0xf0000000 0x10000000>;
27
28		core_intc: archs-intc@cpu {
29			compatible = "snps,archs-intc";
30			interrupt-controller;
31			#interrupt-cells = <1>;
32		};
33
34		/*
35		 * this GPIO block ORs all interrupts on CPU card (creg,..)
36		 * to uplink only 1 IRQ to ARC core intc
37		 */
38		dw-apb-gpio@0x2000 {
39			compatible = "snps,dw-apb-gpio";
40			reg = < 0x2000 0x80 >;
41			#address-cells = <1>;
42			#size-cells = <0>;
43
44			ictl_intc: gpio-controller@0 {
45				compatible = "snps,dw-apb-gpio-port";
46				gpio-controller;
47				#gpio-cells = <2>;
48				snps,nr-gpios = <30>;
49				reg = <0>;
50				interrupt-controller;
51				#interrupt-cells = <2>;
52				interrupt-parent = <&core_intc>;
53				interrupts = <25>;
54			};
55		};
56
57		debug_uart: dw-apb-uart@0x5000 {
58			compatible = "snps,dw-apb-uart";
59			reg = <0x5000 0x100>;
60			clock-frequency = <33333000>;
61			interrupt-parent = <&ictl_intc>;
62			interrupts = <2 4>;
63			baud = <115200>;
64			reg-shift = <2>;
65			reg-io-width = <4>;
66		};
67
68		arcpct0: pct {
69			compatible = "snps,archs-pct";
70			#interrupt-cells = <1>;
71			interrupt-parent = <&core_intc>;
72			interrupts = <20>;
73		};
74	};
75
76	/*
77	 * The DW APB ICTL intc on MB is connected to CPU intc via a
78	 * DT "invisible" DW APB GPIO block, configured to simply pass thru
79	 * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
80	 *
81	 * So here we mimic a direct connection betwen them, ignoring the
82	 * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
83	 * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
84	 *
85	 * This intc actually resides on MB, but we move it here to
86	 * avoid duplicating the MB dtsi file given that IRQ from
87	 * this intc to cpu intc are different for axs101 and axs103
88	 */
89	mb_intc: dw-apb-ictl@0xe0012000 {
90		#interrupt-cells = <1>;
91		compatible = "snps,dw-apb-ictl";
92		reg = < 0xe0012000 0x200 >;
93		interrupt-controller;
94		interrupt-parent = <&core_intc>;
95		interrupts = < 24 >;
96	};
97
98	memory {
99		#address-cells = <1>;
100		#size-cells = <1>;
101		ranges = <0x00000000 0x80000000 0x40000000>;
102		device_type = "memory";
103		reg = <0x80000000 0x20000000>;	/* 512MiB */
104	};
105};
106