1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 2556cc1c5SAlexey Brodkin/* 3556cc1c5SAlexey Brodkin * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 4556cc1c5SAlexey Brodkin */ 5556cc1c5SAlexey Brodkin 6556cc1c5SAlexey Brodkin/* 7556cc1c5SAlexey Brodkin * Device tree for AXC001 770D/EM6/AS221 CPU card 8556cc1c5SAlexey Brodkin * Note that this file only supports the 770D CPU 9556cc1c5SAlexey Brodkin */ 10556cc1c5SAlexey Brodkin 112e8cd938SVineet Gupta/include/ "skeleton.dtsi" 122e8cd938SVineet Gupta 13556cc1c5SAlexey Brodkin/ { 14556cc1c5SAlexey Brodkin compatible = "snps,arc"; 15f862b315SEugeniy Paltsev #address-cells = <2>; 16f862b315SEugeniy Paltsev #size-cells = <2>; 17556cc1c5SAlexey Brodkin 18556cc1c5SAlexey Brodkin cpu_card { 19556cc1c5SAlexey Brodkin compatible = "simple-bus"; 20556cc1c5SAlexey Brodkin #address-cells = <1>; 21556cc1c5SAlexey Brodkin #size-cells = <1>; 22556cc1c5SAlexey Brodkin 23f862b315SEugeniy Paltsev ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 24556cc1c5SAlexey Brodkin 25b3d6aba8SVineet Gupta core_clk: core_clk { 26b3d6aba8SVineet Gupta #clock-cells = <0>; 27b3d6aba8SVineet Gupta compatible = "fixed-clock"; 28b3d6aba8SVineet Gupta clock-frequency = <750000000>; 29b3d6aba8SVineet Gupta }; 30b3d6aba8SVineet Gupta 319ba7648cSVineet Gupta core_intc: arc700-intc@cpu { 32556cc1c5SAlexey Brodkin compatible = "snps,arc700-intc"; 33556cc1c5SAlexey Brodkin interrupt-controller; 34556cc1c5SAlexey Brodkin #interrupt-cells = <1>; 35556cc1c5SAlexey Brodkin }; 36556cc1c5SAlexey Brodkin 37556cc1c5SAlexey Brodkin /* 38556cc1c5SAlexey Brodkin * this GPIO block ORs all interrupts on CPU card (creg,..) 39556cc1c5SAlexey Brodkin * to uplink only 1 IRQ to ARC core intc 40556cc1c5SAlexey Brodkin */ 41ef4c54c3SAlexey Brodkin dw-apb-gpio@2000 { 42556cc1c5SAlexey Brodkin compatible = "snps,dw-apb-gpio"; 43556cc1c5SAlexey Brodkin reg = < 0x2000 0x80 >; 44556cc1c5SAlexey Brodkin #address-cells = <1>; 45556cc1c5SAlexey Brodkin #size-cells = <0>; 46556cc1c5SAlexey Brodkin 47556cc1c5SAlexey Brodkin ictl_intc: gpio-controller@0 { 48556cc1c5SAlexey Brodkin compatible = "snps,dw-apb-gpio-port"; 49556cc1c5SAlexey Brodkin gpio-controller; 50556cc1c5SAlexey Brodkin #gpio-cells = <2>; 51556cc1c5SAlexey Brodkin snps,nr-gpios = <30>; 52556cc1c5SAlexey Brodkin reg = <0>; 53556cc1c5SAlexey Brodkin interrupt-controller; 54556cc1c5SAlexey Brodkin #interrupt-cells = <2>; 559ba7648cSVineet Gupta interrupt-parent = <&core_intc>; 56556cc1c5SAlexey Brodkin interrupts = <15>; 57556cc1c5SAlexey Brodkin }; 58556cc1c5SAlexey Brodkin }; 59556cc1c5SAlexey Brodkin 60ef4c54c3SAlexey Brodkin debug_uart: dw-apb-uart@5000 { 61556cc1c5SAlexey Brodkin compatible = "snps,dw-apb-uart"; 62556cc1c5SAlexey Brodkin reg = <0x5000 0x100>; 63556cc1c5SAlexey Brodkin clock-frequency = <33333000>; 64556cc1c5SAlexey Brodkin interrupt-parent = <&ictl_intc>; 65556cc1c5SAlexey Brodkin interrupts = <19 4>; 66556cc1c5SAlexey Brodkin baud = <115200>; 67556cc1c5SAlexey Brodkin reg-shift = <2>; 68556cc1c5SAlexey Brodkin reg-io-width = <4>; 69556cc1c5SAlexey Brodkin }; 70556cc1c5SAlexey Brodkin 716227e9f0SAlexey Brodkin arcpct0: pct { 72556cc1c5SAlexey Brodkin compatible = "snps,arc700-pct"; 73556cc1c5SAlexey Brodkin }; 74556cc1c5SAlexey Brodkin }; 75556cc1c5SAlexey Brodkin 76e0183f52SAlexey Brodkin /* 77e0183f52SAlexey Brodkin * This INTC is actually connected to DW APB GPIO 78e0183f52SAlexey Brodkin * which acts as a wire between MB INTC and CPU INTC. 79e0183f52SAlexey Brodkin * GPIO INTC is configured in platform init code 80e0183f52SAlexey Brodkin * and here we mimic direct connection from MB INTC to 81e0183f52SAlexey Brodkin * CPU INTC, thus we set "interrupts = <7>" instead of 82e0183f52SAlexey Brodkin * "interrupts = <12>" 83e0183f52SAlexey Brodkin * 84e0183f52SAlexey Brodkin * This intc actually resides on MB, but we move it here to 85e0183f52SAlexey Brodkin * avoid duplicating the MB dtsi file given that IRQ from 86e0183f52SAlexey Brodkin * this intc to cpu intc are different for axs101 and axs103 87e0183f52SAlexey Brodkin */ 88ef4c54c3SAlexey Brodkin mb_intc: dw-apb-ictl@e0012000 { 89e0183f52SAlexey Brodkin #interrupt-cells = <1>; 90e0183f52SAlexey Brodkin compatible = "snps,dw-apb-ictl"; 91f862b315SEugeniy Paltsev reg = < 0x0 0xe0012000 0x0 0x200 >; 92e0183f52SAlexey Brodkin interrupt-controller; 939ba7648cSVineet Gupta interrupt-parent = <&core_intc>; 94e0183f52SAlexey Brodkin interrupts = < 7 >; 95e0183f52SAlexey Brodkin }; 96e0183f52SAlexey Brodkin 97556cc1c5SAlexey Brodkin memory { 98556cc1c5SAlexey Brodkin device_type = "memory"; 999ed68785SEugeniy Paltsev /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ 100f862b315SEugeniy Paltsev reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */ 101cb2ad5e5SAlexey Brodkin }; 102cb2ad5e5SAlexey Brodkin 103cb2ad5e5SAlexey Brodkin reserved-memory { 104f862b315SEugeniy Paltsev #address-cells = <2>; 105f862b315SEugeniy Paltsev #size-cells = <2>; 106cb2ad5e5SAlexey Brodkin ranges; 107cb2ad5e5SAlexey Brodkin /* 108cb2ad5e5SAlexey Brodkin * We just move frame buffer area to the very end of 109cb2ad5e5SAlexey Brodkin * available DDR. And even though in case of ARC770 there's 110cb2ad5e5SAlexey Brodkin * no strict requirement for a frame-buffer to be in any 111cb2ad5e5SAlexey Brodkin * particular location it allows us to use the same 112cb2ad5e5SAlexey Brodkin * base board's DT node for ARC PGU as for ARc HS38. 113cb2ad5e5SAlexey Brodkin */ 114cb2ad5e5SAlexey Brodkin frame_buffer: frame_buffer@9e000000 { 115cb2ad5e5SAlexey Brodkin compatible = "shared-dma-pool"; 116f862b315SEugeniy Paltsev reg = <0x0 0x9e000000 0x0 0x2000000>; 117cb2ad5e5SAlexey Brodkin no-map; 118cb2ad5e5SAlexey Brodkin }; 119556cc1c5SAlexey Brodkin }; 120556cc1c5SAlexey Brodkin}; 121