1556cc1c5SAlexey Brodkin/* 2556cc1c5SAlexey Brodkin * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 3556cc1c5SAlexey Brodkin * 4556cc1c5SAlexey Brodkin * This program is free software; you can redistribute it and/or modify 5556cc1c5SAlexey Brodkin * it under the terms of the GNU General Public License version 2 as 6556cc1c5SAlexey Brodkin * published by the Free Software Foundation. 7556cc1c5SAlexey Brodkin */ 8556cc1c5SAlexey Brodkin 9556cc1c5SAlexey Brodkin/* 10556cc1c5SAlexey Brodkin * Device tree for AXC001 770D/EM6/AS221 CPU card 11556cc1c5SAlexey Brodkin * Note that this file only supports the 770D CPU 12556cc1c5SAlexey Brodkin */ 13556cc1c5SAlexey Brodkin 142e8cd938SVineet Gupta/include/ "skeleton.dtsi" 152e8cd938SVineet Gupta 16556cc1c5SAlexey Brodkin/ { 17556cc1c5SAlexey Brodkin compatible = "snps,arc"; 18f862b315SEugeniy Paltsev #address-cells = <2>; 19f862b315SEugeniy Paltsev #size-cells = <2>; 20556cc1c5SAlexey Brodkin 21556cc1c5SAlexey Brodkin cpu_card { 22556cc1c5SAlexey Brodkin compatible = "simple-bus"; 23556cc1c5SAlexey Brodkin #address-cells = <1>; 24556cc1c5SAlexey Brodkin #size-cells = <1>; 25556cc1c5SAlexey Brodkin 26f862b315SEugeniy Paltsev ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 27556cc1c5SAlexey Brodkin 28b3d6aba8SVineet Gupta core_clk: core_clk { 29b3d6aba8SVineet Gupta #clock-cells = <0>; 30b3d6aba8SVineet Gupta compatible = "fixed-clock"; 31b3d6aba8SVineet Gupta clock-frequency = <750000000>; 32b3d6aba8SVineet Gupta }; 33b3d6aba8SVineet Gupta 349ba7648cSVineet Gupta core_intc: arc700-intc@cpu { 35556cc1c5SAlexey Brodkin compatible = "snps,arc700-intc"; 36556cc1c5SAlexey Brodkin interrupt-controller; 37556cc1c5SAlexey Brodkin #interrupt-cells = <1>; 38556cc1c5SAlexey Brodkin }; 39556cc1c5SAlexey Brodkin 40556cc1c5SAlexey Brodkin /* 41556cc1c5SAlexey Brodkin * this GPIO block ORs all interrupts on CPU card (creg,..) 42556cc1c5SAlexey Brodkin * to uplink only 1 IRQ to ARC core intc 43556cc1c5SAlexey Brodkin */ 44556cc1c5SAlexey Brodkin dw-apb-gpio@0x2000 { 45556cc1c5SAlexey Brodkin compatible = "snps,dw-apb-gpio"; 46556cc1c5SAlexey Brodkin reg = < 0x2000 0x80 >; 47556cc1c5SAlexey Brodkin #address-cells = <1>; 48556cc1c5SAlexey Brodkin #size-cells = <0>; 49556cc1c5SAlexey Brodkin 50556cc1c5SAlexey Brodkin ictl_intc: gpio-controller@0 { 51556cc1c5SAlexey Brodkin compatible = "snps,dw-apb-gpio-port"; 52556cc1c5SAlexey Brodkin gpio-controller; 53556cc1c5SAlexey Brodkin #gpio-cells = <2>; 54556cc1c5SAlexey Brodkin snps,nr-gpios = <30>; 55556cc1c5SAlexey Brodkin reg = <0>; 56556cc1c5SAlexey Brodkin interrupt-controller; 57556cc1c5SAlexey Brodkin #interrupt-cells = <2>; 589ba7648cSVineet Gupta interrupt-parent = <&core_intc>; 59556cc1c5SAlexey Brodkin interrupts = <15>; 60556cc1c5SAlexey Brodkin }; 61556cc1c5SAlexey Brodkin }; 62556cc1c5SAlexey Brodkin 63556cc1c5SAlexey Brodkin debug_uart: dw-apb-uart@0x5000 { 64556cc1c5SAlexey Brodkin compatible = "snps,dw-apb-uart"; 65556cc1c5SAlexey Brodkin reg = <0x5000 0x100>; 66556cc1c5SAlexey Brodkin clock-frequency = <33333000>; 67556cc1c5SAlexey Brodkin interrupt-parent = <&ictl_intc>; 68556cc1c5SAlexey Brodkin interrupts = <19 4>; 69556cc1c5SAlexey Brodkin baud = <115200>; 70556cc1c5SAlexey Brodkin reg-shift = <2>; 71556cc1c5SAlexey Brodkin reg-io-width = <4>; 72556cc1c5SAlexey Brodkin }; 73556cc1c5SAlexey Brodkin 746227e9f0SAlexey Brodkin arcpct0: pct { 75556cc1c5SAlexey Brodkin compatible = "snps,arc700-pct"; 76556cc1c5SAlexey Brodkin }; 77556cc1c5SAlexey Brodkin }; 78556cc1c5SAlexey Brodkin 79e0183f52SAlexey Brodkin /* 80e0183f52SAlexey Brodkin * This INTC is actually connected to DW APB GPIO 81e0183f52SAlexey Brodkin * which acts as a wire between MB INTC and CPU INTC. 82e0183f52SAlexey Brodkin * GPIO INTC is configured in platform init code 83e0183f52SAlexey Brodkin * and here we mimic direct connection from MB INTC to 84e0183f52SAlexey Brodkin * CPU INTC, thus we set "interrupts = <7>" instead of 85e0183f52SAlexey Brodkin * "interrupts = <12>" 86e0183f52SAlexey Brodkin * 87e0183f52SAlexey Brodkin * This intc actually resides on MB, but we move it here to 88e0183f52SAlexey Brodkin * avoid duplicating the MB dtsi file given that IRQ from 89e0183f52SAlexey Brodkin * this intc to cpu intc are different for axs101 and axs103 90e0183f52SAlexey Brodkin */ 91e0183f52SAlexey Brodkin mb_intc: dw-apb-ictl@0xe0012000 { 92e0183f52SAlexey Brodkin #interrupt-cells = <1>; 93e0183f52SAlexey Brodkin compatible = "snps,dw-apb-ictl"; 94f862b315SEugeniy Paltsev reg = < 0x0 0xe0012000 0x0 0x200 >; 95e0183f52SAlexey Brodkin interrupt-controller; 969ba7648cSVineet Gupta interrupt-parent = <&core_intc>; 97e0183f52SAlexey Brodkin interrupts = < 7 >; 98e0183f52SAlexey Brodkin }; 99e0183f52SAlexey Brodkin 100556cc1c5SAlexey Brodkin memory { 101556cc1c5SAlexey Brodkin device_type = "memory"; 1029ed68785SEugeniy Paltsev /* CONFIG_LINUX_RAM_BASE needs to match low mem start */ 103f862b315SEugeniy Paltsev reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */ 104cb2ad5e5SAlexey Brodkin }; 105cb2ad5e5SAlexey Brodkin 106cb2ad5e5SAlexey Brodkin reserved-memory { 107f862b315SEugeniy Paltsev #address-cells = <2>; 108f862b315SEugeniy Paltsev #size-cells = <2>; 109cb2ad5e5SAlexey Brodkin ranges; 110cb2ad5e5SAlexey Brodkin /* 111cb2ad5e5SAlexey Brodkin * We just move frame buffer area to the very end of 112cb2ad5e5SAlexey Brodkin * available DDR. And even though in case of ARC770 there's 113cb2ad5e5SAlexey Brodkin * no strict requirement for a frame-buffer to be in any 114cb2ad5e5SAlexey Brodkin * particular location it allows us to use the same 115cb2ad5e5SAlexey Brodkin * base board's DT node for ARC PGU as for ARc HS38. 116cb2ad5e5SAlexey Brodkin */ 117cb2ad5e5SAlexey Brodkin frame_buffer: frame_buffer@9e000000 { 118cb2ad5e5SAlexey Brodkin compatible = "shared-dma-pool"; 119f862b315SEugeniy Paltsev reg = <0x0 0x9e000000 0x0 0x2000000>; 120cb2ad5e5SAlexey Brodkin no-map; 121cb2ad5e5SAlexey Brodkin }; 122556cc1c5SAlexey Brodkin }; 123556cc1c5SAlexey Brodkin}; 124