1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
29d1a546cSKirti Wankhede /*
39d1a546cSKirti Wankhede * Mediated virtual PCI serial host device driver
49d1a546cSKirti Wankhede *
59d1a546cSKirti Wankhede * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
69d1a546cSKirti Wankhede * Author: Neo Jia <cjia@nvidia.com>
79d1a546cSKirti Wankhede * Kirti Wankhede <kwankhede@nvidia.com>
89d1a546cSKirti Wankhede *
99d1a546cSKirti Wankhede * Sample driver that creates mdev device that simulates serial port over PCI
109d1a546cSKirti Wankhede * card.
119d1a546cSKirti Wankhede */
129d1a546cSKirti Wankhede
139d1a546cSKirti Wankhede #include <linux/init.h>
149d1a546cSKirti Wankhede #include <linux/module.h>
159d1a546cSKirti Wankhede #include <linux/kernel.h>
169d1a546cSKirti Wankhede #include <linux/fs.h>
179d1a546cSKirti Wankhede #include <linux/poll.h>
189d1a546cSKirti Wankhede #include <linux/slab.h>
199d1a546cSKirti Wankhede #include <linux/cdev.h>
209d1a546cSKirti Wankhede #include <linux/sched.h>
219d1a546cSKirti Wankhede #include <linux/wait.h>
229d1a546cSKirti Wankhede #include <linux/vfio.h>
239d1a546cSKirti Wankhede #include <linux/iommu.h>
249d1a546cSKirti Wankhede #include <linux/sysfs.h>
259d1a546cSKirti Wankhede #include <linux/ctype.h>
269d1a546cSKirti Wankhede #include <linux/file.h>
279d1a546cSKirti Wankhede #include <linux/mdev.h>
289d1a546cSKirti Wankhede #include <linux/pci.h>
299d1a546cSKirti Wankhede #include <linux/serial.h>
309d1a546cSKirti Wankhede #include <uapi/linux/serial_reg.h>
319d1a546cSKirti Wankhede #include <linux/eventfd.h>
329d1a546cSKirti Wankhede /*
339d1a546cSKirti Wankhede * #defines
349d1a546cSKirti Wankhede */
359d1a546cSKirti Wankhede
369d1a546cSKirti Wankhede #define VERSION_STRING "0.1"
379d1a546cSKirti Wankhede #define DRIVER_AUTHOR "NVIDIA Corporation"
389d1a546cSKirti Wankhede
399d1a546cSKirti Wankhede #define MTTY_CLASS_NAME "mtty"
409d1a546cSKirti Wankhede
419d1a546cSKirti Wankhede #define MTTY_NAME "mtty"
429d1a546cSKirti Wankhede
439d1a546cSKirti Wankhede #define MTTY_STRING_LEN 16
449d1a546cSKirti Wankhede
459d1a546cSKirti Wankhede #define MTTY_CONFIG_SPACE_SIZE 0xff
469d1a546cSKirti Wankhede #define MTTY_IO_BAR_SIZE 0x8
479d1a546cSKirti Wankhede #define MTTY_MMIO_BAR_SIZE 0x100000
489d1a546cSKirti Wankhede
499d1a546cSKirti Wankhede #define STORE_LE16(addr, val) (*(u16 *)addr = val)
509d1a546cSKirti Wankhede #define STORE_LE32(addr, val) (*(u32 *)addr = val)
519d1a546cSKirti Wankhede
529d1a546cSKirti Wankhede #define MAX_FIFO_SIZE 16
539d1a546cSKirti Wankhede
549d1a546cSKirti Wankhede #define CIRCULAR_BUF_INC_IDX(idx) (idx = (idx + 1) & (MAX_FIFO_SIZE - 1))
559d1a546cSKirti Wankhede
569d1a546cSKirti Wankhede #define MTTY_VFIO_PCI_OFFSET_SHIFT 40
579d1a546cSKirti Wankhede
589d1a546cSKirti Wankhede #define MTTY_VFIO_PCI_OFFSET_TO_INDEX(off) (off >> MTTY_VFIO_PCI_OFFSET_SHIFT)
599d1a546cSKirti Wankhede #define MTTY_VFIO_PCI_INDEX_TO_OFFSET(index) \
609d1a546cSKirti Wankhede ((u64)(index) << MTTY_VFIO_PCI_OFFSET_SHIFT)
619d1a546cSKirti Wankhede #define MTTY_VFIO_PCI_OFFSET_MASK \
629d1a546cSKirti Wankhede (((u64)(1) << MTTY_VFIO_PCI_OFFSET_SHIFT) - 1)
639d1a546cSKirti Wankhede #define MAX_MTTYS 24
649d1a546cSKirti Wankhede
659d1a546cSKirti Wankhede /*
669d1a546cSKirti Wankhede * Global Structures
679d1a546cSKirti Wankhede */
689d1a546cSKirti Wankhede
694b2dbd56SKefeng Wang static struct mtty_dev {
709d1a546cSKirti Wankhede dev_t vd_devt;
719d1a546cSKirti Wankhede struct class *vd_class;
729d1a546cSKirti Wankhede struct cdev vd_cdev;
739d1a546cSKirti Wankhede struct idr vd_idr;
749d1a546cSKirti Wankhede struct device dev;
7589345d51SChristoph Hellwig struct mdev_parent parent;
769d1a546cSKirti Wankhede } mtty_dev;
779d1a546cSKirti Wankhede
789d1a546cSKirti Wankhede struct mdev_region_info {
799d1a546cSKirti Wankhede u64 start;
809d1a546cSKirti Wankhede u64 phys_start;
819d1a546cSKirti Wankhede u32 size;
829d1a546cSKirti Wankhede u64 vfio_offset;
839d1a546cSKirti Wankhede };
849d1a546cSKirti Wankhede
859d1a546cSKirti Wankhede #if defined(DEBUG_REGS)
864b2dbd56SKefeng Wang static const char *wr_reg[] = {
879d1a546cSKirti Wankhede "TX",
889d1a546cSKirti Wankhede "IER",
899d1a546cSKirti Wankhede "FCR",
909d1a546cSKirti Wankhede "LCR",
919d1a546cSKirti Wankhede "MCR",
929d1a546cSKirti Wankhede "LSR",
939d1a546cSKirti Wankhede "MSR",
949d1a546cSKirti Wankhede "SCR"
959d1a546cSKirti Wankhede };
969d1a546cSKirti Wankhede
974b2dbd56SKefeng Wang static const char *rd_reg[] = {
989d1a546cSKirti Wankhede "RX",
999d1a546cSKirti Wankhede "IER",
1009d1a546cSKirti Wankhede "IIR",
1019d1a546cSKirti Wankhede "LCR",
1029d1a546cSKirti Wankhede "MCR",
1039d1a546cSKirti Wankhede "LSR",
1049d1a546cSKirti Wankhede "MSR",
1059d1a546cSKirti Wankhede "SCR"
1069d1a546cSKirti Wankhede };
1079d1a546cSKirti Wankhede #endif
1089d1a546cSKirti Wankhede
1099d1a546cSKirti Wankhede /* loop back buffer */
1109d1a546cSKirti Wankhede struct rxtx {
1119d1a546cSKirti Wankhede u8 fifo[MAX_FIFO_SIZE];
1129d1a546cSKirti Wankhede u8 head, tail;
1139d1a546cSKirti Wankhede u8 count;
1149d1a546cSKirti Wankhede };
1159d1a546cSKirti Wankhede
1169d1a546cSKirti Wankhede struct serial_port {
1179d1a546cSKirti Wankhede u8 uart_reg[8]; /* 8 registers */
1189d1a546cSKirti Wankhede struct rxtx rxtx; /* loop back buffer */
1199d1a546cSKirti Wankhede bool dlab;
1209d1a546cSKirti Wankhede bool overrun;
1219d1a546cSKirti Wankhede u16 divisor;
1229d1a546cSKirti Wankhede u8 fcr; /* FIFO control register */
1239d1a546cSKirti Wankhede u8 max_fifo_size;
1249d1a546cSKirti Wankhede u8 intr_trigger_level; /* interrupt trigger level */
1259d1a546cSKirti Wankhede };
1269d1a546cSKirti Wankhede
1279d1a546cSKirti Wankhede /* State of each mdev device */
1289d1a546cSKirti Wankhede struct mdev_state {
12909177ac9SJason Gunthorpe struct vfio_device vdev;
1309d1a546cSKirti Wankhede struct eventfd_ctx *intx_evtfd;
1319d1a546cSKirti Wankhede struct eventfd_ctx *msi_evtfd;
1329d1a546cSKirti Wankhede int irq_index;
1339d1a546cSKirti Wankhede u8 *vconfig;
1349d1a546cSKirti Wankhede struct mutex ops_lock;
1359d1a546cSKirti Wankhede struct mdev_device *mdev;
1369d1a546cSKirti Wankhede struct mdev_region_info region_info[VFIO_PCI_NUM_REGIONS];
1379d1a546cSKirti Wankhede u32 bar_mask[VFIO_PCI_NUM_REGIONS];
1389d1a546cSKirti Wankhede struct list_head next;
1399d1a546cSKirti Wankhede struct serial_port s[2];
1409d1a546cSKirti Wankhede struct mutex rxtx_lock;
1419d1a546cSKirti Wankhede struct vfio_device_info dev_info;
1429d1a546cSKirti Wankhede int nr_ports;
143*94eacb45SAlex Williamson u8 intx_mask:1;
1449d1a546cSKirti Wankhede };
1459d1a546cSKirti Wankhede
146da44c340SChristoph Hellwig static struct mtty_type {
147da44c340SChristoph Hellwig struct mdev_type type;
148da44c340SChristoph Hellwig int nr_ports;
149da44c340SChristoph Hellwig } mtty_types[2] = {
1500bc79069SChristoph Hellwig { .nr_ports = 1, .type.sysfs_name = "1",
1510bc79069SChristoph Hellwig .type.pretty_name = "Single port serial" },
1520bc79069SChristoph Hellwig { .nr_ports = 2, .type.sysfs_name = "2",
1530bc79069SChristoph Hellwig .type.pretty_name = "Dual port serial" },
154da44c340SChristoph Hellwig };
155da44c340SChristoph Hellwig
156da44c340SChristoph Hellwig static struct mdev_type *mtty_mdev_types[] = {
157da44c340SChristoph Hellwig &mtty_types[0].type,
158da44c340SChristoph Hellwig &mtty_types[1].type,
159da44c340SChristoph Hellwig };
160da44c340SChristoph Hellwig
16197d0a687SAlex Williamson static atomic_t mdev_avail_ports = ATOMIC_INIT(MAX_MTTYS);
1629d1a546cSKirti Wankhede
1639d1a546cSKirti Wankhede static const struct file_operations vd_fops = {
1649d1a546cSKirti Wankhede .owner = THIS_MODULE,
1659d1a546cSKirti Wankhede };
1669d1a546cSKirti Wankhede
16709177ac9SJason Gunthorpe static const struct vfio_device_ops mtty_dev_ops;
16809177ac9SJason Gunthorpe
1699d1a546cSKirti Wankhede /* Helper functions */
1709d1a546cSKirti Wankhede
dump_buffer(u8 * buf,uint32_t count)1714b2dbd56SKefeng Wang static void dump_buffer(u8 *buf, uint32_t count)
1729d1a546cSKirti Wankhede {
1739d1a546cSKirti Wankhede #if defined(DEBUG)
1749d1a546cSKirti Wankhede int i;
1759d1a546cSKirti Wankhede
1769d1a546cSKirti Wankhede pr_info("Buffer:\n");
1779d1a546cSKirti Wankhede for (i = 0; i < count; i++) {
1789d1a546cSKirti Wankhede pr_info("%2x ", *(buf + i));
1799d1a546cSKirti Wankhede if ((i + 1) % 16 == 0)
1809d1a546cSKirti Wankhede pr_info("\n");
1819d1a546cSKirti Wankhede }
1829d1a546cSKirti Wankhede #endif
1839d1a546cSKirti Wankhede }
1849d1a546cSKirti Wankhede
is_intx(struct mdev_state * mdev_state)185*94eacb45SAlex Williamson static bool is_intx(struct mdev_state *mdev_state)
186*94eacb45SAlex Williamson {
187*94eacb45SAlex Williamson return mdev_state->irq_index == VFIO_PCI_INTX_IRQ_INDEX;
188*94eacb45SAlex Williamson }
189*94eacb45SAlex Williamson
is_msi(struct mdev_state * mdev_state)190*94eacb45SAlex Williamson static bool is_msi(struct mdev_state *mdev_state)
191*94eacb45SAlex Williamson {
192*94eacb45SAlex Williamson return mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX;
193*94eacb45SAlex Williamson }
194*94eacb45SAlex Williamson
is_noirq(struct mdev_state * mdev_state)195*94eacb45SAlex Williamson static bool is_noirq(struct mdev_state *mdev_state)
196*94eacb45SAlex Williamson {
197*94eacb45SAlex Williamson return !is_intx(mdev_state) && !is_msi(mdev_state);
198*94eacb45SAlex Williamson }
199*94eacb45SAlex Williamson
mtty_trigger_interrupt(struct mdev_state * mdev_state)200*94eacb45SAlex Williamson static void mtty_trigger_interrupt(struct mdev_state *mdev_state)
201*94eacb45SAlex Williamson {
202*94eacb45SAlex Williamson lockdep_assert_held(&mdev_state->ops_lock);
203*94eacb45SAlex Williamson
204*94eacb45SAlex Williamson if (is_msi(mdev_state)) {
205*94eacb45SAlex Williamson if (mdev_state->msi_evtfd)
206*94eacb45SAlex Williamson eventfd_signal(mdev_state->msi_evtfd, 1);
207*94eacb45SAlex Williamson } else if (is_intx(mdev_state)) {
208*94eacb45SAlex Williamson if (mdev_state->intx_evtfd && !mdev_state->intx_mask) {
209*94eacb45SAlex Williamson eventfd_signal(mdev_state->intx_evtfd, 1);
210*94eacb45SAlex Williamson mdev_state->intx_mask = true;
211*94eacb45SAlex Williamson }
212*94eacb45SAlex Williamson }
213*94eacb45SAlex Williamson }
214*94eacb45SAlex Williamson
mtty_create_config_space(struct mdev_state * mdev_state)2159d1a546cSKirti Wankhede static void mtty_create_config_space(struct mdev_state *mdev_state)
2169d1a546cSKirti Wankhede {
2179d1a546cSKirti Wankhede /* PCI dev ID */
2189d1a546cSKirti Wankhede STORE_LE32((u32 *) &mdev_state->vconfig[0x0], 0x32534348);
2199d1a546cSKirti Wankhede
2209d1a546cSKirti Wankhede /* Control: I/O+, Mem-, BusMaster- */
2219d1a546cSKirti Wankhede STORE_LE16((u16 *) &mdev_state->vconfig[0x4], 0x0001);
2229d1a546cSKirti Wankhede
2239d1a546cSKirti Wankhede /* Status: capabilities list absent */
2249d1a546cSKirti Wankhede STORE_LE16((u16 *) &mdev_state->vconfig[0x6], 0x0200);
2259d1a546cSKirti Wankhede
2269d1a546cSKirti Wankhede /* Rev ID */
2279d1a546cSKirti Wankhede mdev_state->vconfig[0x8] = 0x10;
2289d1a546cSKirti Wankhede
2299d1a546cSKirti Wankhede /* programming interface class : 16550-compatible serial controller */
2309d1a546cSKirti Wankhede mdev_state->vconfig[0x9] = 0x02;
2319d1a546cSKirti Wankhede
2329d1a546cSKirti Wankhede /* Sub class : 00 */
2339d1a546cSKirti Wankhede mdev_state->vconfig[0xa] = 0x00;
2349d1a546cSKirti Wankhede
2359d1a546cSKirti Wankhede /* Base class : Simple Communication controllers */
2369d1a546cSKirti Wankhede mdev_state->vconfig[0xb] = 0x07;
2379d1a546cSKirti Wankhede
2389d1a546cSKirti Wankhede /* base address registers */
2399d1a546cSKirti Wankhede /* BAR0: IO space */
2409d1a546cSKirti Wankhede STORE_LE32((u32 *) &mdev_state->vconfig[0x10], 0x000001);
2419d1a546cSKirti Wankhede mdev_state->bar_mask[0] = ~(MTTY_IO_BAR_SIZE) + 1;
2429d1a546cSKirti Wankhede
2439d1a546cSKirti Wankhede if (mdev_state->nr_ports == 2) {
2449d1a546cSKirti Wankhede /* BAR1: IO space */
2459d1a546cSKirti Wankhede STORE_LE32((u32 *) &mdev_state->vconfig[0x14], 0x000001);
2469d1a546cSKirti Wankhede mdev_state->bar_mask[1] = ~(MTTY_IO_BAR_SIZE) + 1;
2479d1a546cSKirti Wankhede }
2489d1a546cSKirti Wankhede
2499d1a546cSKirti Wankhede /* Subsystem ID */
2509d1a546cSKirti Wankhede STORE_LE32((u32 *) &mdev_state->vconfig[0x2c], 0x32534348);
2519d1a546cSKirti Wankhede
2529d1a546cSKirti Wankhede mdev_state->vconfig[0x34] = 0x00; /* Cap Ptr */
2539d1a546cSKirti Wankhede mdev_state->vconfig[0x3d] = 0x01; /* interrupt pin (INTA#) */
2549d1a546cSKirti Wankhede
2559d1a546cSKirti Wankhede /* Vendor specific data */
2569d1a546cSKirti Wankhede mdev_state->vconfig[0x40] = 0x23;
2579d1a546cSKirti Wankhede mdev_state->vconfig[0x43] = 0x80;
2589d1a546cSKirti Wankhede mdev_state->vconfig[0x44] = 0x23;
2599d1a546cSKirti Wankhede mdev_state->vconfig[0x48] = 0x23;
2609d1a546cSKirti Wankhede mdev_state->vconfig[0x4c] = 0x23;
2619d1a546cSKirti Wankhede
2629d1a546cSKirti Wankhede mdev_state->vconfig[0x60] = 0x50;
2639d1a546cSKirti Wankhede mdev_state->vconfig[0x61] = 0x43;
2649d1a546cSKirti Wankhede mdev_state->vconfig[0x62] = 0x49;
2659d1a546cSKirti Wankhede mdev_state->vconfig[0x63] = 0x20;
2669d1a546cSKirti Wankhede mdev_state->vconfig[0x64] = 0x53;
2679d1a546cSKirti Wankhede mdev_state->vconfig[0x65] = 0x65;
2689d1a546cSKirti Wankhede mdev_state->vconfig[0x66] = 0x72;
2699d1a546cSKirti Wankhede mdev_state->vconfig[0x67] = 0x69;
2709d1a546cSKirti Wankhede mdev_state->vconfig[0x68] = 0x61;
2719d1a546cSKirti Wankhede mdev_state->vconfig[0x69] = 0x6c;
2729d1a546cSKirti Wankhede mdev_state->vconfig[0x6a] = 0x2f;
2739d1a546cSKirti Wankhede mdev_state->vconfig[0x6b] = 0x55;
2749d1a546cSKirti Wankhede mdev_state->vconfig[0x6c] = 0x41;
2759d1a546cSKirti Wankhede mdev_state->vconfig[0x6d] = 0x52;
2769d1a546cSKirti Wankhede mdev_state->vconfig[0x6e] = 0x54;
2779d1a546cSKirti Wankhede }
2789d1a546cSKirti Wankhede
handle_pci_cfg_write(struct mdev_state * mdev_state,u16 offset,u8 * buf,u32 count)2799d1a546cSKirti Wankhede static void handle_pci_cfg_write(struct mdev_state *mdev_state, u16 offset,
2808ba35b3aSNathan Chancellor u8 *buf, u32 count)
2819d1a546cSKirti Wankhede {
2829d1a546cSKirti Wankhede u32 cfg_addr, bar_mask, bar_index = 0;
2839d1a546cSKirti Wankhede
2849d1a546cSKirti Wankhede switch (offset) {
2859d1a546cSKirti Wankhede case 0x04: /* device control */
2869d1a546cSKirti Wankhede case 0x06: /* device status */
2879d1a546cSKirti Wankhede /* do nothing */
2889d1a546cSKirti Wankhede break;
2899d1a546cSKirti Wankhede case 0x3c: /* interrupt line */
2909d1a546cSKirti Wankhede mdev_state->vconfig[0x3c] = buf[0];
2919d1a546cSKirti Wankhede break;
2929d1a546cSKirti Wankhede case 0x3d:
2939d1a546cSKirti Wankhede /*
2949d1a546cSKirti Wankhede * Interrupt Pin is hardwired to INTA.
2959d1a546cSKirti Wankhede * This field is write protected by hardware
2969d1a546cSKirti Wankhede */
2979d1a546cSKirti Wankhede break;
2989d1a546cSKirti Wankhede case 0x10: /* BAR0 */
2999d1a546cSKirti Wankhede case 0x14: /* BAR1 */
3009d1a546cSKirti Wankhede if (offset == 0x10)
3019d1a546cSKirti Wankhede bar_index = 0;
3029d1a546cSKirti Wankhede else if (offset == 0x14)
3039d1a546cSKirti Wankhede bar_index = 1;
3049d1a546cSKirti Wankhede
3059d1a546cSKirti Wankhede if ((mdev_state->nr_ports == 1) && (bar_index == 1)) {
3069d1a546cSKirti Wankhede STORE_LE32(&mdev_state->vconfig[offset], 0);
3079d1a546cSKirti Wankhede break;
3089d1a546cSKirti Wankhede }
3099d1a546cSKirti Wankhede
3109d1a546cSKirti Wankhede cfg_addr = *(u32 *)buf;
3119d1a546cSKirti Wankhede pr_info("BAR%d addr 0x%x\n", bar_index, cfg_addr);
3129d1a546cSKirti Wankhede
3139d1a546cSKirti Wankhede if (cfg_addr == 0xffffffff) {
3149d1a546cSKirti Wankhede bar_mask = mdev_state->bar_mask[bar_index];
3159d1a546cSKirti Wankhede cfg_addr = (cfg_addr & bar_mask);
3169d1a546cSKirti Wankhede }
3179d1a546cSKirti Wankhede
3189d1a546cSKirti Wankhede cfg_addr |= (mdev_state->vconfig[offset] & 0x3ul);
3199d1a546cSKirti Wankhede STORE_LE32(&mdev_state->vconfig[offset], cfg_addr);
3209d1a546cSKirti Wankhede break;
3219d1a546cSKirti Wankhede case 0x18: /* BAR2 */
3229d1a546cSKirti Wankhede case 0x1c: /* BAR3 */
3239d1a546cSKirti Wankhede case 0x20: /* BAR4 */
3249d1a546cSKirti Wankhede STORE_LE32(&mdev_state->vconfig[offset], 0);
3259d1a546cSKirti Wankhede break;
3269d1a546cSKirti Wankhede default:
3279d1a546cSKirti Wankhede pr_info("PCI config write @0x%x of %d bytes not handled\n",
3289d1a546cSKirti Wankhede offset, count);
3299d1a546cSKirti Wankhede break;
3309d1a546cSKirti Wankhede }
3319d1a546cSKirti Wankhede }
3329d1a546cSKirti Wankhede
handle_bar_write(unsigned int index,struct mdev_state * mdev_state,u16 offset,u8 * buf,u32 count)3339d1a546cSKirti Wankhede static void handle_bar_write(unsigned int index, struct mdev_state *mdev_state,
3348ba35b3aSNathan Chancellor u16 offset, u8 *buf, u32 count)
3359d1a546cSKirti Wankhede {
3369d1a546cSKirti Wankhede u8 data = *buf;
3379d1a546cSKirti Wankhede
3389d1a546cSKirti Wankhede /* Handle data written by guest */
3399d1a546cSKirti Wankhede switch (offset) {
3409d1a546cSKirti Wankhede case UART_TX:
3419d1a546cSKirti Wankhede /* if DLAB set, data is LSB of divisor */
3429d1a546cSKirti Wankhede if (mdev_state->s[index].dlab) {
3439d1a546cSKirti Wankhede mdev_state->s[index].divisor |= data;
3449d1a546cSKirti Wankhede break;
3459d1a546cSKirti Wankhede }
3469d1a546cSKirti Wankhede
3479d1a546cSKirti Wankhede mutex_lock(&mdev_state->rxtx_lock);
3489d1a546cSKirti Wankhede
3499d1a546cSKirti Wankhede /* save in TX buffer */
3509d1a546cSKirti Wankhede if (mdev_state->s[index].rxtx.count <
3519d1a546cSKirti Wankhede mdev_state->s[index].max_fifo_size) {
3529d1a546cSKirti Wankhede mdev_state->s[index].rxtx.fifo[
3539d1a546cSKirti Wankhede mdev_state->s[index].rxtx.head] = data;
3549d1a546cSKirti Wankhede mdev_state->s[index].rxtx.count++;
3559d1a546cSKirti Wankhede CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.head);
3569d1a546cSKirti Wankhede mdev_state->s[index].overrun = false;
3579d1a546cSKirti Wankhede
3589d1a546cSKirti Wankhede /*
3599d1a546cSKirti Wankhede * Trigger interrupt if receive data interrupt is
3609d1a546cSKirti Wankhede * enabled and fifo reached trigger level
3619d1a546cSKirti Wankhede */
3629d1a546cSKirti Wankhede if ((mdev_state->s[index].uart_reg[UART_IER] &
3639d1a546cSKirti Wankhede UART_IER_RDI) &&
3649d1a546cSKirti Wankhede (mdev_state->s[index].rxtx.count ==
3659d1a546cSKirti Wankhede mdev_state->s[index].intr_trigger_level)) {
3669d1a546cSKirti Wankhede /* trigger interrupt */
3679d1a546cSKirti Wankhede #if defined(DEBUG_INTR)
3689d1a546cSKirti Wankhede pr_err("Serial port %d: Fifo level trigger\n",
3699d1a546cSKirti Wankhede index);
3709d1a546cSKirti Wankhede #endif
371eee413e6SParav Pandit mtty_trigger_interrupt(mdev_state);
3729d1a546cSKirti Wankhede }
3739d1a546cSKirti Wankhede } else {
3749d1a546cSKirti Wankhede #if defined(DEBUG_INTR)
3759d1a546cSKirti Wankhede pr_err("Serial port %d: Buffer Overflow\n", index);
3769d1a546cSKirti Wankhede #endif
3779d1a546cSKirti Wankhede mdev_state->s[index].overrun = true;
3789d1a546cSKirti Wankhede
3799d1a546cSKirti Wankhede /*
3809d1a546cSKirti Wankhede * Trigger interrupt if receiver line status interrupt
3819d1a546cSKirti Wankhede * is enabled
3829d1a546cSKirti Wankhede */
3839d1a546cSKirti Wankhede if (mdev_state->s[index].uart_reg[UART_IER] &
3849d1a546cSKirti Wankhede UART_IER_RLSI)
385eee413e6SParav Pandit mtty_trigger_interrupt(mdev_state);
3869d1a546cSKirti Wankhede }
3879d1a546cSKirti Wankhede mutex_unlock(&mdev_state->rxtx_lock);
3889d1a546cSKirti Wankhede break;
3899d1a546cSKirti Wankhede
3909d1a546cSKirti Wankhede case UART_IER:
3919d1a546cSKirti Wankhede /* if DLAB set, data is MSB of divisor */
3929d1a546cSKirti Wankhede if (mdev_state->s[index].dlab)
3939d1a546cSKirti Wankhede mdev_state->s[index].divisor |= (u16)data << 8;
3949d1a546cSKirti Wankhede else {
3959d1a546cSKirti Wankhede mdev_state->s[index].uart_reg[offset] = data;
3969d1a546cSKirti Wankhede mutex_lock(&mdev_state->rxtx_lock);
3979d1a546cSKirti Wankhede if ((data & UART_IER_THRI) &&
3989d1a546cSKirti Wankhede (mdev_state->s[index].rxtx.head ==
3999d1a546cSKirti Wankhede mdev_state->s[index].rxtx.tail)) {
4009d1a546cSKirti Wankhede #if defined(DEBUG_INTR)
4019d1a546cSKirti Wankhede pr_err("Serial port %d: IER_THRI write\n",
4029d1a546cSKirti Wankhede index);
4039d1a546cSKirti Wankhede #endif
404eee413e6SParav Pandit mtty_trigger_interrupt(mdev_state);
4059d1a546cSKirti Wankhede }
4069d1a546cSKirti Wankhede
4079d1a546cSKirti Wankhede mutex_unlock(&mdev_state->rxtx_lock);
4089d1a546cSKirti Wankhede }
4099d1a546cSKirti Wankhede
4109d1a546cSKirti Wankhede break;
4119d1a546cSKirti Wankhede
4129d1a546cSKirti Wankhede case UART_FCR:
4139d1a546cSKirti Wankhede mdev_state->s[index].fcr = data;
4149d1a546cSKirti Wankhede
4159d1a546cSKirti Wankhede mutex_lock(&mdev_state->rxtx_lock);
4169d1a546cSKirti Wankhede if (data & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT)) {
4179d1a546cSKirti Wankhede /* clear loop back FIFO */
4189d1a546cSKirti Wankhede mdev_state->s[index].rxtx.count = 0;
4199d1a546cSKirti Wankhede mdev_state->s[index].rxtx.head = 0;
4209d1a546cSKirti Wankhede mdev_state->s[index].rxtx.tail = 0;
4219d1a546cSKirti Wankhede }
4229d1a546cSKirti Wankhede mutex_unlock(&mdev_state->rxtx_lock);
4239d1a546cSKirti Wankhede
4249d1a546cSKirti Wankhede switch (data & UART_FCR_TRIGGER_MASK) {
4259d1a546cSKirti Wankhede case UART_FCR_TRIGGER_1:
4269d1a546cSKirti Wankhede mdev_state->s[index].intr_trigger_level = 1;
4279d1a546cSKirti Wankhede break;
4289d1a546cSKirti Wankhede
4299d1a546cSKirti Wankhede case UART_FCR_TRIGGER_4:
4309d1a546cSKirti Wankhede mdev_state->s[index].intr_trigger_level = 4;
4319d1a546cSKirti Wankhede break;
4329d1a546cSKirti Wankhede
4339d1a546cSKirti Wankhede case UART_FCR_TRIGGER_8:
4349d1a546cSKirti Wankhede mdev_state->s[index].intr_trigger_level = 8;
4359d1a546cSKirti Wankhede break;
4369d1a546cSKirti Wankhede
4379d1a546cSKirti Wankhede case UART_FCR_TRIGGER_14:
4389d1a546cSKirti Wankhede mdev_state->s[index].intr_trigger_level = 14;
4399d1a546cSKirti Wankhede break;
4409d1a546cSKirti Wankhede }
4419d1a546cSKirti Wankhede
4429d1a546cSKirti Wankhede /*
4439d1a546cSKirti Wankhede * Set trigger level to 1 otherwise or implement timer with
4449d1a546cSKirti Wankhede * timeout of 4 characters and on expiring that timer set
4459d1a546cSKirti Wankhede * Recevice data timeout in IIR register
4469d1a546cSKirti Wankhede */
4479d1a546cSKirti Wankhede mdev_state->s[index].intr_trigger_level = 1;
4489d1a546cSKirti Wankhede if (data & UART_FCR_ENABLE_FIFO)
4499d1a546cSKirti Wankhede mdev_state->s[index].max_fifo_size = MAX_FIFO_SIZE;
4509d1a546cSKirti Wankhede else {
4519d1a546cSKirti Wankhede mdev_state->s[index].max_fifo_size = 1;
4529d1a546cSKirti Wankhede mdev_state->s[index].intr_trigger_level = 1;
4539d1a546cSKirti Wankhede }
4549d1a546cSKirti Wankhede
4559d1a546cSKirti Wankhede break;
4569d1a546cSKirti Wankhede
4579d1a546cSKirti Wankhede case UART_LCR:
4589d1a546cSKirti Wankhede if (data & UART_LCR_DLAB) {
4599d1a546cSKirti Wankhede mdev_state->s[index].dlab = true;
4609d1a546cSKirti Wankhede mdev_state->s[index].divisor = 0;
4619d1a546cSKirti Wankhede } else
4629d1a546cSKirti Wankhede mdev_state->s[index].dlab = false;
4639d1a546cSKirti Wankhede
4649d1a546cSKirti Wankhede mdev_state->s[index].uart_reg[offset] = data;
4659d1a546cSKirti Wankhede break;
4669d1a546cSKirti Wankhede
4679d1a546cSKirti Wankhede case UART_MCR:
4689d1a546cSKirti Wankhede mdev_state->s[index].uart_reg[offset] = data;
4699d1a546cSKirti Wankhede
4709d1a546cSKirti Wankhede if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
4719d1a546cSKirti Wankhede (data & UART_MCR_OUT2)) {
4729d1a546cSKirti Wankhede #if defined(DEBUG_INTR)
4739d1a546cSKirti Wankhede pr_err("Serial port %d: MCR_OUT2 write\n", index);
4749d1a546cSKirti Wankhede #endif
475eee413e6SParav Pandit mtty_trigger_interrupt(mdev_state);
4769d1a546cSKirti Wankhede }
4779d1a546cSKirti Wankhede
4789d1a546cSKirti Wankhede if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
4799d1a546cSKirti Wankhede (data & (UART_MCR_RTS | UART_MCR_DTR))) {
4809d1a546cSKirti Wankhede #if defined(DEBUG_INTR)
4819d1a546cSKirti Wankhede pr_err("Serial port %d: MCR RTS/DTR write\n", index);
4829d1a546cSKirti Wankhede #endif
483eee413e6SParav Pandit mtty_trigger_interrupt(mdev_state);
4849d1a546cSKirti Wankhede }
4859d1a546cSKirti Wankhede break;
4869d1a546cSKirti Wankhede
4879d1a546cSKirti Wankhede case UART_LSR:
4889d1a546cSKirti Wankhede case UART_MSR:
4899d1a546cSKirti Wankhede /* do nothing */
4909d1a546cSKirti Wankhede break;
4919d1a546cSKirti Wankhede
4929d1a546cSKirti Wankhede case UART_SCR:
4939d1a546cSKirti Wankhede mdev_state->s[index].uart_reg[offset] = data;
4949d1a546cSKirti Wankhede break;
4959d1a546cSKirti Wankhede
4969d1a546cSKirti Wankhede default:
4979d1a546cSKirti Wankhede break;
4989d1a546cSKirti Wankhede }
4999d1a546cSKirti Wankhede }
5009d1a546cSKirti Wankhede
handle_bar_read(unsigned int index,struct mdev_state * mdev_state,u16 offset,u8 * buf,u32 count)5019d1a546cSKirti Wankhede static void handle_bar_read(unsigned int index, struct mdev_state *mdev_state,
5028ba35b3aSNathan Chancellor u16 offset, u8 *buf, u32 count)
5039d1a546cSKirti Wankhede {
5049d1a546cSKirti Wankhede /* Handle read requests by guest */
5059d1a546cSKirti Wankhede switch (offset) {
5069d1a546cSKirti Wankhede case UART_RX:
5079d1a546cSKirti Wankhede /* if DLAB set, data is LSB of divisor */
5089d1a546cSKirti Wankhede if (mdev_state->s[index].dlab) {
5099d1a546cSKirti Wankhede *buf = (u8)mdev_state->s[index].divisor;
5109d1a546cSKirti Wankhede break;
5119d1a546cSKirti Wankhede }
5129d1a546cSKirti Wankhede
5139d1a546cSKirti Wankhede mutex_lock(&mdev_state->rxtx_lock);
5149d1a546cSKirti Wankhede /* return data in tx buffer */
5159d1a546cSKirti Wankhede if (mdev_state->s[index].rxtx.head !=
5169d1a546cSKirti Wankhede mdev_state->s[index].rxtx.tail) {
5179d1a546cSKirti Wankhede *buf = mdev_state->s[index].rxtx.fifo[
5189d1a546cSKirti Wankhede mdev_state->s[index].rxtx.tail];
5199d1a546cSKirti Wankhede mdev_state->s[index].rxtx.count--;
5209d1a546cSKirti Wankhede CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.tail);
5219d1a546cSKirti Wankhede }
5229d1a546cSKirti Wankhede
5239d1a546cSKirti Wankhede if (mdev_state->s[index].rxtx.head ==
5249d1a546cSKirti Wankhede mdev_state->s[index].rxtx.tail) {
5259d1a546cSKirti Wankhede /*
5269d1a546cSKirti Wankhede * Trigger interrupt if tx buffer empty interrupt is
5279d1a546cSKirti Wankhede * enabled and fifo is empty
5289d1a546cSKirti Wankhede */
5299d1a546cSKirti Wankhede #if defined(DEBUG_INTR)
5309d1a546cSKirti Wankhede pr_err("Serial port %d: Buffer Empty\n", index);
5319d1a546cSKirti Wankhede #endif
5329d1a546cSKirti Wankhede if (mdev_state->s[index].uart_reg[UART_IER] &
5339d1a546cSKirti Wankhede UART_IER_THRI)
534eee413e6SParav Pandit mtty_trigger_interrupt(mdev_state);
5359d1a546cSKirti Wankhede }
5369d1a546cSKirti Wankhede mutex_unlock(&mdev_state->rxtx_lock);
5379d1a546cSKirti Wankhede
5389d1a546cSKirti Wankhede break;
5399d1a546cSKirti Wankhede
5409d1a546cSKirti Wankhede case UART_IER:
5419d1a546cSKirti Wankhede if (mdev_state->s[index].dlab) {
5429d1a546cSKirti Wankhede *buf = (u8)(mdev_state->s[index].divisor >> 8);
5439d1a546cSKirti Wankhede break;
5449d1a546cSKirti Wankhede }
5459d1a546cSKirti Wankhede *buf = mdev_state->s[index].uart_reg[offset] & 0x0f;
5469d1a546cSKirti Wankhede break;
5479d1a546cSKirti Wankhede
5489d1a546cSKirti Wankhede case UART_IIR:
5499d1a546cSKirti Wankhede {
5509d1a546cSKirti Wankhede u8 ier = mdev_state->s[index].uart_reg[UART_IER];
5519d1a546cSKirti Wankhede *buf = 0;
5529d1a546cSKirti Wankhede
5539d1a546cSKirti Wankhede mutex_lock(&mdev_state->rxtx_lock);
5549d1a546cSKirti Wankhede /* Interrupt priority 1: Parity, overrun, framing or break */
5559d1a546cSKirti Wankhede if ((ier & UART_IER_RLSI) && mdev_state->s[index].overrun)
5569d1a546cSKirti Wankhede *buf |= UART_IIR_RLSI;
5579d1a546cSKirti Wankhede
5589d1a546cSKirti Wankhede /* Interrupt priority 2: Fifo trigger level reached */
5599d1a546cSKirti Wankhede if ((ier & UART_IER_RDI) &&
560c9f89c3fSShunyong Yang (mdev_state->s[index].rxtx.count >=
5619d1a546cSKirti Wankhede mdev_state->s[index].intr_trigger_level))
5629d1a546cSKirti Wankhede *buf |= UART_IIR_RDI;
5639d1a546cSKirti Wankhede
5649d1a546cSKirti Wankhede /* Interrupt priotiry 3: transmitter holding register empty */
5659d1a546cSKirti Wankhede if ((ier & UART_IER_THRI) &&
5669d1a546cSKirti Wankhede (mdev_state->s[index].rxtx.head ==
5679d1a546cSKirti Wankhede mdev_state->s[index].rxtx.tail))
5689d1a546cSKirti Wankhede *buf |= UART_IIR_THRI;
5699d1a546cSKirti Wankhede
5709d1a546cSKirti Wankhede /* Interrupt priotiry 4: Modem status: CTS, DSR, RI or DCD */
5719d1a546cSKirti Wankhede if ((ier & UART_IER_MSI) &&
5729d1a546cSKirti Wankhede (mdev_state->s[index].uart_reg[UART_MCR] &
5739d1a546cSKirti Wankhede (UART_MCR_RTS | UART_MCR_DTR)))
5749d1a546cSKirti Wankhede *buf |= UART_IIR_MSI;
5759d1a546cSKirti Wankhede
5769d1a546cSKirti Wankhede /* bit0: 0=> interrupt pending, 1=> no interrupt is pending */
5779d1a546cSKirti Wankhede if (*buf == 0)
5789d1a546cSKirti Wankhede *buf = UART_IIR_NO_INT;
5799d1a546cSKirti Wankhede
5809d1a546cSKirti Wankhede /* set bit 6 & 7 to be 16550 compatible */
5819d1a546cSKirti Wankhede *buf |= 0xC0;
5829d1a546cSKirti Wankhede mutex_unlock(&mdev_state->rxtx_lock);
5839d1a546cSKirti Wankhede }
5849d1a546cSKirti Wankhede break;
5859d1a546cSKirti Wankhede
5869d1a546cSKirti Wankhede case UART_LCR:
5879d1a546cSKirti Wankhede case UART_MCR:
5889d1a546cSKirti Wankhede *buf = mdev_state->s[index].uart_reg[offset];
5899d1a546cSKirti Wankhede break;
5909d1a546cSKirti Wankhede
5919d1a546cSKirti Wankhede case UART_LSR:
5929d1a546cSKirti Wankhede {
5939d1a546cSKirti Wankhede u8 lsr = 0;
5949d1a546cSKirti Wankhede
5959d1a546cSKirti Wankhede mutex_lock(&mdev_state->rxtx_lock);
5969d1a546cSKirti Wankhede /* atleast one char in FIFO */
5979d1a546cSKirti Wankhede if (mdev_state->s[index].rxtx.head !=
5989d1a546cSKirti Wankhede mdev_state->s[index].rxtx.tail)
5999d1a546cSKirti Wankhede lsr |= UART_LSR_DR;
6009d1a546cSKirti Wankhede
6019d1a546cSKirti Wankhede /* if FIFO overrun */
6029d1a546cSKirti Wankhede if (mdev_state->s[index].overrun)
6039d1a546cSKirti Wankhede lsr |= UART_LSR_OE;
6049d1a546cSKirti Wankhede
6059d1a546cSKirti Wankhede /* transmit FIFO empty and tramsitter empty */
6069d1a546cSKirti Wankhede if (mdev_state->s[index].rxtx.head ==
6079d1a546cSKirti Wankhede mdev_state->s[index].rxtx.tail)
6089d1a546cSKirti Wankhede lsr |= UART_LSR_TEMT | UART_LSR_THRE;
6099d1a546cSKirti Wankhede
6109d1a546cSKirti Wankhede mutex_unlock(&mdev_state->rxtx_lock);
6119d1a546cSKirti Wankhede *buf = lsr;
6129d1a546cSKirti Wankhede break;
6139d1a546cSKirti Wankhede }
6149d1a546cSKirti Wankhede case UART_MSR:
6159d1a546cSKirti Wankhede *buf = UART_MSR_DSR | UART_MSR_DDSR | UART_MSR_DCD;
6169d1a546cSKirti Wankhede
6179d1a546cSKirti Wankhede mutex_lock(&mdev_state->rxtx_lock);
6189d1a546cSKirti Wankhede /* if AFE is 1 and FIFO have space, set CTS bit */
6199d1a546cSKirti Wankhede if (mdev_state->s[index].uart_reg[UART_MCR] &
6209d1a546cSKirti Wankhede UART_MCR_AFE) {
6219d1a546cSKirti Wankhede if (mdev_state->s[index].rxtx.count <
6229d1a546cSKirti Wankhede mdev_state->s[index].max_fifo_size)
6239d1a546cSKirti Wankhede *buf |= UART_MSR_CTS | UART_MSR_DCTS;
6249d1a546cSKirti Wankhede } else
6259d1a546cSKirti Wankhede *buf |= UART_MSR_CTS | UART_MSR_DCTS;
6269d1a546cSKirti Wankhede mutex_unlock(&mdev_state->rxtx_lock);
6279d1a546cSKirti Wankhede
6289d1a546cSKirti Wankhede break;
6299d1a546cSKirti Wankhede
6309d1a546cSKirti Wankhede case UART_SCR:
6319d1a546cSKirti Wankhede *buf = mdev_state->s[index].uart_reg[offset];
6329d1a546cSKirti Wankhede break;
6339d1a546cSKirti Wankhede
6349d1a546cSKirti Wankhede default:
6359d1a546cSKirti Wankhede break;
6369d1a546cSKirti Wankhede }
6379d1a546cSKirti Wankhede }
6389d1a546cSKirti Wankhede
mdev_read_base(struct mdev_state * mdev_state)6399d1a546cSKirti Wankhede static void mdev_read_base(struct mdev_state *mdev_state)
6409d1a546cSKirti Wankhede {
6419d1a546cSKirti Wankhede int index, pos;
6429d1a546cSKirti Wankhede u32 start_lo, start_hi;
6439d1a546cSKirti Wankhede u32 mem_type;
6449d1a546cSKirti Wankhede
6459d1a546cSKirti Wankhede pos = PCI_BASE_ADDRESS_0;
6469d1a546cSKirti Wankhede
6479d1a546cSKirti Wankhede for (index = 0; index <= VFIO_PCI_BAR5_REGION_INDEX; index++) {
6489d1a546cSKirti Wankhede
6499d1a546cSKirti Wankhede if (!mdev_state->region_info[index].size)
6509d1a546cSKirti Wankhede continue;
6519d1a546cSKirti Wankhede
6529d1a546cSKirti Wankhede start_lo = (*(u32 *)(mdev_state->vconfig + pos)) &
6539d1a546cSKirti Wankhede PCI_BASE_ADDRESS_MEM_MASK;
6549d1a546cSKirti Wankhede mem_type = (*(u32 *)(mdev_state->vconfig + pos)) &
6559d1a546cSKirti Wankhede PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6569d1a546cSKirti Wankhede
6579d1a546cSKirti Wankhede switch (mem_type) {
6589d1a546cSKirti Wankhede case PCI_BASE_ADDRESS_MEM_TYPE_64:
6599d1a546cSKirti Wankhede start_hi = (*(u32 *)(mdev_state->vconfig + pos + 4));
6609d1a546cSKirti Wankhede pos += 4;
6619d1a546cSKirti Wankhede break;
6629d1a546cSKirti Wankhede case PCI_BASE_ADDRESS_MEM_TYPE_32:
6639d1a546cSKirti Wankhede case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6649d1a546cSKirti Wankhede /* 1M mem BAR treated as 32-bit BAR */
6659d1a546cSKirti Wankhede default:
6669d1a546cSKirti Wankhede /* mem unknown type treated as 32-bit BAR */
6679d1a546cSKirti Wankhede start_hi = 0;
6689d1a546cSKirti Wankhede break;
6699d1a546cSKirti Wankhede }
6709d1a546cSKirti Wankhede pos += 4;
6719d1a546cSKirti Wankhede mdev_state->region_info[index].start = ((u64)start_hi << 32) |
6729d1a546cSKirti Wankhede start_lo;
6739d1a546cSKirti Wankhede }
6749d1a546cSKirti Wankhede }
6759d1a546cSKirti Wankhede
mdev_access(struct mdev_state * mdev_state,u8 * buf,size_t count,loff_t pos,bool is_write)67609177ac9SJason Gunthorpe static ssize_t mdev_access(struct mdev_state *mdev_state, u8 *buf, size_t count,
6779d1a546cSKirti Wankhede loff_t pos, bool is_write)
6789d1a546cSKirti Wankhede {
6799d1a546cSKirti Wankhede unsigned int index;
6809d1a546cSKirti Wankhede loff_t offset;
6819d1a546cSKirti Wankhede int ret = 0;
6829d1a546cSKirti Wankhede
68309177ac9SJason Gunthorpe if (!buf)
6849d1a546cSKirti Wankhede return -EINVAL;
6859d1a546cSKirti Wankhede
6869d1a546cSKirti Wankhede mutex_lock(&mdev_state->ops_lock);
6879d1a546cSKirti Wankhede
6889d1a546cSKirti Wankhede index = MTTY_VFIO_PCI_OFFSET_TO_INDEX(pos);
6899d1a546cSKirti Wankhede offset = pos & MTTY_VFIO_PCI_OFFSET_MASK;
6909d1a546cSKirti Wankhede switch (index) {
6919d1a546cSKirti Wankhede case VFIO_PCI_CONFIG_REGION_INDEX:
6929d1a546cSKirti Wankhede
6939d1a546cSKirti Wankhede #if defined(DEBUG)
6949d1a546cSKirti Wankhede pr_info("%s: PCI config space %s at offset 0x%llx\n",
6959d1a546cSKirti Wankhede __func__, is_write ? "write" : "read", offset);
6969d1a546cSKirti Wankhede #endif
6979d1a546cSKirti Wankhede if (is_write) {
6989d1a546cSKirti Wankhede dump_buffer(buf, count);
6999d1a546cSKirti Wankhede handle_pci_cfg_write(mdev_state, offset, buf, count);
7009d1a546cSKirti Wankhede } else {
7019d1a546cSKirti Wankhede memcpy(buf, (mdev_state->vconfig + offset), count);
7029d1a546cSKirti Wankhede dump_buffer(buf, count);
7039d1a546cSKirti Wankhede }
7049d1a546cSKirti Wankhede
7059d1a546cSKirti Wankhede break;
7069d1a546cSKirti Wankhede
7079d1a546cSKirti Wankhede case VFIO_PCI_BAR0_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX:
7089d1a546cSKirti Wankhede if (!mdev_state->region_info[index].start)
7099d1a546cSKirti Wankhede mdev_read_base(mdev_state);
7109d1a546cSKirti Wankhede
7119d1a546cSKirti Wankhede if (is_write) {
7129d1a546cSKirti Wankhede dump_buffer(buf, count);
7139d1a546cSKirti Wankhede
7149d1a546cSKirti Wankhede #if defined(DEBUG_REGS)
7159d1a546cSKirti Wankhede pr_info("%s: BAR%d WR @0x%llx %s val:0x%02x dlab:%d\n",
7169d1a546cSKirti Wankhede __func__, index, offset, wr_reg[offset],
7178ba35b3aSNathan Chancellor *buf, mdev_state->s[index].dlab);
7189d1a546cSKirti Wankhede #endif
7199d1a546cSKirti Wankhede handle_bar_write(index, mdev_state, offset, buf, count);
7209d1a546cSKirti Wankhede } else {
7219d1a546cSKirti Wankhede handle_bar_read(index, mdev_state, offset, buf, count);
7229d1a546cSKirti Wankhede dump_buffer(buf, count);
7239d1a546cSKirti Wankhede
7249d1a546cSKirti Wankhede #if defined(DEBUG_REGS)
7259d1a546cSKirti Wankhede pr_info("%s: BAR%d RD @0x%llx %s val:0x%02x dlab:%d\n",
7269d1a546cSKirti Wankhede __func__, index, offset, rd_reg[offset],
7278ba35b3aSNathan Chancellor *buf, mdev_state->s[index].dlab);
7289d1a546cSKirti Wankhede #endif
7299d1a546cSKirti Wankhede }
7309d1a546cSKirti Wankhede break;
7319d1a546cSKirti Wankhede
7329d1a546cSKirti Wankhede default:
7339d1a546cSKirti Wankhede ret = -1;
7349d1a546cSKirti Wankhede goto accessfailed;
7359d1a546cSKirti Wankhede }
7369d1a546cSKirti Wankhede
7379d1a546cSKirti Wankhede ret = count;
7389d1a546cSKirti Wankhede
7399d1a546cSKirti Wankhede
7409d1a546cSKirti Wankhede accessfailed:
7419d1a546cSKirti Wankhede mutex_unlock(&mdev_state->ops_lock);
7429d1a546cSKirti Wankhede
7439d1a546cSKirti Wankhede return ret;
7449d1a546cSKirti Wankhede }
7459d1a546cSKirti Wankhede
mtty_init_dev(struct vfio_device * vdev)74667c5a181SYi Liu static int mtty_init_dev(struct vfio_device *vdev)
7479d1a546cSKirti Wankhede {
74867c5a181SYi Liu struct mdev_state *mdev_state =
74967c5a181SYi Liu container_of(vdev, struct mdev_state, vdev);
75067c5a181SYi Liu struct mdev_device *mdev = to_mdev_device(vdev->dev);
751da44c340SChristoph Hellwig struct mtty_type *type =
752da44c340SChristoph Hellwig container_of(mdev->type, struct mtty_type, type);
75397d0a687SAlex Williamson int avail_ports = atomic_read(&mdev_avail_ports);
75409177ac9SJason Gunthorpe int ret;
7559d1a546cSKirti Wankhede
75697d0a687SAlex Williamson do {
757da44c340SChristoph Hellwig if (avail_ports < type->nr_ports)
75897d0a687SAlex Williamson return -ENOSPC;
75997d0a687SAlex Williamson } while (!atomic_try_cmpxchg(&mdev_avail_ports,
760da44c340SChristoph Hellwig &avail_ports,
761da44c340SChristoph Hellwig avail_ports - type->nr_ports));
76297d0a687SAlex Williamson
763da44c340SChristoph Hellwig mdev_state->nr_ports = type->nr_ports;
7649d1a546cSKirti Wankhede mdev_state->irq_index = -1;
7659d1a546cSKirti Wankhede mdev_state->s[0].max_fifo_size = MAX_FIFO_SIZE;
7669d1a546cSKirti Wankhede mdev_state->s[1].max_fifo_size = MAX_FIFO_SIZE;
7679d1a546cSKirti Wankhede mutex_init(&mdev_state->rxtx_lock);
7689d1a546cSKirti Wankhede
76967c5a181SYi Liu mdev_state->vconfig = kzalloc(MTTY_CONFIG_SPACE_SIZE, GFP_KERNEL);
77067c5a181SYi Liu if (!mdev_state->vconfig) {
771ae03c377SMax Gurtovoy ret = -ENOMEM;
77267c5a181SYi Liu goto err_nr_ports;
7739d1a546cSKirti Wankhede }
7749d1a546cSKirti Wankhede
7759d1a546cSKirti Wankhede mutex_init(&mdev_state->ops_lock);
7769d1a546cSKirti Wankhede mdev_state->mdev = mdev;
7779d1a546cSKirti Wankhede mtty_create_config_space(mdev_state);
7789d1a546cSKirti Wankhede return 0;
779ae03c377SMax Gurtovoy
780ae03c377SMax Gurtovoy err_nr_ports:
781da44c340SChristoph Hellwig atomic_add(type->nr_ports, &mdev_avail_ports);
782ae03c377SMax Gurtovoy return ret;
7839d1a546cSKirti Wankhede }
7849d1a546cSKirti Wankhede
mtty_probe(struct mdev_device * mdev)78567c5a181SYi Liu static int mtty_probe(struct mdev_device *mdev)
78667c5a181SYi Liu {
78767c5a181SYi Liu struct mdev_state *mdev_state;
78867c5a181SYi Liu int ret;
78967c5a181SYi Liu
79067c5a181SYi Liu mdev_state = vfio_alloc_device(mdev_state, vdev, &mdev->dev,
79167c5a181SYi Liu &mtty_dev_ops);
79267c5a181SYi Liu if (IS_ERR(mdev_state))
79367c5a181SYi Liu return PTR_ERR(mdev_state);
79467c5a181SYi Liu
79567c5a181SYi Liu ret = vfio_register_emulated_iommu_dev(&mdev_state->vdev);
79667c5a181SYi Liu if (ret)
79767c5a181SYi Liu goto err_put_vdev;
79867c5a181SYi Liu dev_set_drvdata(&mdev->dev, mdev_state);
79967c5a181SYi Liu return 0;
80067c5a181SYi Liu
80167c5a181SYi Liu err_put_vdev:
80267c5a181SYi Liu vfio_put_device(&mdev_state->vdev);
80367c5a181SYi Liu return ret;
80467c5a181SYi Liu }
80567c5a181SYi Liu
mtty_release_dev(struct vfio_device * vdev)80667c5a181SYi Liu static void mtty_release_dev(struct vfio_device *vdev)
80767c5a181SYi Liu {
80867c5a181SYi Liu struct mdev_state *mdev_state =
80967c5a181SYi Liu container_of(vdev, struct mdev_state, vdev);
81067c5a181SYi Liu
81167c5a181SYi Liu atomic_add(mdev_state->nr_ports, &mdev_avail_ports);
81267c5a181SYi Liu kfree(mdev_state->vconfig);
81367c5a181SYi Liu }
81467c5a181SYi Liu
mtty_remove(struct mdev_device * mdev)81509177ac9SJason Gunthorpe static void mtty_remove(struct mdev_device *mdev)
8169d1a546cSKirti Wankhede {
81709177ac9SJason Gunthorpe struct mdev_state *mdev_state = dev_get_drvdata(&mdev->dev);
8189d1a546cSKirti Wankhede
81909177ac9SJason Gunthorpe vfio_unregister_group_dev(&mdev_state->vdev);
82067c5a181SYi Liu vfio_put_device(&mdev_state->vdev);
8219d1a546cSKirti Wankhede }
8229d1a546cSKirti Wankhede
mtty_reset(struct mdev_state * mdev_state)82309177ac9SJason Gunthorpe static int mtty_reset(struct mdev_state *mdev_state)
8249d1a546cSKirti Wankhede {
8259d1a546cSKirti Wankhede pr_info("%s: called\n", __func__);
8269d1a546cSKirti Wankhede
8279d1a546cSKirti Wankhede return 0;
8289d1a546cSKirti Wankhede }
8299d1a546cSKirti Wankhede
mtty_read(struct vfio_device * vdev,char __user * buf,size_t count,loff_t * ppos)83009177ac9SJason Gunthorpe static ssize_t mtty_read(struct vfio_device *vdev, char __user *buf,
8314b2dbd56SKefeng Wang size_t count, loff_t *ppos)
8329d1a546cSKirti Wankhede {
83309177ac9SJason Gunthorpe struct mdev_state *mdev_state =
83409177ac9SJason Gunthorpe container_of(vdev, struct mdev_state, vdev);
8359d1a546cSKirti Wankhede unsigned int done = 0;
8369d1a546cSKirti Wankhede int ret;
8379d1a546cSKirti Wankhede
8389d1a546cSKirti Wankhede while (count) {
8399d1a546cSKirti Wankhede size_t filled;
8409d1a546cSKirti Wankhede
8419d1a546cSKirti Wankhede if (count >= 4 && !(*ppos % 4)) {
8429d1a546cSKirti Wankhede u32 val;
8439d1a546cSKirti Wankhede
84409177ac9SJason Gunthorpe ret = mdev_access(mdev_state, (u8 *)&val, sizeof(val),
8459d1a546cSKirti Wankhede *ppos, false);
8469d1a546cSKirti Wankhede if (ret <= 0)
8479d1a546cSKirti Wankhede goto read_err;
8489d1a546cSKirti Wankhede
8499d1a546cSKirti Wankhede if (copy_to_user(buf, &val, sizeof(val)))
8509d1a546cSKirti Wankhede goto read_err;
8519d1a546cSKirti Wankhede
8529d1a546cSKirti Wankhede filled = 4;
8539d1a546cSKirti Wankhede } else if (count >= 2 && !(*ppos % 2)) {
8549d1a546cSKirti Wankhede u16 val;
8559d1a546cSKirti Wankhede
85609177ac9SJason Gunthorpe ret = mdev_access(mdev_state, (u8 *)&val, sizeof(val),
8579d1a546cSKirti Wankhede *ppos, false);
8589d1a546cSKirti Wankhede if (ret <= 0)
8599d1a546cSKirti Wankhede goto read_err;
8609d1a546cSKirti Wankhede
8619d1a546cSKirti Wankhede if (copy_to_user(buf, &val, sizeof(val)))
8629d1a546cSKirti Wankhede goto read_err;
8639d1a546cSKirti Wankhede
8649d1a546cSKirti Wankhede filled = 2;
8659d1a546cSKirti Wankhede } else {
8669d1a546cSKirti Wankhede u8 val;
8679d1a546cSKirti Wankhede
86809177ac9SJason Gunthorpe ret = mdev_access(mdev_state, (u8 *)&val, sizeof(val),
8699d1a546cSKirti Wankhede *ppos, false);
8709d1a546cSKirti Wankhede if (ret <= 0)
8719d1a546cSKirti Wankhede goto read_err;
8729d1a546cSKirti Wankhede
8739d1a546cSKirti Wankhede if (copy_to_user(buf, &val, sizeof(val)))
8749d1a546cSKirti Wankhede goto read_err;
8759d1a546cSKirti Wankhede
8769d1a546cSKirti Wankhede filled = 1;
8779d1a546cSKirti Wankhede }
8789d1a546cSKirti Wankhede
8799d1a546cSKirti Wankhede count -= filled;
8809d1a546cSKirti Wankhede done += filled;
8819d1a546cSKirti Wankhede *ppos += filled;
8829d1a546cSKirti Wankhede buf += filled;
8839d1a546cSKirti Wankhede }
8849d1a546cSKirti Wankhede
8859d1a546cSKirti Wankhede return done;
8869d1a546cSKirti Wankhede
8879d1a546cSKirti Wankhede read_err:
8889d1a546cSKirti Wankhede return -EFAULT;
8899d1a546cSKirti Wankhede }
8909d1a546cSKirti Wankhede
mtty_write(struct vfio_device * vdev,const char __user * buf,size_t count,loff_t * ppos)89109177ac9SJason Gunthorpe static ssize_t mtty_write(struct vfio_device *vdev, const char __user *buf,
8929d1a546cSKirti Wankhede size_t count, loff_t *ppos)
8939d1a546cSKirti Wankhede {
89409177ac9SJason Gunthorpe struct mdev_state *mdev_state =
89509177ac9SJason Gunthorpe container_of(vdev, struct mdev_state, vdev);
8969d1a546cSKirti Wankhede unsigned int done = 0;
8979d1a546cSKirti Wankhede int ret;
8989d1a546cSKirti Wankhede
8999d1a546cSKirti Wankhede while (count) {
9009d1a546cSKirti Wankhede size_t filled;
9019d1a546cSKirti Wankhede
9029d1a546cSKirti Wankhede if (count >= 4 && !(*ppos % 4)) {
9039d1a546cSKirti Wankhede u32 val;
9049d1a546cSKirti Wankhede
9059d1a546cSKirti Wankhede if (copy_from_user(&val, buf, sizeof(val)))
9069d1a546cSKirti Wankhede goto write_err;
9079d1a546cSKirti Wankhede
90809177ac9SJason Gunthorpe ret = mdev_access(mdev_state, (u8 *)&val, sizeof(val),
9099d1a546cSKirti Wankhede *ppos, true);
9109d1a546cSKirti Wankhede if (ret <= 0)
9119d1a546cSKirti Wankhede goto write_err;
9129d1a546cSKirti Wankhede
9139d1a546cSKirti Wankhede filled = 4;
9149d1a546cSKirti Wankhede } else if (count >= 2 && !(*ppos % 2)) {
9159d1a546cSKirti Wankhede u16 val;
9169d1a546cSKirti Wankhede
9179d1a546cSKirti Wankhede if (copy_from_user(&val, buf, sizeof(val)))
9189d1a546cSKirti Wankhede goto write_err;
9199d1a546cSKirti Wankhede
92009177ac9SJason Gunthorpe ret = mdev_access(mdev_state, (u8 *)&val, sizeof(val),
9219d1a546cSKirti Wankhede *ppos, true);
9229d1a546cSKirti Wankhede if (ret <= 0)
9239d1a546cSKirti Wankhede goto write_err;
9249d1a546cSKirti Wankhede
9259d1a546cSKirti Wankhede filled = 2;
9269d1a546cSKirti Wankhede } else {
9279d1a546cSKirti Wankhede u8 val;
9289d1a546cSKirti Wankhede
9299d1a546cSKirti Wankhede if (copy_from_user(&val, buf, sizeof(val)))
9309d1a546cSKirti Wankhede goto write_err;
9319d1a546cSKirti Wankhede
93209177ac9SJason Gunthorpe ret = mdev_access(mdev_state, (u8 *)&val, sizeof(val),
9339d1a546cSKirti Wankhede *ppos, true);
9349d1a546cSKirti Wankhede if (ret <= 0)
9359d1a546cSKirti Wankhede goto write_err;
9369d1a546cSKirti Wankhede
9379d1a546cSKirti Wankhede filled = 1;
9389d1a546cSKirti Wankhede }
9399d1a546cSKirti Wankhede count -= filled;
9409d1a546cSKirti Wankhede done += filled;
9419d1a546cSKirti Wankhede *ppos += filled;
9429d1a546cSKirti Wankhede buf += filled;
9439d1a546cSKirti Wankhede }
9449d1a546cSKirti Wankhede
9459d1a546cSKirti Wankhede return done;
9469d1a546cSKirti Wankhede write_err:
9479d1a546cSKirti Wankhede return -EFAULT;
9489d1a546cSKirti Wankhede }
9499d1a546cSKirti Wankhede
mtty_disable_intx(struct mdev_state * mdev_state)950*94eacb45SAlex Williamson static void mtty_disable_intx(struct mdev_state *mdev_state)
951*94eacb45SAlex Williamson {
952*94eacb45SAlex Williamson if (mdev_state->intx_evtfd) {
953*94eacb45SAlex Williamson eventfd_ctx_put(mdev_state->intx_evtfd);
954*94eacb45SAlex Williamson mdev_state->intx_evtfd = NULL;
955*94eacb45SAlex Williamson mdev_state->intx_mask = false;
956*94eacb45SAlex Williamson mdev_state->irq_index = -1;
957*94eacb45SAlex Williamson }
958*94eacb45SAlex Williamson }
959*94eacb45SAlex Williamson
mtty_disable_msi(struct mdev_state * mdev_state)960*94eacb45SAlex Williamson static void mtty_disable_msi(struct mdev_state *mdev_state)
961*94eacb45SAlex Williamson {
962*94eacb45SAlex Williamson if (mdev_state->msi_evtfd) {
963*94eacb45SAlex Williamson eventfd_ctx_put(mdev_state->msi_evtfd);
964*94eacb45SAlex Williamson mdev_state->msi_evtfd = NULL;
965*94eacb45SAlex Williamson mdev_state->irq_index = -1;
966*94eacb45SAlex Williamson }
967*94eacb45SAlex Williamson }
968*94eacb45SAlex Williamson
mtty_set_irqs(struct mdev_state * mdev_state,uint32_t flags,unsigned int index,unsigned int start,unsigned int count,void * data)96909177ac9SJason Gunthorpe static int mtty_set_irqs(struct mdev_state *mdev_state, uint32_t flags,
9709d1a546cSKirti Wankhede unsigned int index, unsigned int start,
9719d1a546cSKirti Wankhede unsigned int count, void *data)
9729d1a546cSKirti Wankhede {
9739d1a546cSKirti Wankhede int ret = 0;
9749d1a546cSKirti Wankhede
9759d1a546cSKirti Wankhede mutex_lock(&mdev_state->ops_lock);
9769d1a546cSKirti Wankhede switch (index) {
9779d1a546cSKirti Wankhede case VFIO_PCI_INTX_IRQ_INDEX:
9789d1a546cSKirti Wankhede switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) {
9799d1a546cSKirti Wankhede case VFIO_IRQ_SET_ACTION_MASK:
980*94eacb45SAlex Williamson if (!is_intx(mdev_state) || start != 0 || count != 1) {
981*94eacb45SAlex Williamson ret = -EINVAL;
982*94eacb45SAlex Williamson break;
983*94eacb45SAlex Williamson }
984*94eacb45SAlex Williamson
985*94eacb45SAlex Williamson if (flags & VFIO_IRQ_SET_DATA_NONE) {
986*94eacb45SAlex Williamson mdev_state->intx_mask = true;
987*94eacb45SAlex Williamson } else if (flags & VFIO_IRQ_SET_DATA_BOOL) {
988*94eacb45SAlex Williamson uint8_t mask = *(uint8_t *)data;
989*94eacb45SAlex Williamson
990*94eacb45SAlex Williamson if (mask)
991*94eacb45SAlex Williamson mdev_state->intx_mask = true;
992*94eacb45SAlex Williamson } else if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
993*94eacb45SAlex Williamson ret = -ENOTTY; /* No support for mask fd */
994*94eacb45SAlex Williamson }
995*94eacb45SAlex Williamson break;
9969d1a546cSKirti Wankhede case VFIO_IRQ_SET_ACTION_UNMASK:
997*94eacb45SAlex Williamson if (!is_intx(mdev_state) || start != 0 || count != 1) {
998*94eacb45SAlex Williamson ret = -EINVAL;
999*94eacb45SAlex Williamson break;
1000*94eacb45SAlex Williamson }
1001*94eacb45SAlex Williamson
1002*94eacb45SAlex Williamson if (flags & VFIO_IRQ_SET_DATA_NONE) {
1003*94eacb45SAlex Williamson mdev_state->intx_mask = false;
1004*94eacb45SAlex Williamson } else if (flags & VFIO_IRQ_SET_DATA_BOOL) {
1005*94eacb45SAlex Williamson uint8_t mask = *(uint8_t *)data;
1006*94eacb45SAlex Williamson
1007*94eacb45SAlex Williamson if (mask)
1008*94eacb45SAlex Williamson mdev_state->intx_mask = false;
1009*94eacb45SAlex Williamson } else if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
1010*94eacb45SAlex Williamson ret = -ENOTTY; /* No support for unmask fd */
1011*94eacb45SAlex Williamson }
10129d1a546cSKirti Wankhede break;
10139d1a546cSKirti Wankhede case VFIO_IRQ_SET_ACTION_TRIGGER:
1014*94eacb45SAlex Williamson if (is_intx(mdev_state) && !count &&
1015*94eacb45SAlex Williamson (flags & VFIO_IRQ_SET_DATA_NONE)) {
1016*94eacb45SAlex Williamson mtty_disable_intx(mdev_state);
1017*94eacb45SAlex Williamson break;
1018*94eacb45SAlex Williamson }
1019*94eacb45SAlex Williamson
1020*94eacb45SAlex Williamson if (!(is_intx(mdev_state) || is_noirq(mdev_state)) ||
1021*94eacb45SAlex Williamson start != 0 || count != 1) {
1022*94eacb45SAlex Williamson ret = -EINVAL;
10239d1a546cSKirti Wankhede break;
10249d1a546cSKirti Wankhede }
10259d1a546cSKirti Wankhede
10269d1a546cSKirti Wankhede if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
10279d1a546cSKirti Wankhede int fd = *(int *)data;
10289d1a546cSKirti Wankhede struct eventfd_ctx *evt;
10299d1a546cSKirti Wankhede
1030*94eacb45SAlex Williamson mtty_disable_intx(mdev_state);
1031*94eacb45SAlex Williamson
1032*94eacb45SAlex Williamson if (fd < 0)
1033*94eacb45SAlex Williamson break;
1034*94eacb45SAlex Williamson
10359d1a546cSKirti Wankhede evt = eventfd_ctx_fdget(fd);
10369d1a546cSKirti Wankhede if (IS_ERR(evt)) {
10379d1a546cSKirti Wankhede ret = PTR_ERR(evt);
10389d1a546cSKirti Wankhede break;
10399d1a546cSKirti Wankhede }
10409d1a546cSKirti Wankhede mdev_state->intx_evtfd = evt;
10419d1a546cSKirti Wankhede mdev_state->irq_index = index;
10429d1a546cSKirti Wankhede break;
10439d1a546cSKirti Wankhede }
1044*94eacb45SAlex Williamson
1045*94eacb45SAlex Williamson if (!is_intx(mdev_state)) {
1046*94eacb45SAlex Williamson ret = -EINVAL;
10479d1a546cSKirti Wankhede break;
10489d1a546cSKirti Wankhede }
1049*94eacb45SAlex Williamson
1050*94eacb45SAlex Williamson if (flags & VFIO_IRQ_SET_DATA_NONE) {
1051*94eacb45SAlex Williamson mtty_trigger_interrupt(mdev_state);
1052*94eacb45SAlex Williamson } else if (flags & VFIO_IRQ_SET_DATA_BOOL) {
1053*94eacb45SAlex Williamson uint8_t trigger = *(uint8_t *)data;
1054*94eacb45SAlex Williamson
1055*94eacb45SAlex Williamson if (trigger)
1056*94eacb45SAlex Williamson mtty_trigger_interrupt(mdev_state);
1057*94eacb45SAlex Williamson }
1058*94eacb45SAlex Williamson break;
10599d1a546cSKirti Wankhede }
10609d1a546cSKirti Wankhede break;
10619d1a546cSKirti Wankhede case VFIO_PCI_MSI_IRQ_INDEX:
10629d1a546cSKirti Wankhede switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) {
10639d1a546cSKirti Wankhede case VFIO_IRQ_SET_ACTION_MASK:
10649d1a546cSKirti Wankhede case VFIO_IRQ_SET_ACTION_UNMASK:
1065*94eacb45SAlex Williamson ret = -ENOTTY;
10669d1a546cSKirti Wankhede break;
10679d1a546cSKirti Wankhede case VFIO_IRQ_SET_ACTION_TRIGGER:
1068*94eacb45SAlex Williamson if (is_msi(mdev_state) && !count &&
1069*94eacb45SAlex Williamson (flags & VFIO_IRQ_SET_DATA_NONE)) {
1070*94eacb45SAlex Williamson mtty_disable_msi(mdev_state);
10719d1a546cSKirti Wankhede break;
10729d1a546cSKirti Wankhede }
1073*94eacb45SAlex Williamson
1074*94eacb45SAlex Williamson if (!(is_msi(mdev_state) || is_noirq(mdev_state)) ||
1075*94eacb45SAlex Williamson start != 0 || count != 1) {
1076*94eacb45SAlex Williamson ret = -EINVAL;
1077*94eacb45SAlex Williamson break;
1078*94eacb45SAlex Williamson }
1079*94eacb45SAlex Williamson
10809d1a546cSKirti Wankhede if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
10819d1a546cSKirti Wankhede int fd = *(int *)data;
10829d1a546cSKirti Wankhede struct eventfd_ctx *evt;
10839d1a546cSKirti Wankhede
1084*94eacb45SAlex Williamson mtty_disable_msi(mdev_state);
10859d1a546cSKirti Wankhede
1086*94eacb45SAlex Williamson if (fd < 0)
10879d1a546cSKirti Wankhede break;
10889d1a546cSKirti Wankhede
10899d1a546cSKirti Wankhede evt = eventfd_ctx_fdget(fd);
10909d1a546cSKirti Wankhede if (IS_ERR(evt)) {
10919d1a546cSKirti Wankhede ret = PTR_ERR(evt);
10929d1a546cSKirti Wankhede break;
10939d1a546cSKirti Wankhede }
10949d1a546cSKirti Wankhede mdev_state->msi_evtfd = evt;
10959d1a546cSKirti Wankhede mdev_state->irq_index = index;
1096*94eacb45SAlex Williamson break;
1097*94eacb45SAlex Williamson }
1098*94eacb45SAlex Williamson
1099*94eacb45SAlex Williamson if (!is_msi(mdev_state)) {
1100*94eacb45SAlex Williamson ret = -EINVAL;
1101*94eacb45SAlex Williamson break;
1102*94eacb45SAlex Williamson }
1103*94eacb45SAlex Williamson
1104*94eacb45SAlex Williamson if (flags & VFIO_IRQ_SET_DATA_NONE) {
1105*94eacb45SAlex Williamson mtty_trigger_interrupt(mdev_state);
1106*94eacb45SAlex Williamson } else if (flags & VFIO_IRQ_SET_DATA_BOOL) {
1107*94eacb45SAlex Williamson uint8_t trigger = *(uint8_t *)data;
1108*94eacb45SAlex Williamson
1109*94eacb45SAlex Williamson if (trigger)
1110*94eacb45SAlex Williamson mtty_trigger_interrupt(mdev_state);
11119d1a546cSKirti Wankhede }
11129d1a546cSKirti Wankhede break;
11139d1a546cSKirti Wankhede }
11149d1a546cSKirti Wankhede break;
11159d1a546cSKirti Wankhede case VFIO_PCI_MSIX_IRQ_INDEX:
1116*94eacb45SAlex Williamson dev_dbg(mdev_state->vdev.dev, "%s: MSIX_IRQ\n", __func__);
1117*94eacb45SAlex Williamson ret = -ENOTTY;
11189d1a546cSKirti Wankhede break;
11199d1a546cSKirti Wankhede case VFIO_PCI_ERR_IRQ_INDEX:
1120*94eacb45SAlex Williamson dev_dbg(mdev_state->vdev.dev, "%s: ERR_IRQ\n", __func__);
1121*94eacb45SAlex Williamson ret = -ENOTTY;
11229d1a546cSKirti Wankhede break;
11239d1a546cSKirti Wankhede case VFIO_PCI_REQ_IRQ_INDEX:
1124*94eacb45SAlex Williamson dev_dbg(mdev_state->vdev.dev, "%s: REQ_IRQ\n", __func__);
1125*94eacb45SAlex Williamson ret = -ENOTTY;
11269d1a546cSKirti Wankhede break;
11279d1a546cSKirti Wankhede }
11289d1a546cSKirti Wankhede
11299d1a546cSKirti Wankhede mutex_unlock(&mdev_state->ops_lock);
11309d1a546cSKirti Wankhede return ret;
11319d1a546cSKirti Wankhede }
11329d1a546cSKirti Wankhede
mtty_get_region_info(struct mdev_state * mdev_state,struct vfio_region_info * region_info,u16 * cap_type_id,void ** cap_type)113309177ac9SJason Gunthorpe static int mtty_get_region_info(struct mdev_state *mdev_state,
11349d1a546cSKirti Wankhede struct vfio_region_info *region_info,
11359d1a546cSKirti Wankhede u16 *cap_type_id, void **cap_type)
11369d1a546cSKirti Wankhede {
11379d1a546cSKirti Wankhede unsigned int size = 0;
11385c677869SDan Carpenter u32 bar_index;
11399d1a546cSKirti Wankhede
11409d1a546cSKirti Wankhede bar_index = region_info->index;
11415c677869SDan Carpenter if (bar_index >= VFIO_PCI_NUM_REGIONS)
11425c677869SDan Carpenter return -EINVAL;
11435c677869SDan Carpenter
11445c677869SDan Carpenter mutex_lock(&mdev_state->ops_lock);
11459d1a546cSKirti Wankhede
11469d1a546cSKirti Wankhede switch (bar_index) {
11479d1a546cSKirti Wankhede case VFIO_PCI_CONFIG_REGION_INDEX:
11489d1a546cSKirti Wankhede size = MTTY_CONFIG_SPACE_SIZE;
11499d1a546cSKirti Wankhede break;
11509d1a546cSKirti Wankhede case VFIO_PCI_BAR0_REGION_INDEX:
11519d1a546cSKirti Wankhede size = MTTY_IO_BAR_SIZE;
11529d1a546cSKirti Wankhede break;
11539d1a546cSKirti Wankhede case VFIO_PCI_BAR1_REGION_INDEX:
11549d1a546cSKirti Wankhede if (mdev_state->nr_ports == 2)
11559d1a546cSKirti Wankhede size = MTTY_IO_BAR_SIZE;
11569d1a546cSKirti Wankhede break;
11579d1a546cSKirti Wankhede default:
11589d1a546cSKirti Wankhede size = 0;
11599d1a546cSKirti Wankhede break;
11609d1a546cSKirti Wankhede }
11619d1a546cSKirti Wankhede
11629d1a546cSKirti Wankhede mdev_state->region_info[bar_index].size = size;
11639d1a546cSKirti Wankhede mdev_state->region_info[bar_index].vfio_offset =
11649d1a546cSKirti Wankhede MTTY_VFIO_PCI_INDEX_TO_OFFSET(bar_index);
11659d1a546cSKirti Wankhede
11669d1a546cSKirti Wankhede region_info->size = size;
11679d1a546cSKirti Wankhede region_info->offset = MTTY_VFIO_PCI_INDEX_TO_OFFSET(bar_index);
11689d1a546cSKirti Wankhede region_info->flags = VFIO_REGION_INFO_FLAG_READ |
11699d1a546cSKirti Wankhede VFIO_REGION_INFO_FLAG_WRITE;
11709d1a546cSKirti Wankhede mutex_unlock(&mdev_state->ops_lock);
11719d1a546cSKirti Wankhede return 0;
11729d1a546cSKirti Wankhede }
11739d1a546cSKirti Wankhede
mtty_get_irq_info(struct vfio_irq_info * irq_info)117409177ac9SJason Gunthorpe static int mtty_get_irq_info(struct vfio_irq_info *irq_info)
11759d1a546cSKirti Wankhede {
1176*94eacb45SAlex Williamson if (irq_info->index != VFIO_PCI_INTX_IRQ_INDEX &&
1177*94eacb45SAlex Williamson irq_info->index != VFIO_PCI_MSI_IRQ_INDEX)
11789d1a546cSKirti Wankhede return -EINVAL;
11799d1a546cSKirti Wankhede
11809d1a546cSKirti Wankhede irq_info->flags = VFIO_IRQ_INFO_EVENTFD;
11819d1a546cSKirti Wankhede irq_info->count = 1;
11829d1a546cSKirti Wankhede
11839d1a546cSKirti Wankhede if (irq_info->index == VFIO_PCI_INTX_IRQ_INDEX)
1184*94eacb45SAlex Williamson irq_info->flags |= VFIO_IRQ_INFO_MASKABLE |
1185*94eacb45SAlex Williamson VFIO_IRQ_INFO_AUTOMASKED;
11869d1a546cSKirti Wankhede else
11879d1a546cSKirti Wankhede irq_info->flags |= VFIO_IRQ_INFO_NORESIZE;
11889d1a546cSKirti Wankhede
11899d1a546cSKirti Wankhede return 0;
11909d1a546cSKirti Wankhede }
11919d1a546cSKirti Wankhede
mtty_get_device_info(struct vfio_device_info * dev_info)119209177ac9SJason Gunthorpe static int mtty_get_device_info(struct vfio_device_info *dev_info)
11939d1a546cSKirti Wankhede {
11949d1a546cSKirti Wankhede dev_info->flags = VFIO_DEVICE_FLAGS_PCI;
11959d1a546cSKirti Wankhede dev_info->num_regions = VFIO_PCI_NUM_REGIONS;
11969d1a546cSKirti Wankhede dev_info->num_irqs = VFIO_PCI_NUM_IRQS;
11979d1a546cSKirti Wankhede
11989d1a546cSKirti Wankhede return 0;
11999d1a546cSKirti Wankhede }
12009d1a546cSKirti Wankhede
mtty_ioctl(struct vfio_device * vdev,unsigned int cmd,unsigned long arg)120109177ac9SJason Gunthorpe static long mtty_ioctl(struct vfio_device *vdev, unsigned int cmd,
12029d1a546cSKirti Wankhede unsigned long arg)
12039d1a546cSKirti Wankhede {
120409177ac9SJason Gunthorpe struct mdev_state *mdev_state =
120509177ac9SJason Gunthorpe container_of(vdev, struct mdev_state, vdev);
12069d1a546cSKirti Wankhede int ret = 0;
12079d1a546cSKirti Wankhede unsigned long minsz;
12089d1a546cSKirti Wankhede
12099d1a546cSKirti Wankhede switch (cmd) {
12109d1a546cSKirti Wankhede case VFIO_DEVICE_GET_INFO:
12119d1a546cSKirti Wankhede {
12129d1a546cSKirti Wankhede struct vfio_device_info info;
12139d1a546cSKirti Wankhede
12149d1a546cSKirti Wankhede minsz = offsetofend(struct vfio_device_info, num_irqs);
12159d1a546cSKirti Wankhede
12169d1a546cSKirti Wankhede if (copy_from_user(&info, (void __user *)arg, minsz))
12179d1a546cSKirti Wankhede return -EFAULT;
12189d1a546cSKirti Wankhede
12199d1a546cSKirti Wankhede if (info.argsz < minsz)
12209d1a546cSKirti Wankhede return -EINVAL;
12219d1a546cSKirti Wankhede
122209177ac9SJason Gunthorpe ret = mtty_get_device_info(&info);
12239d1a546cSKirti Wankhede if (ret)
12249d1a546cSKirti Wankhede return ret;
12259d1a546cSKirti Wankhede
12269d1a546cSKirti Wankhede memcpy(&mdev_state->dev_info, &info, sizeof(info));
12279d1a546cSKirti Wankhede
12286ed0993aSDan Carpenter if (copy_to_user((void __user *)arg, &info, minsz))
12296ed0993aSDan Carpenter return -EFAULT;
12306ed0993aSDan Carpenter
12316ed0993aSDan Carpenter return 0;
12329d1a546cSKirti Wankhede }
12339d1a546cSKirti Wankhede case VFIO_DEVICE_GET_REGION_INFO:
12349d1a546cSKirti Wankhede {
12359d1a546cSKirti Wankhede struct vfio_region_info info;
12369d1a546cSKirti Wankhede u16 cap_type_id = 0;
12379d1a546cSKirti Wankhede void *cap_type = NULL;
12389d1a546cSKirti Wankhede
12399d1a546cSKirti Wankhede minsz = offsetofend(struct vfio_region_info, offset);
12409d1a546cSKirti Wankhede
12419d1a546cSKirti Wankhede if (copy_from_user(&info, (void __user *)arg, minsz))
12429d1a546cSKirti Wankhede return -EFAULT;
12439d1a546cSKirti Wankhede
12449d1a546cSKirti Wankhede if (info.argsz < minsz)
12459d1a546cSKirti Wankhede return -EINVAL;
12469d1a546cSKirti Wankhede
124709177ac9SJason Gunthorpe ret = mtty_get_region_info(mdev_state, &info, &cap_type_id,
12489d1a546cSKirti Wankhede &cap_type);
12499d1a546cSKirti Wankhede if (ret)
12509d1a546cSKirti Wankhede return ret;
12519d1a546cSKirti Wankhede
12526ed0993aSDan Carpenter if (copy_to_user((void __user *)arg, &info, minsz))
12536ed0993aSDan Carpenter return -EFAULT;
12546ed0993aSDan Carpenter
12556ed0993aSDan Carpenter return 0;
12569d1a546cSKirti Wankhede }
12579d1a546cSKirti Wankhede
12589d1a546cSKirti Wankhede case VFIO_DEVICE_GET_IRQ_INFO:
12599d1a546cSKirti Wankhede {
12609d1a546cSKirti Wankhede struct vfio_irq_info info;
12619d1a546cSKirti Wankhede
12629d1a546cSKirti Wankhede minsz = offsetofend(struct vfio_irq_info, count);
12639d1a546cSKirti Wankhede
12649d1a546cSKirti Wankhede if (copy_from_user(&info, (void __user *)arg, minsz))
12659d1a546cSKirti Wankhede return -EFAULT;
12669d1a546cSKirti Wankhede
12679d1a546cSKirti Wankhede if ((info.argsz < minsz) ||
12689d1a546cSKirti Wankhede (info.index >= mdev_state->dev_info.num_irqs))
12699d1a546cSKirti Wankhede return -EINVAL;
12709d1a546cSKirti Wankhede
127109177ac9SJason Gunthorpe ret = mtty_get_irq_info(&info);
12729d1a546cSKirti Wankhede if (ret)
12739d1a546cSKirti Wankhede return ret;
12749d1a546cSKirti Wankhede
12756ed0993aSDan Carpenter if (copy_to_user((void __user *)arg, &info, minsz))
12766ed0993aSDan Carpenter return -EFAULT;
12776ed0993aSDan Carpenter
12786ed0993aSDan Carpenter return 0;
12799d1a546cSKirti Wankhede }
12809d1a546cSKirti Wankhede case VFIO_DEVICE_SET_IRQS:
12819d1a546cSKirti Wankhede {
12829d1a546cSKirti Wankhede struct vfio_irq_set hdr;
12839d1a546cSKirti Wankhede u8 *data = NULL, *ptr = NULL;
12849d1a546cSKirti Wankhede size_t data_size = 0;
12859d1a546cSKirti Wankhede
12869d1a546cSKirti Wankhede minsz = offsetofend(struct vfio_irq_set, count);
12879d1a546cSKirti Wankhede
12889d1a546cSKirti Wankhede if (copy_from_user(&hdr, (void __user *)arg, minsz))
12899d1a546cSKirti Wankhede return -EFAULT;
12909d1a546cSKirti Wankhede
12919d1a546cSKirti Wankhede ret = vfio_set_irqs_validate_and_prepare(&hdr,
12929d1a546cSKirti Wankhede mdev_state->dev_info.num_irqs,
12939d1a546cSKirti Wankhede VFIO_PCI_NUM_IRQS,
12949d1a546cSKirti Wankhede &data_size);
12959d1a546cSKirti Wankhede if (ret)
12969d1a546cSKirti Wankhede return ret;
12979d1a546cSKirti Wankhede
12989d1a546cSKirti Wankhede if (data_size) {
12999d1a546cSKirti Wankhede ptr = data = memdup_user((void __user *)(arg + minsz),
13009d1a546cSKirti Wankhede data_size);
13019d1a546cSKirti Wankhede if (IS_ERR(data))
13029d1a546cSKirti Wankhede return PTR_ERR(data);
13039d1a546cSKirti Wankhede }
13049d1a546cSKirti Wankhede
130509177ac9SJason Gunthorpe ret = mtty_set_irqs(mdev_state, hdr.flags, hdr.index, hdr.start,
13069d1a546cSKirti Wankhede hdr.count, data);
13079d1a546cSKirti Wankhede
13089d1a546cSKirti Wankhede kfree(ptr);
13099d1a546cSKirti Wankhede return ret;
13109d1a546cSKirti Wankhede }
13119d1a546cSKirti Wankhede case VFIO_DEVICE_RESET:
131209177ac9SJason Gunthorpe return mtty_reset(mdev_state);
13139d1a546cSKirti Wankhede }
13149d1a546cSKirti Wankhede return -ENOTTY;
13159d1a546cSKirti Wankhede }
13169d1a546cSKirti Wankhede
13179d1a546cSKirti Wankhede static ssize_t
sample_mdev_dev_show(struct device * dev,struct device_attribute * attr,char * buf)13189d1a546cSKirti Wankhede sample_mdev_dev_show(struct device *dev, struct device_attribute *attr,
13199d1a546cSKirti Wankhede char *buf)
13209d1a546cSKirti Wankhede {
132199e3123eSAlex Williamson return sprintf(buf, "This is MDEV %s\n", dev_name(dev));
13229d1a546cSKirti Wankhede }
13239d1a546cSKirti Wankhede
13249d1a546cSKirti Wankhede static DEVICE_ATTR_RO(sample_mdev_dev);
13259d1a546cSKirti Wankhede
13269d1a546cSKirti Wankhede static struct attribute *mdev_dev_attrs[] = {
13279d1a546cSKirti Wankhede &dev_attr_sample_mdev_dev.attr,
13289d1a546cSKirti Wankhede NULL,
13299d1a546cSKirti Wankhede };
13309d1a546cSKirti Wankhede
13319d1a546cSKirti Wankhede static const struct attribute_group mdev_dev_group = {
13329d1a546cSKirti Wankhede .name = "vendor",
13339d1a546cSKirti Wankhede .attrs = mdev_dev_attrs,
13349d1a546cSKirti Wankhede };
13359d1a546cSKirti Wankhede
13364b2dbd56SKefeng Wang static const struct attribute_group *mdev_dev_groups[] = {
13379d1a546cSKirti Wankhede &mdev_dev_group,
13389d1a546cSKirti Wankhede NULL,
13399d1a546cSKirti Wankhede };
13409d1a546cSKirti Wankhede
mtty_get_available(struct mdev_type * mtype)1341f2fbc72eSChristoph Hellwig static unsigned int mtty_get_available(struct mdev_type *mtype)
13429d1a546cSKirti Wankhede {
1343da44c340SChristoph Hellwig struct mtty_type *type = container_of(mtype, struct mtty_type, type);
13449d1a546cSKirti Wankhede
1345f2fbc72eSChristoph Hellwig return atomic_read(&mdev_avail_ports) / type->nr_ports;
13469d1a546cSKirti Wankhede }
13479d1a546cSKirti Wankhede
mtty_close(struct vfio_device * vdev)1348*94eacb45SAlex Williamson static void mtty_close(struct vfio_device *vdev)
1349*94eacb45SAlex Williamson {
1350*94eacb45SAlex Williamson struct mdev_state *mdev_state =
1351*94eacb45SAlex Williamson container_of(vdev, struct mdev_state, vdev);
1352*94eacb45SAlex Williamson
1353*94eacb45SAlex Williamson mtty_disable_intx(mdev_state);
1354*94eacb45SAlex Williamson mtty_disable_msi(mdev_state);
1355*94eacb45SAlex Williamson }
1356*94eacb45SAlex Williamson
135709177ac9SJason Gunthorpe static const struct vfio_device_ops mtty_dev_ops = {
135809177ac9SJason Gunthorpe .name = "vfio-mtty",
135967c5a181SYi Liu .init = mtty_init_dev,
136067c5a181SYi Liu .release = mtty_release_dev,
13619d1a546cSKirti Wankhede .read = mtty_read,
13629d1a546cSKirti Wankhede .write = mtty_write,
13639d1a546cSKirti Wankhede .ioctl = mtty_ioctl,
13640a782d15SYi Liu .bind_iommufd = vfio_iommufd_emulated_bind,
13650a782d15SYi Liu .unbind_iommufd = vfio_iommufd_emulated_unbind,
13660a782d15SYi Liu .attach_ioas = vfio_iommufd_emulated_attach_ioas,
13678cfa7186SYi Liu .detach_ioas = vfio_iommufd_emulated_detach_ioas,
1368*94eacb45SAlex Williamson .close_device = mtty_close,
13699d1a546cSKirti Wankhede };
13709d1a546cSKirti Wankhede
137109177ac9SJason Gunthorpe static struct mdev_driver mtty_driver = {
1372290aac5dSJason Gunthorpe .device_api = VFIO_DEVICE_API_PCI_STRING,
137309177ac9SJason Gunthorpe .driver = {
137409177ac9SJason Gunthorpe .name = "mtty",
137509177ac9SJason Gunthorpe .owner = THIS_MODULE,
137609177ac9SJason Gunthorpe .mod_name = KBUILD_MODNAME,
137709177ac9SJason Gunthorpe .dev_groups = mdev_dev_groups,
137809177ac9SJason Gunthorpe },
137909177ac9SJason Gunthorpe .probe = mtty_probe,
138009177ac9SJason Gunthorpe .remove = mtty_remove,
1381f2fbc72eSChristoph Hellwig .get_available = mtty_get_available,
138209177ac9SJason Gunthorpe };
138309177ac9SJason Gunthorpe
mtty_device_release(struct device * dev)13849d1a546cSKirti Wankhede static void mtty_device_release(struct device *dev)
13859d1a546cSKirti Wankhede {
13869d1a546cSKirti Wankhede dev_dbg(dev, "mtty: released\n");
13879d1a546cSKirti Wankhede }
13889d1a546cSKirti Wankhede
mtty_dev_init(void)13899d1a546cSKirti Wankhede static int __init mtty_dev_init(void)
13909d1a546cSKirti Wankhede {
13919d1a546cSKirti Wankhede int ret = 0;
13929d1a546cSKirti Wankhede
13939d1a546cSKirti Wankhede pr_info("mtty_dev: %s\n", __func__);
13949d1a546cSKirti Wankhede
13959d1a546cSKirti Wankhede memset(&mtty_dev, 0, sizeof(mtty_dev));
13969d1a546cSKirti Wankhede
13979d1a546cSKirti Wankhede idr_init(&mtty_dev.vd_idr);
13989d1a546cSKirti Wankhede
13993e4835f7SChengguang Xu ret = alloc_chrdev_region(&mtty_dev.vd_devt, 0, MINORMASK + 1,
14003e4835f7SChengguang Xu MTTY_NAME);
14019d1a546cSKirti Wankhede
14029d1a546cSKirti Wankhede if (ret < 0) {
14039d1a546cSKirti Wankhede pr_err("Error: failed to register mtty_dev, err:%d\n", ret);
14049d1a546cSKirti Wankhede return ret;
14059d1a546cSKirti Wankhede }
14069d1a546cSKirti Wankhede
14079d1a546cSKirti Wankhede cdev_init(&mtty_dev.vd_cdev, &vd_fops);
14083e4835f7SChengguang Xu cdev_add(&mtty_dev.vd_cdev, mtty_dev.vd_devt, MINORMASK + 1);
14099d1a546cSKirti Wankhede
14109d1a546cSKirti Wankhede pr_info("major_number:%d\n", MAJOR(mtty_dev.vd_devt));
14119d1a546cSKirti Wankhede
141209177ac9SJason Gunthorpe ret = mdev_register_driver(&mtty_driver);
141309177ac9SJason Gunthorpe if (ret)
141409177ac9SJason Gunthorpe goto err_cdev;
141509177ac9SJason Gunthorpe
14161aaba11dSGreg Kroah-Hartman mtty_dev.vd_class = class_create(MTTY_CLASS_NAME);
14179d1a546cSKirti Wankhede
14189d1a546cSKirti Wankhede if (IS_ERR(mtty_dev.vd_class)) {
14199d1a546cSKirti Wankhede pr_err("Error: failed to register mtty_dev class\n");
1420d293dbaaSDan Carpenter ret = PTR_ERR(mtty_dev.vd_class);
142109177ac9SJason Gunthorpe goto err_driver;
14229d1a546cSKirti Wankhede }
14239d1a546cSKirti Wankhede
14249d1a546cSKirti Wankhede mtty_dev.dev.class = mtty_dev.vd_class;
14259d1a546cSKirti Wankhede mtty_dev.dev.release = mtty_device_release;
14269d1a546cSKirti Wankhede dev_set_name(&mtty_dev.dev, "%s", MTTY_NAME);
14279d1a546cSKirti Wankhede
14289d1a546cSKirti Wankhede ret = device_register(&mtty_dev.dev);
14299d1a546cSKirti Wankhede if (ret)
1430ce389573SAlex Williamson goto err_put;
14319d1a546cSKirti Wankhede
143289345d51SChristoph Hellwig ret = mdev_register_parent(&mtty_dev.parent, &mtty_dev.dev,
1433da44c340SChristoph Hellwig &mtty_driver, mtty_mdev_types,
1434da44c340SChristoph Hellwig ARRAY_SIZE(mtty_mdev_types));
1435d293dbaaSDan Carpenter if (ret)
143609177ac9SJason Gunthorpe goto err_device;
143709177ac9SJason Gunthorpe return 0;
14389d1a546cSKirti Wankhede
143909177ac9SJason Gunthorpe err_device:
1440ce389573SAlex Williamson device_del(&mtty_dev.dev);
1441ce389573SAlex Williamson err_put:
1442ce389573SAlex Williamson put_device(&mtty_dev.dev);
14439d1a546cSKirti Wankhede class_destroy(mtty_dev.vd_class);
144409177ac9SJason Gunthorpe err_driver:
144509177ac9SJason Gunthorpe mdev_unregister_driver(&mtty_driver);
144609177ac9SJason Gunthorpe err_cdev:
14479d1a546cSKirti Wankhede cdev_del(&mtty_dev.vd_cdev);
14483e4835f7SChengguang Xu unregister_chrdev_region(mtty_dev.vd_devt, MINORMASK + 1);
14499d1a546cSKirti Wankhede return ret;
14509d1a546cSKirti Wankhede }
14519d1a546cSKirti Wankhede
mtty_dev_exit(void)14529d1a546cSKirti Wankhede static void __exit mtty_dev_exit(void)
14539d1a546cSKirti Wankhede {
14549d1a546cSKirti Wankhede mtty_dev.dev.bus = NULL;
145589345d51SChristoph Hellwig mdev_unregister_parent(&mtty_dev.parent);
14569d1a546cSKirti Wankhede
14579d1a546cSKirti Wankhede device_unregister(&mtty_dev.dev);
14589d1a546cSKirti Wankhede idr_destroy(&mtty_dev.vd_idr);
145909177ac9SJason Gunthorpe mdev_unregister_driver(&mtty_driver);
14609d1a546cSKirti Wankhede cdev_del(&mtty_dev.vd_cdev);
14613e4835f7SChengguang Xu unregister_chrdev_region(mtty_dev.vd_devt, MINORMASK + 1);
14629d1a546cSKirti Wankhede class_destroy(mtty_dev.vd_class);
14639d1a546cSKirti Wankhede mtty_dev.vd_class = NULL;
14649d1a546cSKirti Wankhede pr_info("mtty_dev: Unloaded!\n");
14659d1a546cSKirti Wankhede }
14669d1a546cSKirti Wankhede
14679d1a546cSKirti Wankhede module_init(mtty_dev_init)
14689d1a546cSKirti Wankhede module_exit(mtty_dev_exit)
14699d1a546cSKirti Wankhede
14709d1a546cSKirti Wankhede MODULE_LICENSE("GPL v2");
14719d1a546cSKirti Wankhede MODULE_INFO(supported, "Test driver that simulate serial port over PCI");
14729d1a546cSKirti Wankhede MODULE_VERSION(VERSION_STRING);
14739d1a546cSKirti Wankhede MODULE_AUTHOR(DRIVER_AUTHOR);
1474