1f3cf8bb0SJiang Liu /* 2f3cf8bb0SJiang Liu * linux/kernel/irq/msi.c 3f3cf8bb0SJiang Liu * 4f3cf8bb0SJiang Liu * Copyright (C) 2014 Intel Corp. 5f3cf8bb0SJiang Liu * Author: Jiang Liu <jiang.liu@linux.intel.com> 6f3cf8bb0SJiang Liu * 7f3cf8bb0SJiang Liu * This file is licensed under GPLv2. 8f3cf8bb0SJiang Liu * 9f3cf8bb0SJiang Liu * This file contains common code to support Message Signalled Interrupt for 10f3cf8bb0SJiang Liu * PCI compatible and non PCI compatible devices. 11f3cf8bb0SJiang Liu */ 12aeeb5965SJiang Liu #include <linux/types.h> 13aeeb5965SJiang Liu #include <linux/device.h> 14f3cf8bb0SJiang Liu #include <linux/irq.h> 15f3cf8bb0SJiang Liu #include <linux/irqdomain.h> 16f3cf8bb0SJiang Liu #include <linux/msi.h> 17f3cf8bb0SJiang Liu 18d9109698SJiang Liu /* Temparory solution for building, will be removed later */ 19d9109698SJiang Liu #include <linux/pci.h> 20d9109698SJiang Liu 21aa48b6f7SJiang Liu struct msi_desc *alloc_msi_entry(struct device *dev) 22aa48b6f7SJiang Liu { 23aa48b6f7SJiang Liu struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); 24aa48b6f7SJiang Liu if (!desc) 25aa48b6f7SJiang Liu return NULL; 26aa48b6f7SJiang Liu 27aa48b6f7SJiang Liu INIT_LIST_HEAD(&desc->list); 28aa48b6f7SJiang Liu desc->dev = dev; 29aa48b6f7SJiang Liu 30aa48b6f7SJiang Liu return desc; 31aa48b6f7SJiang Liu } 32aa48b6f7SJiang Liu 33aa48b6f7SJiang Liu void free_msi_entry(struct msi_desc *entry) 34aa48b6f7SJiang Liu { 35aa48b6f7SJiang Liu kfree(entry); 36aa48b6f7SJiang Liu } 37aa48b6f7SJiang Liu 3838b6a1cfSJiang Liu void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) 3938b6a1cfSJiang Liu { 4038b6a1cfSJiang Liu *msg = entry->msg; 4138b6a1cfSJiang Liu } 4238b6a1cfSJiang Liu 4338b6a1cfSJiang Liu void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) 4438b6a1cfSJiang Liu { 4538b6a1cfSJiang Liu struct msi_desc *entry = irq_get_msi_desc(irq); 4638b6a1cfSJiang Liu 4738b6a1cfSJiang Liu __get_cached_msi_msg(entry, msg); 4838b6a1cfSJiang Liu } 4938b6a1cfSJiang Liu EXPORT_SYMBOL_GPL(get_cached_msi_msg); 5038b6a1cfSJiang Liu 51f3cf8bb0SJiang Liu #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN 5274faaf7aSThomas Gleixner static inline void irq_chip_write_msi_msg(struct irq_data *data, 5374faaf7aSThomas Gleixner struct msi_msg *msg) 5474faaf7aSThomas Gleixner { 5574faaf7aSThomas Gleixner data->chip->irq_write_msi_msg(data, msg); 5674faaf7aSThomas Gleixner } 5774faaf7aSThomas Gleixner 58f3cf8bb0SJiang Liu /** 59f3cf8bb0SJiang Liu * msi_domain_set_affinity - Generic affinity setter function for MSI domains 60f3cf8bb0SJiang Liu * @irq_data: The irq data associated to the interrupt 61f3cf8bb0SJiang Liu * @mask: The affinity mask to set 62f3cf8bb0SJiang Liu * @force: Flag to enforce setting (disable online checks) 63f3cf8bb0SJiang Liu * 64f3cf8bb0SJiang Liu * Intended to be used by MSI interrupt controllers which are 65f3cf8bb0SJiang Liu * implemented with hierarchical domains. 66f3cf8bb0SJiang Liu */ 67f3cf8bb0SJiang Liu int msi_domain_set_affinity(struct irq_data *irq_data, 68f3cf8bb0SJiang Liu const struct cpumask *mask, bool force) 69f3cf8bb0SJiang Liu { 70f3cf8bb0SJiang Liu struct irq_data *parent = irq_data->parent_data; 71f3cf8bb0SJiang Liu struct msi_msg msg; 72f3cf8bb0SJiang Liu int ret; 73f3cf8bb0SJiang Liu 74f3cf8bb0SJiang Liu ret = parent->chip->irq_set_affinity(parent, mask, force); 75f3cf8bb0SJiang Liu if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) { 76f3cf8bb0SJiang Liu BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg)); 77f3cf8bb0SJiang Liu irq_chip_write_msi_msg(irq_data, &msg); 78f3cf8bb0SJiang Liu } 79f3cf8bb0SJiang Liu 80f3cf8bb0SJiang Liu return ret; 81f3cf8bb0SJiang Liu } 82f3cf8bb0SJiang Liu 83f3cf8bb0SJiang Liu static void msi_domain_activate(struct irq_domain *domain, 84f3cf8bb0SJiang Liu struct irq_data *irq_data) 85f3cf8bb0SJiang Liu { 86f3cf8bb0SJiang Liu struct msi_msg msg; 87f3cf8bb0SJiang Liu 88f3cf8bb0SJiang Liu BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg)); 89f3cf8bb0SJiang Liu irq_chip_write_msi_msg(irq_data, &msg); 90f3cf8bb0SJiang Liu } 91f3cf8bb0SJiang Liu 92f3cf8bb0SJiang Liu static void msi_domain_deactivate(struct irq_domain *domain, 93f3cf8bb0SJiang Liu struct irq_data *irq_data) 94f3cf8bb0SJiang Liu { 95f3cf8bb0SJiang Liu struct msi_msg msg; 96f3cf8bb0SJiang Liu 97f3cf8bb0SJiang Liu memset(&msg, 0, sizeof(msg)); 98f3cf8bb0SJiang Liu irq_chip_write_msi_msg(irq_data, &msg); 99f3cf8bb0SJiang Liu } 100f3cf8bb0SJiang Liu 101f3cf8bb0SJiang Liu static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 102f3cf8bb0SJiang Liu unsigned int nr_irqs, void *arg) 103f3cf8bb0SJiang Liu { 104f3cf8bb0SJiang Liu struct msi_domain_info *info = domain->host_data; 105f3cf8bb0SJiang Liu struct msi_domain_ops *ops = info->ops; 106f3cf8bb0SJiang Liu irq_hw_number_t hwirq = ops->get_hwirq(info, arg); 107f3cf8bb0SJiang Liu int i, ret; 108f3cf8bb0SJiang Liu 109f3cf8bb0SJiang Liu if (irq_find_mapping(domain, hwirq) > 0) 110f3cf8bb0SJiang Liu return -EEXIST; 111f3cf8bb0SJiang Liu 112f3cf8bb0SJiang Liu ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); 113f3cf8bb0SJiang Liu if (ret < 0) 114f3cf8bb0SJiang Liu return ret; 115f3cf8bb0SJiang Liu 116f3cf8bb0SJiang Liu for (i = 0; i < nr_irqs; i++) { 117f3cf8bb0SJiang Liu ret = ops->msi_init(domain, info, virq + i, hwirq + i, arg); 118f3cf8bb0SJiang Liu if (ret < 0) { 119f3cf8bb0SJiang Liu if (ops->msi_free) { 120f3cf8bb0SJiang Liu for (i--; i > 0; i--) 121f3cf8bb0SJiang Liu ops->msi_free(domain, info, virq + i); 122f3cf8bb0SJiang Liu } 123f3cf8bb0SJiang Liu irq_domain_free_irqs_top(domain, virq, nr_irqs); 124f3cf8bb0SJiang Liu return ret; 125f3cf8bb0SJiang Liu } 126f3cf8bb0SJiang Liu } 127f3cf8bb0SJiang Liu 128f3cf8bb0SJiang Liu return 0; 129f3cf8bb0SJiang Liu } 130f3cf8bb0SJiang Liu 131f3cf8bb0SJiang Liu static void msi_domain_free(struct irq_domain *domain, unsigned int virq, 132f3cf8bb0SJiang Liu unsigned int nr_irqs) 133f3cf8bb0SJiang Liu { 134f3cf8bb0SJiang Liu struct msi_domain_info *info = domain->host_data; 135f3cf8bb0SJiang Liu int i; 136f3cf8bb0SJiang Liu 137f3cf8bb0SJiang Liu if (info->ops->msi_free) { 138f3cf8bb0SJiang Liu for (i = 0; i < nr_irqs; i++) 139f3cf8bb0SJiang Liu info->ops->msi_free(domain, info, virq + i); 140f3cf8bb0SJiang Liu } 141f3cf8bb0SJiang Liu irq_domain_free_irqs_top(domain, virq, nr_irqs); 142f3cf8bb0SJiang Liu } 143f3cf8bb0SJiang Liu 14401364028SKrzysztof Kozlowski static const struct irq_domain_ops msi_domain_ops = { 145f3cf8bb0SJiang Liu .alloc = msi_domain_alloc, 146f3cf8bb0SJiang Liu .free = msi_domain_free, 147f3cf8bb0SJiang Liu .activate = msi_domain_activate, 148f3cf8bb0SJiang Liu .deactivate = msi_domain_deactivate, 149f3cf8bb0SJiang Liu }; 150f3cf8bb0SJiang Liu 151aeeb5965SJiang Liu #ifdef GENERIC_MSI_DOMAIN_OPS 152aeeb5965SJiang Liu static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info, 153aeeb5965SJiang Liu msi_alloc_info_t *arg) 154aeeb5965SJiang Liu { 155aeeb5965SJiang Liu return arg->hwirq; 156aeeb5965SJiang Liu } 157aeeb5965SJiang Liu 158aeeb5965SJiang Liu static int msi_domain_ops_prepare(struct irq_domain *domain, struct device *dev, 159aeeb5965SJiang Liu int nvec, msi_alloc_info_t *arg) 160aeeb5965SJiang Liu { 161aeeb5965SJiang Liu memset(arg, 0, sizeof(*arg)); 162aeeb5965SJiang Liu return 0; 163aeeb5965SJiang Liu } 164aeeb5965SJiang Liu 165aeeb5965SJiang Liu static void msi_domain_ops_set_desc(msi_alloc_info_t *arg, 166aeeb5965SJiang Liu struct msi_desc *desc) 167aeeb5965SJiang Liu { 168aeeb5965SJiang Liu arg->desc = desc; 169aeeb5965SJiang Liu } 170aeeb5965SJiang Liu #else 171aeeb5965SJiang Liu #define msi_domain_ops_get_hwirq NULL 172aeeb5965SJiang Liu #define msi_domain_ops_prepare NULL 173aeeb5965SJiang Liu #define msi_domain_ops_set_desc NULL 174aeeb5965SJiang Liu #endif /* !GENERIC_MSI_DOMAIN_OPS */ 175aeeb5965SJiang Liu 176aeeb5965SJiang Liu static int msi_domain_ops_init(struct irq_domain *domain, 177aeeb5965SJiang Liu struct msi_domain_info *info, 178aeeb5965SJiang Liu unsigned int virq, irq_hw_number_t hwirq, 179aeeb5965SJiang Liu msi_alloc_info_t *arg) 180aeeb5965SJiang Liu { 181aeeb5965SJiang Liu irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip, 182aeeb5965SJiang Liu info->chip_data); 183aeeb5965SJiang Liu if (info->handler && info->handler_name) { 184aeeb5965SJiang Liu __irq_set_handler(virq, info->handler, 0, info->handler_name); 185aeeb5965SJiang Liu if (info->handler_data) 186aeeb5965SJiang Liu irq_set_handler_data(virq, info->handler_data); 187aeeb5965SJiang Liu } 188aeeb5965SJiang Liu return 0; 189aeeb5965SJiang Liu } 190aeeb5965SJiang Liu 191aeeb5965SJiang Liu static int msi_domain_ops_check(struct irq_domain *domain, 192aeeb5965SJiang Liu struct msi_domain_info *info, 193aeeb5965SJiang Liu struct device *dev) 194aeeb5965SJiang Liu { 195aeeb5965SJiang Liu return 0; 196aeeb5965SJiang Liu } 197aeeb5965SJiang Liu 198aeeb5965SJiang Liu static struct msi_domain_ops msi_domain_ops_default = { 199aeeb5965SJiang Liu .get_hwirq = msi_domain_ops_get_hwirq, 200aeeb5965SJiang Liu .msi_init = msi_domain_ops_init, 201aeeb5965SJiang Liu .msi_check = msi_domain_ops_check, 202aeeb5965SJiang Liu .msi_prepare = msi_domain_ops_prepare, 203aeeb5965SJiang Liu .set_desc = msi_domain_ops_set_desc, 204aeeb5965SJiang Liu }; 205aeeb5965SJiang Liu 206aeeb5965SJiang Liu static void msi_domain_update_dom_ops(struct msi_domain_info *info) 207aeeb5965SJiang Liu { 208aeeb5965SJiang Liu struct msi_domain_ops *ops = info->ops; 209aeeb5965SJiang Liu 210aeeb5965SJiang Liu if (ops == NULL) { 211aeeb5965SJiang Liu info->ops = &msi_domain_ops_default; 212aeeb5965SJiang Liu return; 213aeeb5965SJiang Liu } 214aeeb5965SJiang Liu 215aeeb5965SJiang Liu if (ops->get_hwirq == NULL) 216aeeb5965SJiang Liu ops->get_hwirq = msi_domain_ops_default.get_hwirq; 217aeeb5965SJiang Liu if (ops->msi_init == NULL) 218aeeb5965SJiang Liu ops->msi_init = msi_domain_ops_default.msi_init; 219aeeb5965SJiang Liu if (ops->msi_check == NULL) 220aeeb5965SJiang Liu ops->msi_check = msi_domain_ops_default.msi_check; 221aeeb5965SJiang Liu if (ops->msi_prepare == NULL) 222aeeb5965SJiang Liu ops->msi_prepare = msi_domain_ops_default.msi_prepare; 223aeeb5965SJiang Liu if (ops->set_desc == NULL) 224aeeb5965SJiang Liu ops->set_desc = msi_domain_ops_default.set_desc; 225aeeb5965SJiang Liu } 226aeeb5965SJiang Liu 227aeeb5965SJiang Liu static void msi_domain_update_chip_ops(struct msi_domain_info *info) 228aeeb5965SJiang Liu { 229aeeb5965SJiang Liu struct irq_chip *chip = info->chip; 230aeeb5965SJiang Liu 2310701c53eSMarc Zyngier BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask); 232aeeb5965SJiang Liu if (!chip->irq_set_affinity) 233aeeb5965SJiang Liu chip->irq_set_affinity = msi_domain_set_affinity; 234aeeb5965SJiang Liu } 235aeeb5965SJiang Liu 236f3cf8bb0SJiang Liu /** 237f3cf8bb0SJiang Liu * msi_create_irq_domain - Create a MSI interrupt domain 238f3cf8bb0SJiang Liu * @of_node: Optional device-tree node of the interrupt controller 239f3cf8bb0SJiang Liu * @info: MSI domain info 240f3cf8bb0SJiang Liu * @parent: Parent irq domain 241f3cf8bb0SJiang Liu */ 242aeeb5965SJiang Liu struct irq_domain *msi_create_irq_domain(struct device_node *node, 243f3cf8bb0SJiang Liu struct msi_domain_info *info, 244f3cf8bb0SJiang Liu struct irq_domain *parent) 245f3cf8bb0SJiang Liu { 246aeeb5965SJiang Liu if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) 247aeeb5965SJiang Liu msi_domain_update_dom_ops(info); 248aeeb5965SJiang Liu if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) 249aeeb5965SJiang Liu msi_domain_update_chip_ops(info); 250f3cf8bb0SJiang Liu 251aeeb5965SJiang Liu return irq_domain_add_hierarchy(parent, 0, 0, node, &msi_domain_ops, 252aeeb5965SJiang Liu info); 253f3cf8bb0SJiang Liu } 254f3cf8bb0SJiang Liu 255f3cf8bb0SJiang Liu /** 256d9109698SJiang Liu * msi_domain_alloc_irqs - Allocate interrupts from a MSI interrupt domain 257d9109698SJiang Liu * @domain: The domain to allocate from 258d9109698SJiang Liu * @dev: Pointer to device struct of the device for which the interrupts 259d9109698SJiang Liu * are allocated 260d9109698SJiang Liu * @nvec: The number of interrupts to allocate 261d9109698SJiang Liu * 262d9109698SJiang Liu * Returns 0 on success or an error code. 263d9109698SJiang Liu */ 264d9109698SJiang Liu int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, 265d9109698SJiang Liu int nvec) 266d9109698SJiang Liu { 267d9109698SJiang Liu struct msi_domain_info *info = domain->host_data; 268d9109698SJiang Liu struct msi_domain_ops *ops = info->ops; 269d9109698SJiang Liu msi_alloc_info_t arg; 270d9109698SJiang Liu struct msi_desc *desc; 271d9109698SJiang Liu int i, ret, virq = -1; 272d9109698SJiang Liu 273d9109698SJiang Liu ret = ops->msi_check(domain, info, dev); 274d9109698SJiang Liu if (ret == 0) 275d9109698SJiang Liu ret = ops->msi_prepare(domain, dev, nvec, &arg); 276d9109698SJiang Liu if (ret) 277d9109698SJiang Liu return ret; 278d9109698SJiang Liu 279d9109698SJiang Liu for_each_msi_entry(desc, dev) { 280d9109698SJiang Liu ops->set_desc(&arg, desc); 281aeeb5965SJiang Liu if (info->flags & MSI_FLAG_IDENTITY_MAP) 282aeeb5965SJiang Liu virq = (int)ops->get_hwirq(info, &arg); 283aeeb5965SJiang Liu else 284aeeb5965SJiang Liu virq = -1; 285d9109698SJiang Liu 286aeeb5965SJiang Liu virq = __irq_domain_alloc_irqs(domain, virq, desc->nvec_used, 287d9109698SJiang Liu dev_to_node(dev), &arg, false); 288d9109698SJiang Liu if (virq < 0) { 289d9109698SJiang Liu ret = -ENOSPC; 290d9109698SJiang Liu if (ops->handle_error) 291d9109698SJiang Liu ret = ops->handle_error(domain, desc, ret); 292d9109698SJiang Liu if (ops->msi_finish) 293d9109698SJiang Liu ops->msi_finish(&arg, ret); 294d9109698SJiang Liu return ret; 295d9109698SJiang Liu } 296d9109698SJiang Liu 297d9109698SJiang Liu for (i = 0; i < desc->nvec_used; i++) 298d9109698SJiang Liu irq_set_msi_desc_off(virq, i, desc); 299d9109698SJiang Liu } 300d9109698SJiang Liu 301d9109698SJiang Liu if (ops->msi_finish) 302d9109698SJiang Liu ops->msi_finish(&arg, 0); 303d9109698SJiang Liu 304d9109698SJiang Liu for_each_msi_entry(desc, dev) { 305d9109698SJiang Liu if (desc->nvec_used == 1) 306d9109698SJiang Liu dev_dbg(dev, "irq %d for MSI\n", virq); 307d9109698SJiang Liu else 308d9109698SJiang Liu dev_dbg(dev, "irq [%d-%d] for MSI\n", 309d9109698SJiang Liu virq, virq + desc->nvec_used - 1); 310d9109698SJiang Liu } 311d9109698SJiang Liu 312d9109698SJiang Liu return 0; 313d9109698SJiang Liu } 314d9109698SJiang Liu 315d9109698SJiang Liu /** 316d9109698SJiang Liu * msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain associated tp @dev 317d9109698SJiang Liu * @domain: The domain to managing the interrupts 318d9109698SJiang Liu * @dev: Pointer to device struct of the device for which the interrupts 319d9109698SJiang Liu * are free 320d9109698SJiang Liu */ 321d9109698SJiang Liu void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev) 322d9109698SJiang Liu { 323d9109698SJiang Liu struct msi_desc *desc; 324d9109698SJiang Liu 325d9109698SJiang Liu for_each_msi_entry(desc, dev) { 326fe0c52fcSMarc Zyngier /* 327fe0c52fcSMarc Zyngier * We might have failed to allocate an MSI early 328fe0c52fcSMarc Zyngier * enough that there is no IRQ associated to this 329fe0c52fcSMarc Zyngier * entry. If that's the case, don't do anything. 330fe0c52fcSMarc Zyngier */ 331fe0c52fcSMarc Zyngier if (desc->irq) { 332d9109698SJiang Liu irq_domain_free_irqs(desc->irq, desc->nvec_used); 333d9109698SJiang Liu desc->irq = 0; 334d9109698SJiang Liu } 335d9109698SJiang Liu } 336fe0c52fcSMarc Zyngier } 337d9109698SJiang Liu 338d9109698SJiang Liu /** 339f3cf8bb0SJiang Liu * msi_get_domain_info - Get the MSI interrupt domain info for @domain 340f3cf8bb0SJiang Liu * @domain: The interrupt domain to retrieve data from 341f3cf8bb0SJiang Liu * 342f3cf8bb0SJiang Liu * Returns the pointer to the msi_domain_info stored in 343f3cf8bb0SJiang Liu * @domain->host_data. 344f3cf8bb0SJiang Liu */ 345f3cf8bb0SJiang Liu struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain) 346f3cf8bb0SJiang Liu { 347f3cf8bb0SJiang Liu return (struct msi_domain_info *)domain->host_data; 348f3cf8bb0SJiang Liu } 349f3cf8bb0SJiang Liu 350f3cf8bb0SJiang Liu #endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */ 351