xref: /openbmc/linux/kernel/irq/generic-chip.c (revision 68198dca)
1 /*
2  * Library implementing the most common irq chip callback functions
3  *
4  * Copyright (C) 2011, Thomas Gleixner
5  */
6 #include <linux/io.h>
7 #include <linux/irq.h>
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/irqdomain.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/syscore_ops.h>
14 
15 #include "internals.h"
16 
17 static LIST_HEAD(gc_list);
18 static DEFINE_RAW_SPINLOCK(gc_lock);
19 
20 /**
21  * irq_gc_noop - NOOP function
22  * @d: irq_data
23  */
24 void irq_gc_noop(struct irq_data *d)
25 {
26 }
27 
28 /**
29  * irq_gc_mask_disable_reg - Mask chip via disable register
30  * @d: irq_data
31  *
32  * Chip has separate enable/disable registers instead of a single mask
33  * register.
34  */
35 void irq_gc_mask_disable_reg(struct irq_data *d)
36 {
37 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
38 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
39 	u32 mask = d->mask;
40 
41 	irq_gc_lock(gc);
42 	irq_reg_writel(gc, mask, ct->regs.disable);
43 	*ct->mask_cache &= ~mask;
44 	irq_gc_unlock(gc);
45 }
46 
47 /**
48  * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
49  * @d: irq_data
50  *
51  * Chip has a single mask register. Values of this register are cached
52  * and protected by gc->lock
53  */
54 void irq_gc_mask_set_bit(struct irq_data *d)
55 {
56 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
57 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
58 	u32 mask = d->mask;
59 
60 	irq_gc_lock(gc);
61 	*ct->mask_cache |= mask;
62 	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
63 	irq_gc_unlock(gc);
64 }
65 EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
66 
67 /**
68  * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
69  * @d: irq_data
70  *
71  * Chip has a single mask register. Values of this register are cached
72  * and protected by gc->lock
73  */
74 void irq_gc_mask_clr_bit(struct irq_data *d)
75 {
76 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
77 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
78 	u32 mask = d->mask;
79 
80 	irq_gc_lock(gc);
81 	*ct->mask_cache &= ~mask;
82 	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
83 	irq_gc_unlock(gc);
84 }
85 EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
86 
87 /**
88  * irq_gc_unmask_enable_reg - Unmask chip via enable register
89  * @d: irq_data
90  *
91  * Chip has separate enable/disable registers instead of a single mask
92  * register.
93  */
94 void irq_gc_unmask_enable_reg(struct irq_data *d)
95 {
96 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
97 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
98 	u32 mask = d->mask;
99 
100 	irq_gc_lock(gc);
101 	irq_reg_writel(gc, mask, ct->regs.enable);
102 	*ct->mask_cache |= mask;
103 	irq_gc_unlock(gc);
104 }
105 
106 /**
107  * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
108  * @d: irq_data
109  */
110 void irq_gc_ack_set_bit(struct irq_data *d)
111 {
112 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
113 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
114 	u32 mask = d->mask;
115 
116 	irq_gc_lock(gc);
117 	irq_reg_writel(gc, mask, ct->regs.ack);
118 	irq_gc_unlock(gc);
119 }
120 EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
121 
122 /**
123  * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
124  * @d: irq_data
125  */
126 void irq_gc_ack_clr_bit(struct irq_data *d)
127 {
128 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
129 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
130 	u32 mask = ~d->mask;
131 
132 	irq_gc_lock(gc);
133 	irq_reg_writel(gc, mask, ct->regs.ack);
134 	irq_gc_unlock(gc);
135 }
136 
137 /**
138  * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
139  * @d: irq_data
140  *
141  * This generic implementation of the irq_mask_ack method is for chips
142  * with separate enable/disable registers instead of a single mask
143  * register and where a pending interrupt is acknowledged by setting a
144  * bit.
145  *
146  * Note: This is the only permutation currently used.  Similar generic
147  * functions should be added here if other permutations are required.
148  */
149 void irq_gc_mask_disable_and_ack_set(struct irq_data *d)
150 {
151 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
152 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
153 	u32 mask = d->mask;
154 
155 	irq_gc_lock(gc);
156 	irq_reg_writel(gc, mask, ct->regs.disable);
157 	*ct->mask_cache &= ~mask;
158 	irq_reg_writel(gc, mask, ct->regs.ack);
159 	irq_gc_unlock(gc);
160 }
161 
162 /**
163  * irq_gc_eoi - EOI interrupt
164  * @d: irq_data
165  */
166 void irq_gc_eoi(struct irq_data *d)
167 {
168 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
169 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
170 	u32 mask = d->mask;
171 
172 	irq_gc_lock(gc);
173 	irq_reg_writel(gc, mask, ct->regs.eoi);
174 	irq_gc_unlock(gc);
175 }
176 
177 /**
178  * irq_gc_set_wake - Set/clr wake bit for an interrupt
179  * @d:  irq_data
180  * @on: Indicates whether the wake bit should be set or cleared
181  *
182  * For chips where the wake from suspend functionality is not
183  * configured in a separate register and the wakeup active state is
184  * just stored in a bitmask.
185  */
186 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
187 {
188 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
189 	u32 mask = d->mask;
190 
191 	if (!(mask & gc->wake_enabled))
192 		return -EINVAL;
193 
194 	irq_gc_lock(gc);
195 	if (on)
196 		gc->wake_active |= mask;
197 	else
198 		gc->wake_active &= ~mask;
199 	irq_gc_unlock(gc);
200 	return 0;
201 }
202 
203 static u32 irq_readl_be(void __iomem *addr)
204 {
205 	return ioread32be(addr);
206 }
207 
208 static void irq_writel_be(u32 val, void __iomem *addr)
209 {
210 	iowrite32be(val, addr);
211 }
212 
213 void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
214 			   int num_ct, unsigned int irq_base,
215 			   void __iomem *reg_base, irq_flow_handler_t handler)
216 {
217 	raw_spin_lock_init(&gc->lock);
218 	gc->num_ct = num_ct;
219 	gc->irq_base = irq_base;
220 	gc->reg_base = reg_base;
221 	gc->chip_types->chip.name = name;
222 	gc->chip_types->handler = handler;
223 }
224 
225 /**
226  * irq_alloc_generic_chip - Allocate a generic chip and initialize it
227  * @name:	Name of the irq chip
228  * @num_ct:	Number of irq_chip_type instances associated with this
229  * @irq_base:	Interrupt base nr for this chip
230  * @reg_base:	Register base address (virtual)
231  * @handler:	Default flow handler associated with this chip
232  *
233  * Returns an initialized irq_chip_generic structure. The chip defaults
234  * to the primary (index 0) irq_chip_type and @handler
235  */
236 struct irq_chip_generic *
237 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
238 		       void __iomem *reg_base, irq_flow_handler_t handler)
239 {
240 	struct irq_chip_generic *gc;
241 	unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
242 
243 	gc = kzalloc(sz, GFP_KERNEL);
244 	if (gc) {
245 		irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
246 				      handler);
247 	}
248 	return gc;
249 }
250 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
251 
252 static void
253 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
254 {
255 	struct irq_chip_type *ct = gc->chip_types;
256 	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
257 	int i;
258 
259 	for (i = 0; i < gc->num_ct; i++) {
260 		if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
261 			mskptr = &ct[i].mask_cache_priv;
262 			mskreg = ct[i].regs.mask;
263 		}
264 		ct[i].mask_cache = mskptr;
265 		if (flags & IRQ_GC_INIT_MASK_CACHE)
266 			*mskptr = irq_reg_readl(gc, mskreg);
267 	}
268 }
269 
270 /**
271  * __irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
272  * @d:			irq domain for which to allocate chips
273  * @irqs_per_chip:	Number of interrupts each chip handles (max 32)
274  * @num_ct:		Number of irq_chip_type instances associated with this
275  * @name:		Name of the irq chip
276  * @handler:		Default flow handler associated with these chips
277  * @clr:		IRQ_* bits to clear in the mapping function
278  * @set:		IRQ_* bits to set in the mapping function
279  * @gcflags:		Generic chip specific setup flags
280  */
281 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
282 				     int num_ct, const char *name,
283 				     irq_flow_handler_t handler,
284 				     unsigned int clr, unsigned int set,
285 				     enum irq_gc_flags gcflags)
286 {
287 	struct irq_domain_chip_generic *dgc;
288 	struct irq_chip_generic *gc;
289 	int numchips, sz, i;
290 	unsigned long flags;
291 	void *tmp;
292 
293 	if (d->gc)
294 		return -EBUSY;
295 
296 	numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
297 	if (!numchips)
298 		return -EINVAL;
299 
300 	/* Allocate a pointer, generic chip and chiptypes for each chip */
301 	sz = sizeof(*dgc) + numchips * sizeof(gc);
302 	sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));
303 
304 	tmp = dgc = kzalloc(sz, GFP_KERNEL);
305 	if (!dgc)
306 		return -ENOMEM;
307 	dgc->irqs_per_chip = irqs_per_chip;
308 	dgc->num_chips = numchips;
309 	dgc->irq_flags_to_set = set;
310 	dgc->irq_flags_to_clear = clr;
311 	dgc->gc_flags = gcflags;
312 	d->gc = dgc;
313 
314 	/* Calc pointer to the first generic chip */
315 	tmp += sizeof(*dgc) + numchips * sizeof(gc);
316 	for (i = 0; i < numchips; i++) {
317 		/* Store the pointer to the generic chip */
318 		dgc->gc[i] = gc = tmp;
319 		irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
320 				      NULL, handler);
321 
322 		gc->domain = d;
323 		if (gcflags & IRQ_GC_BE_IO) {
324 			gc->reg_readl = &irq_readl_be;
325 			gc->reg_writel = &irq_writel_be;
326 		}
327 
328 		raw_spin_lock_irqsave(&gc_lock, flags);
329 		list_add_tail(&gc->list, &gc_list);
330 		raw_spin_unlock_irqrestore(&gc_lock, flags);
331 		/* Calc pointer to the next generic chip */
332 		tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
333 	}
334 	return 0;
335 }
336 EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
337 
338 static struct irq_chip_generic *
339 __irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
340 {
341 	struct irq_domain_chip_generic *dgc = d->gc;
342 	int idx;
343 
344 	if (!dgc)
345 		return ERR_PTR(-ENODEV);
346 	idx = hw_irq / dgc->irqs_per_chip;
347 	if (idx >= dgc->num_chips)
348 		return ERR_PTR(-EINVAL);
349 	return dgc->gc[idx];
350 }
351 
352 /**
353  * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
354  * @d:			irq domain pointer
355  * @hw_irq:		Hardware interrupt number
356  */
357 struct irq_chip_generic *
358 irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
359 {
360 	struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
361 
362 	return !IS_ERR(gc) ? gc : NULL;
363 }
364 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
365 
366 /*
367  * Separate lockdep class for interrupt chip which can nest irq_desc
368  * lock.
369  */
370 static struct lock_class_key irq_nested_lock_class;
371 
372 /*
373  * irq_map_generic_chip - Map a generic chip for an irq domain
374  */
375 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
376 			 irq_hw_number_t hw_irq)
377 {
378 	struct irq_data *data = irq_domain_get_irq_data(d, virq);
379 	struct irq_domain_chip_generic *dgc = d->gc;
380 	struct irq_chip_generic *gc;
381 	struct irq_chip_type *ct;
382 	struct irq_chip *chip;
383 	unsigned long flags;
384 	int idx;
385 
386 	gc = __irq_get_domain_generic_chip(d, hw_irq);
387 	if (IS_ERR(gc))
388 		return PTR_ERR(gc);
389 
390 	idx = hw_irq % dgc->irqs_per_chip;
391 
392 	if (test_bit(idx, &gc->unused))
393 		return -ENOTSUPP;
394 
395 	if (test_bit(idx, &gc->installed))
396 		return -EBUSY;
397 
398 	ct = gc->chip_types;
399 	chip = &ct->chip;
400 
401 	/* We only init the cache for the first mapping of a generic chip */
402 	if (!gc->installed) {
403 		raw_spin_lock_irqsave(&gc->lock, flags);
404 		irq_gc_init_mask_cache(gc, dgc->gc_flags);
405 		raw_spin_unlock_irqrestore(&gc->lock, flags);
406 	}
407 
408 	/* Mark the interrupt as installed */
409 	set_bit(idx, &gc->installed);
410 
411 	if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
412 		irq_set_lockdep_class(virq, &irq_nested_lock_class);
413 
414 	if (chip->irq_calc_mask)
415 		chip->irq_calc_mask(data);
416 	else
417 		data->mask = 1 << idx;
418 
419 	irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
420 	irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
421 	return 0;
422 }
423 
424 static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
425 {
426 	struct irq_data *data = irq_domain_get_irq_data(d, virq);
427 	struct irq_domain_chip_generic *dgc = d->gc;
428 	unsigned int hw_irq = data->hwirq;
429 	struct irq_chip_generic *gc;
430 	int irq_idx;
431 
432 	gc = irq_get_domain_generic_chip(d, hw_irq);
433 	if (!gc)
434 		return;
435 
436 	irq_idx = hw_irq % dgc->irqs_per_chip;
437 
438 	clear_bit(irq_idx, &gc->installed);
439 	irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
440 			    NULL);
441 
442 }
443 
444 struct irq_domain_ops irq_generic_chip_ops = {
445 	.map	= irq_map_generic_chip,
446 	.unmap  = irq_unmap_generic_chip,
447 	.xlate	= irq_domain_xlate_onetwocell,
448 };
449 EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
450 
451 /**
452  * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
453  * @gc:		Generic irq chip holding all data
454  * @msk:	Bitmask holding the irqs to initialize relative to gc->irq_base
455  * @flags:	Flags for initialization
456  * @clr:	IRQ_* bits to clear
457  * @set:	IRQ_* bits to set
458  *
459  * Set up max. 32 interrupts starting from gc->irq_base. Note, this
460  * initializes all interrupts to the primary irq_chip_type and its
461  * associated handler.
462  */
463 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
464 			    enum irq_gc_flags flags, unsigned int clr,
465 			    unsigned int set)
466 {
467 	struct irq_chip_type *ct = gc->chip_types;
468 	struct irq_chip *chip = &ct->chip;
469 	unsigned int i;
470 
471 	raw_spin_lock(&gc_lock);
472 	list_add_tail(&gc->list, &gc_list);
473 	raw_spin_unlock(&gc_lock);
474 
475 	irq_gc_init_mask_cache(gc, flags);
476 
477 	for (i = gc->irq_base; msk; msk >>= 1, i++) {
478 		if (!(msk & 0x01))
479 			continue;
480 
481 		if (flags & IRQ_GC_INIT_NESTED_LOCK)
482 			irq_set_lockdep_class(i, &irq_nested_lock_class);
483 
484 		if (!(flags & IRQ_GC_NO_MASK)) {
485 			struct irq_data *d = irq_get_irq_data(i);
486 
487 			if (chip->irq_calc_mask)
488 				chip->irq_calc_mask(d);
489 			else
490 				d->mask = 1 << (i - gc->irq_base);
491 		}
492 		irq_set_chip_and_handler(i, chip, ct->handler);
493 		irq_set_chip_data(i, gc);
494 		irq_modify_status(i, clr, set);
495 	}
496 	gc->irq_cnt = i - gc->irq_base;
497 }
498 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
499 
500 /**
501  * irq_setup_alt_chip - Switch to alternative chip
502  * @d:		irq_data for this interrupt
503  * @type:	Flow type to be initialized
504  *
505  * Only to be called from chip->irq_set_type() callbacks.
506  */
507 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
508 {
509 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
510 	struct irq_chip_type *ct = gc->chip_types;
511 	unsigned int i;
512 
513 	for (i = 0; i < gc->num_ct; i++, ct++) {
514 		if (ct->type & type) {
515 			d->chip = &ct->chip;
516 			irq_data_to_desc(d)->handle_irq = ct->handler;
517 			return 0;
518 		}
519 	}
520 	return -EINVAL;
521 }
522 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
523 
524 /**
525  * irq_remove_generic_chip - Remove a chip
526  * @gc:		Generic irq chip holding all data
527  * @msk:	Bitmask holding the irqs to initialize relative to gc->irq_base
528  * @clr:	IRQ_* bits to clear
529  * @set:	IRQ_* bits to set
530  *
531  * Remove up to 32 interrupts starting from gc->irq_base.
532  */
533 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
534 			     unsigned int clr, unsigned int set)
535 {
536 	unsigned int i = gc->irq_base;
537 
538 	raw_spin_lock(&gc_lock);
539 	list_del(&gc->list);
540 	raw_spin_unlock(&gc_lock);
541 
542 	for (; msk; msk >>= 1, i++) {
543 		if (!(msk & 0x01))
544 			continue;
545 
546 		/* Remove handler first. That will mask the irq line */
547 		irq_set_handler(i, NULL);
548 		irq_set_chip(i, &no_irq_chip);
549 		irq_set_chip_data(i, NULL);
550 		irq_modify_status(i, clr, set);
551 	}
552 }
553 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
554 
555 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
556 {
557 	unsigned int virq;
558 
559 	if (!gc->domain)
560 		return irq_get_irq_data(gc->irq_base);
561 
562 	/*
563 	 * We don't know which of the irqs has been actually
564 	 * installed. Use the first one.
565 	 */
566 	if (!gc->installed)
567 		return NULL;
568 
569 	virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
570 	return virq ? irq_get_irq_data(virq) : NULL;
571 }
572 
573 #ifdef CONFIG_PM
574 static int irq_gc_suspend(void)
575 {
576 	struct irq_chip_generic *gc;
577 
578 	list_for_each_entry(gc, &gc_list, list) {
579 		struct irq_chip_type *ct = gc->chip_types;
580 
581 		if (ct->chip.irq_suspend) {
582 			struct irq_data *data = irq_gc_get_irq_data(gc);
583 
584 			if (data)
585 				ct->chip.irq_suspend(data);
586 		}
587 
588 		if (gc->suspend)
589 			gc->suspend(gc);
590 	}
591 	return 0;
592 }
593 
594 static void irq_gc_resume(void)
595 {
596 	struct irq_chip_generic *gc;
597 
598 	list_for_each_entry(gc, &gc_list, list) {
599 		struct irq_chip_type *ct = gc->chip_types;
600 
601 		if (gc->resume)
602 			gc->resume(gc);
603 
604 		if (ct->chip.irq_resume) {
605 			struct irq_data *data = irq_gc_get_irq_data(gc);
606 
607 			if (data)
608 				ct->chip.irq_resume(data);
609 		}
610 	}
611 }
612 #else
613 #define irq_gc_suspend NULL
614 #define irq_gc_resume NULL
615 #endif
616 
617 static void irq_gc_shutdown(void)
618 {
619 	struct irq_chip_generic *gc;
620 
621 	list_for_each_entry(gc, &gc_list, list) {
622 		struct irq_chip_type *ct = gc->chip_types;
623 
624 		if (ct->chip.irq_pm_shutdown) {
625 			struct irq_data *data = irq_gc_get_irq_data(gc);
626 
627 			if (data)
628 				ct->chip.irq_pm_shutdown(data);
629 		}
630 	}
631 }
632 
633 static struct syscore_ops irq_gc_syscore_ops = {
634 	.suspend = irq_gc_suspend,
635 	.resume = irq_gc_resume,
636 	.shutdown = irq_gc_shutdown,
637 };
638 
639 static int __init irq_gc_init_ops(void)
640 {
641 	register_syscore_ops(&irq_gc_syscore_ops);
642 	return 0;
643 }
644 device_initcall(irq_gc_init_ops);
645