1 /* 2 * Library implementing the most common irq chip callback functions 3 * 4 * Copyright (C) 2011, Thomas Gleixner 5 */ 6 #include <linux/io.h> 7 #include <linux/irq.h> 8 #include <linux/slab.h> 9 #include <linux/export.h> 10 #include <linux/irqdomain.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel_stat.h> 13 #include <linux/syscore_ops.h> 14 15 #include "internals.h" 16 17 static LIST_HEAD(gc_list); 18 static DEFINE_RAW_SPINLOCK(gc_lock); 19 20 /** 21 * irq_gc_noop - NOOP function 22 * @d: irq_data 23 */ 24 void irq_gc_noop(struct irq_data *d) 25 { 26 } 27 28 /** 29 * irq_gc_mask_disable_reg - Mask chip via disable register 30 * @d: irq_data 31 * 32 * Chip has separate enable/disable registers instead of a single mask 33 * register. 34 */ 35 void irq_gc_mask_disable_reg(struct irq_data *d) 36 { 37 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 38 struct irq_chip_type *ct = irq_data_get_chip_type(d); 39 u32 mask = d->mask; 40 41 irq_gc_lock(gc); 42 irq_reg_writel(mask, gc->reg_base + ct->regs.disable); 43 *ct->mask_cache &= ~mask; 44 irq_gc_unlock(gc); 45 } 46 47 /** 48 * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register 49 * @d: irq_data 50 * 51 * Chip has a single mask register. Values of this register are cached 52 * and protected by gc->lock 53 */ 54 void irq_gc_mask_set_bit(struct irq_data *d) 55 { 56 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 57 struct irq_chip_type *ct = irq_data_get_chip_type(d); 58 u32 mask = d->mask; 59 60 irq_gc_lock(gc); 61 *ct->mask_cache |= mask; 62 irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask); 63 irq_gc_unlock(gc); 64 } 65 66 /** 67 * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register 68 * @d: irq_data 69 * 70 * Chip has a single mask register. Values of this register are cached 71 * and protected by gc->lock 72 */ 73 void irq_gc_mask_clr_bit(struct irq_data *d) 74 { 75 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 76 struct irq_chip_type *ct = irq_data_get_chip_type(d); 77 u32 mask = d->mask; 78 79 irq_gc_lock(gc); 80 *ct->mask_cache &= ~mask; 81 irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask); 82 irq_gc_unlock(gc); 83 } 84 85 /** 86 * irq_gc_unmask_enable_reg - Unmask chip via enable register 87 * @d: irq_data 88 * 89 * Chip has separate enable/disable registers instead of a single mask 90 * register. 91 */ 92 void irq_gc_unmask_enable_reg(struct irq_data *d) 93 { 94 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 95 struct irq_chip_type *ct = irq_data_get_chip_type(d); 96 u32 mask = d->mask; 97 98 irq_gc_lock(gc); 99 irq_reg_writel(mask, gc->reg_base + ct->regs.enable); 100 *ct->mask_cache |= mask; 101 irq_gc_unlock(gc); 102 } 103 104 /** 105 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit 106 * @d: irq_data 107 */ 108 void irq_gc_ack_set_bit(struct irq_data *d) 109 { 110 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 111 struct irq_chip_type *ct = irq_data_get_chip_type(d); 112 u32 mask = d->mask; 113 114 irq_gc_lock(gc); 115 irq_reg_writel(mask, gc->reg_base + ct->regs.ack); 116 irq_gc_unlock(gc); 117 } 118 119 /** 120 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit 121 * @d: irq_data 122 */ 123 void irq_gc_ack_clr_bit(struct irq_data *d) 124 { 125 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 126 struct irq_chip_type *ct = irq_data_get_chip_type(d); 127 u32 mask = ~d->mask; 128 129 irq_gc_lock(gc); 130 irq_reg_writel(mask, gc->reg_base + ct->regs.ack); 131 irq_gc_unlock(gc); 132 } 133 134 /** 135 * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt 136 * @d: irq_data 137 */ 138 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d) 139 { 140 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 141 struct irq_chip_type *ct = irq_data_get_chip_type(d); 142 u32 mask = d->mask; 143 144 irq_gc_lock(gc); 145 irq_reg_writel(mask, gc->reg_base + ct->regs.mask); 146 irq_reg_writel(mask, gc->reg_base + ct->regs.ack); 147 irq_gc_unlock(gc); 148 } 149 150 /** 151 * irq_gc_eoi - EOI interrupt 152 * @d: irq_data 153 */ 154 void irq_gc_eoi(struct irq_data *d) 155 { 156 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 157 struct irq_chip_type *ct = irq_data_get_chip_type(d); 158 u32 mask = d->mask; 159 160 irq_gc_lock(gc); 161 irq_reg_writel(mask, gc->reg_base + ct->regs.eoi); 162 irq_gc_unlock(gc); 163 } 164 165 /** 166 * irq_gc_set_wake - Set/clr wake bit for an interrupt 167 * @d: irq_data 168 * 169 * For chips where the wake from suspend functionality is not 170 * configured in a separate register and the wakeup active state is 171 * just stored in a bitmask. 172 */ 173 int irq_gc_set_wake(struct irq_data *d, unsigned int on) 174 { 175 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 176 u32 mask = d->mask; 177 178 if (!(mask & gc->wake_enabled)) 179 return -EINVAL; 180 181 irq_gc_lock(gc); 182 if (on) 183 gc->wake_active |= mask; 184 else 185 gc->wake_active &= ~mask; 186 irq_gc_unlock(gc); 187 return 0; 188 } 189 190 static void 191 irq_init_generic_chip(struct irq_chip_generic *gc, const char *name, 192 int num_ct, unsigned int irq_base, 193 void __iomem *reg_base, irq_flow_handler_t handler) 194 { 195 raw_spin_lock_init(&gc->lock); 196 gc->num_ct = num_ct; 197 gc->irq_base = irq_base; 198 gc->reg_base = reg_base; 199 gc->chip_types->chip.name = name; 200 gc->chip_types->handler = handler; 201 } 202 203 /** 204 * irq_alloc_generic_chip - Allocate a generic chip and initialize it 205 * @name: Name of the irq chip 206 * @num_ct: Number of irq_chip_type instances associated with this 207 * @irq_base: Interrupt base nr for this chip 208 * @reg_base: Register base address (virtual) 209 * @handler: Default flow handler associated with this chip 210 * 211 * Returns an initialized irq_chip_generic structure. The chip defaults 212 * to the primary (index 0) irq_chip_type and @handler 213 */ 214 struct irq_chip_generic * 215 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base, 216 void __iomem *reg_base, irq_flow_handler_t handler) 217 { 218 struct irq_chip_generic *gc; 219 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type); 220 221 gc = kzalloc(sz, GFP_KERNEL); 222 if (gc) { 223 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base, 224 handler); 225 } 226 return gc; 227 } 228 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip); 229 230 static void 231 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags) 232 { 233 struct irq_chip_type *ct = gc->chip_types; 234 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; 235 int i; 236 237 for (i = 0; i < gc->num_ct; i++) { 238 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) { 239 mskptr = &ct[i].mask_cache_priv; 240 mskreg = ct[i].regs.mask; 241 } 242 ct[i].mask_cache = mskptr; 243 if (flags & IRQ_GC_INIT_MASK_CACHE) 244 *mskptr = irq_reg_readl(gc->reg_base + mskreg); 245 } 246 } 247 248 /** 249 * irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain 250 * @d: irq domain for which to allocate chips 251 * @irqs_per_chip: Number of interrupts each chip handles 252 * @num_ct: Number of irq_chip_type instances associated with this 253 * @name: Name of the irq chip 254 * @handler: Default flow handler associated with these chips 255 * @clr: IRQ_* bits to clear in the mapping function 256 * @set: IRQ_* bits to set in the mapping function 257 */ 258 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 259 int num_ct, const char *name, 260 irq_flow_handler_t handler, 261 unsigned int clr, unsigned int set, 262 enum irq_gc_flags gcflags) 263 { 264 struct irq_domain_chip_generic *dgc; 265 struct irq_chip_generic *gc; 266 int numchips, sz, i; 267 unsigned long flags; 268 void *tmp; 269 270 if (d->gc) 271 return -EBUSY; 272 273 if (d->revmap_type != IRQ_DOMAIN_MAP_LINEAR) 274 return -EINVAL; 275 276 numchips = d->revmap_data.linear.size / irqs_per_chip; 277 if (!numchips) 278 return -EINVAL; 279 280 /* Allocate a pointer, generic chip and chiptypes for each chip */ 281 sz = sizeof(*dgc) + numchips * sizeof(gc); 282 sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type)); 283 284 tmp = dgc = kzalloc(sz, GFP_KERNEL); 285 if (!dgc) 286 return -ENOMEM; 287 dgc->irqs_per_chip = irqs_per_chip; 288 dgc->num_chips = numchips; 289 dgc->irq_flags_to_set = set; 290 dgc->irq_flags_to_clear = clr; 291 dgc->gc_flags = gcflags; 292 d->gc = dgc; 293 294 /* Calc pointer to the first generic chip */ 295 tmp += sizeof(*dgc) + numchips * sizeof(gc); 296 for (i = 0; i < numchips; i++) { 297 /* Store the pointer to the generic chip */ 298 dgc->gc[i] = gc = tmp; 299 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip, 300 NULL, handler); 301 gc->domain = d; 302 raw_spin_lock_irqsave(&gc_lock, flags); 303 list_add_tail(&gc->list, &gc_list); 304 raw_spin_unlock_irqrestore(&gc_lock, flags); 305 /* Calc pointer to the next generic chip */ 306 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type); 307 } 308 d->name = name; 309 return 0; 310 } 311 EXPORT_SYMBOL_GPL(irq_alloc_domain_generic_chips); 312 313 /** 314 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq 315 * @d: irq domain pointer 316 * @hw_irq: Hardware interrupt number 317 */ 318 struct irq_chip_generic * 319 irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq) 320 { 321 struct irq_domain_chip_generic *dgc = d->gc; 322 int idx; 323 324 if (!dgc) 325 return NULL; 326 idx = hw_irq / dgc->irqs_per_chip; 327 if (idx >= dgc->num_chips) 328 return NULL; 329 return dgc->gc[idx]; 330 } 331 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip); 332 333 /* 334 * Separate lockdep class for interrupt chip which can nest irq_desc 335 * lock. 336 */ 337 static struct lock_class_key irq_nested_lock_class; 338 339 /** 340 * irq_map_generic_chip - Map a generic chip for an irq domain 341 */ 342 static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 343 irq_hw_number_t hw_irq) 344 { 345 struct irq_data *data = irq_get_irq_data(virq); 346 struct irq_domain_chip_generic *dgc = d->gc; 347 struct irq_chip_generic *gc; 348 struct irq_chip_type *ct; 349 struct irq_chip *chip; 350 unsigned long flags; 351 int idx; 352 353 if (!d->gc) 354 return -ENODEV; 355 356 idx = hw_irq / dgc->irqs_per_chip; 357 if (idx >= dgc->num_chips) 358 return -EINVAL; 359 gc = dgc->gc[idx]; 360 361 idx = hw_irq % dgc->irqs_per_chip; 362 363 if (test_bit(idx, &gc->unused)) 364 return -ENOTSUPP; 365 366 if (test_bit(idx, &gc->installed)) 367 return -EBUSY; 368 369 ct = gc->chip_types; 370 chip = &ct->chip; 371 372 /* We only init the cache for the first mapping of a generic chip */ 373 if (!gc->installed) { 374 raw_spin_lock_irqsave(&gc->lock, flags); 375 irq_gc_init_mask_cache(gc, dgc->gc_flags); 376 raw_spin_unlock_irqrestore(&gc->lock, flags); 377 } 378 379 /* Mark the interrupt as installed */ 380 set_bit(idx, &gc->installed); 381 382 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK) 383 irq_set_lockdep_class(virq, &irq_nested_lock_class); 384 385 if (chip->irq_calc_mask) 386 chip->irq_calc_mask(data); 387 else 388 data->mask = 1 << idx; 389 390 irq_set_chip_and_handler(virq, chip, ct->handler); 391 irq_set_chip_data(virq, gc); 392 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set); 393 return 0; 394 } 395 396 struct irq_domain_ops irq_generic_chip_ops = { 397 .map = irq_map_generic_chip, 398 .xlate = irq_domain_xlate_onetwocell, 399 }; 400 EXPORT_SYMBOL_GPL(irq_generic_chip_ops); 401 402 /** 403 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip 404 * @gc: Generic irq chip holding all data 405 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base 406 * @flags: Flags for initialization 407 * @clr: IRQ_* bits to clear 408 * @set: IRQ_* bits to set 409 * 410 * Set up max. 32 interrupts starting from gc->irq_base. Note, this 411 * initializes all interrupts to the primary irq_chip_type and its 412 * associated handler. 413 */ 414 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 415 enum irq_gc_flags flags, unsigned int clr, 416 unsigned int set) 417 { 418 struct irq_chip_type *ct = gc->chip_types; 419 struct irq_chip *chip = &ct->chip; 420 unsigned int i; 421 422 raw_spin_lock(&gc_lock); 423 list_add_tail(&gc->list, &gc_list); 424 raw_spin_unlock(&gc_lock); 425 426 irq_gc_init_mask_cache(gc, flags); 427 428 for (i = gc->irq_base; msk; msk >>= 1, i++) { 429 if (!(msk & 0x01)) 430 continue; 431 432 if (flags & IRQ_GC_INIT_NESTED_LOCK) 433 irq_set_lockdep_class(i, &irq_nested_lock_class); 434 435 if (!(flags & IRQ_GC_NO_MASK)) { 436 struct irq_data *d = irq_get_irq_data(i); 437 438 if (chip->irq_calc_mask) 439 chip->irq_calc_mask(d); 440 else 441 d->mask = 1 << (i - gc->irq_base); 442 } 443 irq_set_chip_and_handler(i, chip, ct->handler); 444 irq_set_chip_data(i, gc); 445 irq_modify_status(i, clr, set); 446 } 447 gc->irq_cnt = i - gc->irq_base; 448 } 449 EXPORT_SYMBOL_GPL(irq_setup_generic_chip); 450 451 /** 452 * irq_setup_alt_chip - Switch to alternative chip 453 * @d: irq_data for this interrupt 454 * @type Flow type to be initialized 455 * 456 * Only to be called from chip->irq_set_type() callbacks. 457 */ 458 int irq_setup_alt_chip(struct irq_data *d, unsigned int type) 459 { 460 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 461 struct irq_chip_type *ct = gc->chip_types; 462 unsigned int i; 463 464 for (i = 0; i < gc->num_ct; i++, ct++) { 465 if (ct->type & type) { 466 d->chip = &ct->chip; 467 irq_data_to_desc(d)->handle_irq = ct->handler; 468 return 0; 469 } 470 } 471 return -EINVAL; 472 } 473 EXPORT_SYMBOL_GPL(irq_setup_alt_chip); 474 475 /** 476 * irq_remove_generic_chip - Remove a chip 477 * @gc: Generic irq chip holding all data 478 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base 479 * @clr: IRQ_* bits to clear 480 * @set: IRQ_* bits to set 481 * 482 * Remove up to 32 interrupts starting from gc->irq_base. 483 */ 484 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 485 unsigned int clr, unsigned int set) 486 { 487 unsigned int i = gc->irq_base; 488 489 raw_spin_lock(&gc_lock); 490 list_del(&gc->list); 491 raw_spin_unlock(&gc_lock); 492 493 for (; msk; msk >>= 1, i++) { 494 if (!(msk & 0x01)) 495 continue; 496 497 /* Remove handler first. That will mask the irq line */ 498 irq_set_handler(i, NULL); 499 irq_set_chip(i, &no_irq_chip); 500 irq_set_chip_data(i, NULL); 501 irq_modify_status(i, clr, set); 502 } 503 } 504 EXPORT_SYMBOL_GPL(irq_remove_generic_chip); 505 506 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc) 507 { 508 unsigned int virq; 509 510 if (!gc->domain) 511 return irq_get_irq_data(gc->irq_base); 512 513 /* 514 * We don't know which of the irqs has been actually 515 * installed. Use the first one. 516 */ 517 if (!gc->installed) 518 return NULL; 519 520 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed)); 521 return virq ? irq_get_irq_data(virq) : NULL; 522 } 523 524 #ifdef CONFIG_PM 525 static int irq_gc_suspend(void) 526 { 527 struct irq_chip_generic *gc; 528 529 list_for_each_entry(gc, &gc_list, list) { 530 struct irq_chip_type *ct = gc->chip_types; 531 532 if (ct->chip.irq_suspend) { 533 struct irq_data *data = irq_gc_get_irq_data(gc); 534 535 if (data) 536 ct->chip.irq_suspend(data); 537 } 538 } 539 return 0; 540 } 541 542 static void irq_gc_resume(void) 543 { 544 struct irq_chip_generic *gc; 545 546 list_for_each_entry(gc, &gc_list, list) { 547 struct irq_chip_type *ct = gc->chip_types; 548 549 if (ct->chip.irq_resume) { 550 struct irq_data *data = irq_gc_get_irq_data(gc); 551 552 if (data) 553 ct->chip.irq_resume(data); 554 } 555 } 556 } 557 #else 558 #define irq_gc_suspend NULL 559 #define irq_gc_resume NULL 560 #endif 561 562 static void irq_gc_shutdown(void) 563 { 564 struct irq_chip_generic *gc; 565 566 list_for_each_entry(gc, &gc_list, list) { 567 struct irq_chip_type *ct = gc->chip_types; 568 569 if (ct->chip.irq_pm_shutdown) { 570 struct irq_data *data = irq_gc_get_irq_data(gc); 571 572 if (data) 573 ct->chip.irq_pm_shutdown(data); 574 } 575 } 576 } 577 578 static struct syscore_ops irq_gc_syscore_ops = { 579 .suspend = irq_gc_suspend, 580 .resume = irq_gc_resume, 581 .shutdown = irq_gc_shutdown, 582 }; 583 584 static int __init irq_gc_init_ops(void) 585 { 586 register_syscore_ops(&irq_gc_syscore_ops); 587 return 0; 588 } 589 device_initcall(irq_gc_init_ops); 590