1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright 2017 Thomas Gleixner <tglx@linutronix.de> 3 4 #include <linux/irqdomain.h> 5 #include <linux/irq.h> 6 #include <linux/uaccess.h> 7 8 #include "internals.h" 9 10 static struct dentry *irq_dir; 11 12 struct irq_bit_descr { 13 unsigned int mask; 14 char *name; 15 }; 16 #define BIT_MASK_DESCR(m) { .mask = m, .name = #m } 17 18 static void irq_debug_show_bits(struct seq_file *m, int ind, unsigned int state, 19 const struct irq_bit_descr *sd, int size) 20 { 21 int i; 22 23 for (i = 0; i < size; i++, sd++) { 24 if (state & sd->mask) 25 seq_printf(m, "%*s%s\n", ind + 12, "", sd->name); 26 } 27 } 28 29 #ifdef CONFIG_SMP 30 static void irq_debug_show_masks(struct seq_file *m, struct irq_desc *desc) 31 { 32 struct irq_data *data = irq_desc_get_irq_data(desc); 33 struct cpumask *msk; 34 35 msk = irq_data_get_affinity_mask(data); 36 seq_printf(m, "affinity: %*pbl\n", cpumask_pr_args(msk)); 37 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 38 msk = irq_data_get_effective_affinity_mask(data); 39 seq_printf(m, "effectiv: %*pbl\n", cpumask_pr_args(msk)); 40 #endif 41 #ifdef CONFIG_GENERIC_PENDING_IRQ 42 msk = desc->pending_mask; 43 seq_printf(m, "pending: %*pbl\n", cpumask_pr_args(msk)); 44 #endif 45 } 46 #else 47 static void irq_debug_show_masks(struct seq_file *m, struct irq_desc *desc) { } 48 #endif 49 50 static const struct irq_bit_descr irqchip_flags[] = { 51 BIT_MASK_DESCR(IRQCHIP_SET_TYPE_MASKED), 52 BIT_MASK_DESCR(IRQCHIP_EOI_IF_HANDLED), 53 BIT_MASK_DESCR(IRQCHIP_MASK_ON_SUSPEND), 54 BIT_MASK_DESCR(IRQCHIP_ONOFFLINE_ENABLED), 55 BIT_MASK_DESCR(IRQCHIP_SKIP_SET_WAKE), 56 BIT_MASK_DESCR(IRQCHIP_ONESHOT_SAFE), 57 BIT_MASK_DESCR(IRQCHIP_EOI_THREADED), 58 BIT_MASK_DESCR(IRQCHIP_SUPPORTS_LEVEL_MSI), 59 }; 60 61 static void 62 irq_debug_show_chip(struct seq_file *m, struct irq_data *data, int ind) 63 { 64 struct irq_chip *chip = data->chip; 65 66 if (!chip) { 67 seq_printf(m, "chip: None\n"); 68 return; 69 } 70 seq_printf(m, "%*schip: %s\n", ind, "", chip->name); 71 seq_printf(m, "%*sflags: 0x%lx\n", ind + 1, "", chip->flags); 72 irq_debug_show_bits(m, ind, chip->flags, irqchip_flags, 73 ARRAY_SIZE(irqchip_flags)); 74 } 75 76 static void 77 irq_debug_show_data(struct seq_file *m, struct irq_data *data, int ind) 78 { 79 seq_printf(m, "%*sdomain: %s\n", ind, "", 80 data->domain ? data->domain->name : ""); 81 seq_printf(m, "%*shwirq: 0x%lx\n", ind + 1, "", data->hwirq); 82 irq_debug_show_chip(m, data, ind + 1); 83 if (data->domain && data->domain->ops && data->domain->ops->debug_show) 84 data->domain->ops->debug_show(m, NULL, data, ind + 1); 85 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 86 if (!data->parent_data) 87 return; 88 seq_printf(m, "%*sparent:\n", ind + 1, ""); 89 irq_debug_show_data(m, data->parent_data, ind + 4); 90 #endif 91 } 92 93 static const struct irq_bit_descr irqdata_states[] = { 94 BIT_MASK_DESCR(IRQ_TYPE_EDGE_RISING), 95 BIT_MASK_DESCR(IRQ_TYPE_EDGE_FALLING), 96 BIT_MASK_DESCR(IRQ_TYPE_LEVEL_HIGH), 97 BIT_MASK_DESCR(IRQ_TYPE_LEVEL_LOW), 98 BIT_MASK_DESCR(IRQD_LEVEL), 99 100 BIT_MASK_DESCR(IRQD_ACTIVATED), 101 BIT_MASK_DESCR(IRQD_IRQ_STARTED), 102 BIT_MASK_DESCR(IRQD_IRQ_DISABLED), 103 BIT_MASK_DESCR(IRQD_IRQ_MASKED), 104 BIT_MASK_DESCR(IRQD_IRQ_INPROGRESS), 105 106 BIT_MASK_DESCR(IRQD_PER_CPU), 107 BIT_MASK_DESCR(IRQD_NO_BALANCING), 108 109 BIT_MASK_DESCR(IRQD_SINGLE_TARGET), 110 BIT_MASK_DESCR(IRQD_MOVE_PCNTXT), 111 BIT_MASK_DESCR(IRQD_AFFINITY_SET), 112 BIT_MASK_DESCR(IRQD_SETAFFINITY_PENDING), 113 BIT_MASK_DESCR(IRQD_AFFINITY_MANAGED), 114 BIT_MASK_DESCR(IRQD_MANAGED_SHUTDOWN), 115 BIT_MASK_DESCR(IRQD_CAN_RESERVE), 116 117 BIT_MASK_DESCR(IRQD_FORWARDED_TO_VCPU), 118 119 BIT_MASK_DESCR(IRQD_WAKEUP_STATE), 120 BIT_MASK_DESCR(IRQD_WAKEUP_ARMED), 121 }; 122 123 static const struct irq_bit_descr irqdesc_states[] = { 124 BIT_MASK_DESCR(_IRQ_NOPROBE), 125 BIT_MASK_DESCR(_IRQ_NOREQUEST), 126 BIT_MASK_DESCR(_IRQ_NOTHREAD), 127 BIT_MASK_DESCR(_IRQ_NOAUTOEN), 128 BIT_MASK_DESCR(_IRQ_NESTED_THREAD), 129 BIT_MASK_DESCR(_IRQ_PER_CPU_DEVID), 130 BIT_MASK_DESCR(_IRQ_IS_POLLED), 131 BIT_MASK_DESCR(_IRQ_DISABLE_UNLAZY), 132 }; 133 134 static const struct irq_bit_descr irqdesc_istates[] = { 135 BIT_MASK_DESCR(IRQS_AUTODETECT), 136 BIT_MASK_DESCR(IRQS_SPURIOUS_DISABLED), 137 BIT_MASK_DESCR(IRQS_POLL_INPROGRESS), 138 BIT_MASK_DESCR(IRQS_ONESHOT), 139 BIT_MASK_DESCR(IRQS_REPLAY), 140 BIT_MASK_DESCR(IRQS_WAITING), 141 BIT_MASK_DESCR(IRQS_PENDING), 142 BIT_MASK_DESCR(IRQS_SUSPENDED), 143 }; 144 145 146 static int irq_debug_show(struct seq_file *m, void *p) 147 { 148 struct irq_desc *desc = m->private; 149 struct irq_data *data; 150 151 raw_spin_lock_irq(&desc->lock); 152 data = irq_desc_get_irq_data(desc); 153 seq_printf(m, "handler: %pf\n", desc->handle_irq); 154 seq_printf(m, "device: %s\n", desc->dev_name); 155 seq_printf(m, "status: 0x%08x\n", desc->status_use_accessors); 156 irq_debug_show_bits(m, 0, desc->status_use_accessors, irqdesc_states, 157 ARRAY_SIZE(irqdesc_states)); 158 seq_printf(m, "istate: 0x%08x\n", desc->istate); 159 irq_debug_show_bits(m, 0, desc->istate, irqdesc_istates, 160 ARRAY_SIZE(irqdesc_istates)); 161 seq_printf(m, "ddepth: %u\n", desc->depth); 162 seq_printf(m, "wdepth: %u\n", desc->wake_depth); 163 seq_printf(m, "dstate: 0x%08x\n", irqd_get(data)); 164 irq_debug_show_bits(m, 0, irqd_get(data), irqdata_states, 165 ARRAY_SIZE(irqdata_states)); 166 seq_printf(m, "node: %d\n", irq_data_get_node(data)); 167 irq_debug_show_masks(m, desc); 168 irq_debug_show_data(m, data, 0); 169 raw_spin_unlock_irq(&desc->lock); 170 return 0; 171 } 172 173 static int irq_debug_open(struct inode *inode, struct file *file) 174 { 175 return single_open(file, irq_debug_show, inode->i_private); 176 } 177 178 static ssize_t irq_debug_write(struct file *file, const char __user *user_buf, 179 size_t count, loff_t *ppos) 180 { 181 struct irq_desc *desc = file_inode(file)->i_private; 182 char buf[8] = { 0, }; 183 size_t size; 184 185 size = min(sizeof(buf) - 1, count); 186 if (copy_from_user(buf, user_buf, size)) 187 return -EFAULT; 188 189 if (!strncmp(buf, "trigger", size)) { 190 unsigned long flags; 191 int err; 192 193 /* Try the HW interface first */ 194 err = irq_set_irqchip_state(irq_desc_get_irq(desc), 195 IRQCHIP_STATE_PENDING, true); 196 if (!err) 197 return count; 198 199 /* 200 * Otherwise, try to inject via the resend interface, 201 * which may or may not succeed. 202 */ 203 chip_bus_lock(desc); 204 raw_spin_lock_irqsave(&desc->lock, flags); 205 206 if (irq_settings_is_level(desc)) { 207 /* Can't do level, sorry */ 208 err = -EINVAL; 209 } else { 210 desc->istate |= IRQS_PENDING; 211 check_irq_resend(desc); 212 err = 0; 213 } 214 215 raw_spin_unlock_irqrestore(&desc->lock, flags); 216 chip_bus_sync_unlock(desc); 217 218 return err ? err : count; 219 } 220 221 return count; 222 } 223 224 static const struct file_operations dfs_irq_ops = { 225 .open = irq_debug_open, 226 .write = irq_debug_write, 227 .read = seq_read, 228 .llseek = seq_lseek, 229 .release = single_release, 230 }; 231 232 void irq_debugfs_copy_devname(int irq, struct device *dev) 233 { 234 struct irq_desc *desc = irq_to_desc(irq); 235 const char *name = dev_name(dev); 236 237 if (name) 238 desc->dev_name = kstrdup(name, GFP_KERNEL); 239 } 240 241 void irq_add_debugfs_entry(unsigned int irq, struct irq_desc *desc) 242 { 243 char name [10]; 244 245 if (!irq_dir || !desc || desc->debugfs_file) 246 return; 247 248 sprintf(name, "%d", irq); 249 desc->debugfs_file = debugfs_create_file(name, 0644, irq_dir, desc, 250 &dfs_irq_ops); 251 } 252 253 static int __init irq_debugfs_init(void) 254 { 255 struct dentry *root_dir; 256 int irq; 257 258 root_dir = debugfs_create_dir("irq", NULL); 259 if (!root_dir) 260 return -ENOMEM; 261 262 irq_domain_debugfs_init(root_dir); 263 264 irq_dir = debugfs_create_dir("irqs", root_dir); 265 266 irq_lock_sparse(); 267 for_each_active_irq(irq) 268 irq_add_debugfs_entry(irq, irq_to_desc(irq)); 269 irq_unlock_sparse(); 270 271 return 0; 272 } 273 __initcall(irq_debugfs_init); 274