xref: /openbmc/linux/kernel/dma/mapping.c (revision d0e22329)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * arch-independent dma-mapping routines
4  *
5  * Copyright (c) 2006  SUSE Linux Products GmbH
6  * Copyright (c) 2006  Tejun Heo <teheo@suse.de>
7  */
8 #include <linux/memblock.h> /* for max_pfn */
9 #include <linux/acpi.h>
10 #include <linux/dma-direct.h>
11 #include <linux/dma-noncoherent.h>
12 #include <linux/export.h>
13 #include <linux/gfp.h>
14 #include <linux/of_device.h>
15 #include <linux/slab.h>
16 #include <linux/vmalloc.h>
17 
18 /*
19  * Managed DMA API
20  */
21 struct dma_devres {
22 	size_t		size;
23 	void		*vaddr;
24 	dma_addr_t	dma_handle;
25 	unsigned long	attrs;
26 };
27 
28 static void dmam_release(struct device *dev, void *res)
29 {
30 	struct dma_devres *this = res;
31 
32 	dma_free_attrs(dev, this->size, this->vaddr, this->dma_handle,
33 			this->attrs);
34 }
35 
36 static int dmam_match(struct device *dev, void *res, void *match_data)
37 {
38 	struct dma_devres *this = res, *match = match_data;
39 
40 	if (this->vaddr == match->vaddr) {
41 		WARN_ON(this->size != match->size ||
42 			this->dma_handle != match->dma_handle);
43 		return 1;
44 	}
45 	return 0;
46 }
47 
48 /**
49  * dmam_free_coherent - Managed dma_free_coherent()
50  * @dev: Device to free coherent memory for
51  * @size: Size of allocation
52  * @vaddr: Virtual address of the memory to free
53  * @dma_handle: DMA handle of the memory to free
54  *
55  * Managed dma_free_coherent().
56  */
57 void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
58 			dma_addr_t dma_handle)
59 {
60 	struct dma_devres match_data = { size, vaddr, dma_handle };
61 
62 	dma_free_coherent(dev, size, vaddr, dma_handle);
63 	WARN_ON(devres_destroy(dev, dmam_release, dmam_match, &match_data));
64 }
65 EXPORT_SYMBOL(dmam_free_coherent);
66 
67 /**
68  * dmam_alloc_attrs - Managed dma_alloc_attrs()
69  * @dev: Device to allocate non_coherent memory for
70  * @size: Size of allocation
71  * @dma_handle: Out argument for allocated DMA handle
72  * @gfp: Allocation flags
73  * @attrs: Flags in the DMA_ATTR_* namespace.
74  *
75  * Managed dma_alloc_attrs().  Memory allocated using this function will be
76  * automatically released on driver detach.
77  *
78  * RETURNS:
79  * Pointer to allocated memory on success, NULL on failure.
80  */
81 void *dmam_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
82 		gfp_t gfp, unsigned long attrs)
83 {
84 	struct dma_devres *dr;
85 	void *vaddr;
86 
87 	dr = devres_alloc(dmam_release, sizeof(*dr), gfp);
88 	if (!dr)
89 		return NULL;
90 
91 	vaddr = dma_alloc_attrs(dev, size, dma_handle, gfp, attrs);
92 	if (!vaddr) {
93 		devres_free(dr);
94 		return NULL;
95 	}
96 
97 	dr->vaddr = vaddr;
98 	dr->dma_handle = *dma_handle;
99 	dr->size = size;
100 	dr->attrs = attrs;
101 
102 	devres_add(dev, dr);
103 
104 	return vaddr;
105 }
106 EXPORT_SYMBOL(dmam_alloc_attrs);
107 
108 /*
109  * Create scatter-list for the already allocated DMA buffer.
110  */
111 int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
112 		 void *cpu_addr, dma_addr_t dma_addr, size_t size,
113 		 unsigned long attrs)
114 {
115 	struct page *page;
116 	int ret;
117 
118 	if (!dev_is_dma_coherent(dev)) {
119 		if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN))
120 			return -ENXIO;
121 
122 		page = pfn_to_page(arch_dma_coherent_to_pfn(dev, cpu_addr,
123 				dma_addr));
124 	} else {
125 		page = virt_to_page(cpu_addr);
126 	}
127 
128 	ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
129 	if (!ret)
130 		sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
131 	return ret;
132 }
133 
134 int dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt,
135 		void *cpu_addr, dma_addr_t dma_addr, size_t size,
136 		unsigned long attrs)
137 {
138 	const struct dma_map_ops *ops = get_dma_ops(dev);
139 
140 	if (!dma_is_direct(ops) && ops->get_sgtable)
141 		return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size,
142 					attrs);
143 	return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr, size,
144 			attrs);
145 }
146 EXPORT_SYMBOL(dma_get_sgtable_attrs);
147 
148 /*
149  * Create userspace mapping for the DMA-coherent memory.
150  */
151 int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
152 		void *cpu_addr, dma_addr_t dma_addr, size_t size,
153 		unsigned long attrs)
154 {
155 #ifndef CONFIG_ARCH_NO_COHERENT_DMA_MMAP
156 	unsigned long user_count = vma_pages(vma);
157 	unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
158 	unsigned long off = vma->vm_pgoff;
159 	unsigned long pfn;
160 	int ret = -ENXIO;
161 
162 	vma->vm_page_prot = arch_dma_mmap_pgprot(dev, vma->vm_page_prot, attrs);
163 
164 	if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
165 		return ret;
166 
167 	if (off >= count || user_count > count - off)
168 		return -ENXIO;
169 
170 	if (!dev_is_dma_coherent(dev)) {
171 		if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN))
172 			return -ENXIO;
173 		pfn = arch_dma_coherent_to_pfn(dev, cpu_addr, dma_addr);
174 	} else {
175 		pfn = page_to_pfn(virt_to_page(cpu_addr));
176 	}
177 
178 	return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
179 			user_count << PAGE_SHIFT, vma->vm_page_prot);
180 #else
181 	return -ENXIO;
182 #endif /* !CONFIG_ARCH_NO_COHERENT_DMA_MMAP */
183 }
184 
185 /**
186  * dma_mmap_attrs - map a coherent DMA allocation into user space
187  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
188  * @vma: vm_area_struct describing requested user mapping
189  * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs
190  * @dma_addr: device-view address returned from dma_alloc_attrs
191  * @size: size of memory originally requested in dma_alloc_attrs
192  * @attrs: attributes of mapping properties requested in dma_alloc_attrs
193  *
194  * Map a coherent DMA buffer previously allocated by dma_alloc_attrs into user
195  * space.  The coherent DMA buffer must not be freed by the driver until the
196  * user space mapping has been released.
197  */
198 int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
199 		void *cpu_addr, dma_addr_t dma_addr, size_t size,
200 		unsigned long attrs)
201 {
202 	const struct dma_map_ops *ops = get_dma_ops(dev);
203 
204 	if (!dma_is_direct(ops) && ops->mmap)
205 		return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
206 	return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
207 }
208 EXPORT_SYMBOL(dma_mmap_attrs);
209 
210 #ifndef ARCH_HAS_DMA_GET_REQUIRED_MASK
211 static u64 dma_default_get_required_mask(struct device *dev)
212 {
213 	u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT);
214 	u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT));
215 	u64 mask;
216 
217 	if (!high_totalram) {
218 		/* convert to mask just covering totalram */
219 		low_totalram = (1 << (fls(low_totalram) - 1));
220 		low_totalram += low_totalram - 1;
221 		mask = low_totalram;
222 	} else {
223 		high_totalram = (1 << (fls(high_totalram) - 1));
224 		high_totalram += high_totalram - 1;
225 		mask = (((u64)high_totalram) << 32) + 0xffffffff;
226 	}
227 	return mask;
228 }
229 
230 u64 dma_get_required_mask(struct device *dev)
231 {
232 	const struct dma_map_ops *ops = get_dma_ops(dev);
233 
234 	if (dma_is_direct(ops))
235 		return dma_direct_get_required_mask(dev);
236 	if (ops->get_required_mask)
237 		return ops->get_required_mask(dev);
238 	return dma_default_get_required_mask(dev);
239 }
240 EXPORT_SYMBOL_GPL(dma_get_required_mask);
241 #endif
242 
243 #ifndef arch_dma_alloc_attrs
244 #define arch_dma_alloc_attrs(dev)	(true)
245 #endif
246 
247 void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
248 		gfp_t flag, unsigned long attrs)
249 {
250 	const struct dma_map_ops *ops = get_dma_ops(dev);
251 	void *cpu_addr;
252 
253 	WARN_ON_ONCE(dev && !dev->coherent_dma_mask);
254 
255 	if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr))
256 		return cpu_addr;
257 
258 	/* let the implementation decide on the zone to allocate from: */
259 	flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
260 
261 	if (!arch_dma_alloc_attrs(&dev))
262 		return NULL;
263 
264 	if (dma_is_direct(ops))
265 		cpu_addr = dma_direct_alloc(dev, size, dma_handle, flag, attrs);
266 	else if (ops->alloc)
267 		cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs);
268 	else
269 		return NULL;
270 
271 	debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
272 	return cpu_addr;
273 }
274 EXPORT_SYMBOL(dma_alloc_attrs);
275 
276 void dma_free_attrs(struct device *dev, size_t size, void *cpu_addr,
277 		dma_addr_t dma_handle, unsigned long attrs)
278 {
279 	const struct dma_map_ops *ops = get_dma_ops(dev);
280 
281 	if (dma_release_from_dev_coherent(dev, get_order(size), cpu_addr))
282 		return;
283 	/*
284 	 * On non-coherent platforms which implement DMA-coherent buffers via
285 	 * non-cacheable remaps, ops->free() may call vunmap(). Thus getting
286 	 * this far in IRQ context is a) at risk of a BUG_ON() or trying to
287 	 * sleep on some machines, and b) an indication that the driver is
288 	 * probably misusing the coherent API anyway.
289 	 */
290 	WARN_ON(irqs_disabled());
291 
292 	if (!cpu_addr)
293 		return;
294 
295 	debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
296 	if (dma_is_direct(ops))
297 		dma_direct_free(dev, size, cpu_addr, dma_handle, attrs);
298 	else if (ops->free)
299 		ops->free(dev, size, cpu_addr, dma_handle, attrs);
300 }
301 EXPORT_SYMBOL(dma_free_attrs);
302 
303 static inline void dma_check_mask(struct device *dev, u64 mask)
304 {
305 	if (sme_active() && (mask < (((u64)sme_get_me_mask() << 1) - 1)))
306 		dev_warn(dev, "SME is active, device will require DMA bounce buffers\n");
307 }
308 
309 int dma_supported(struct device *dev, u64 mask)
310 {
311 	const struct dma_map_ops *ops = get_dma_ops(dev);
312 
313 	if (dma_is_direct(ops))
314 		return dma_direct_supported(dev, mask);
315 	if (!ops->dma_supported)
316 		return 1;
317 	return ops->dma_supported(dev, mask);
318 }
319 EXPORT_SYMBOL(dma_supported);
320 
321 #ifndef HAVE_ARCH_DMA_SET_MASK
322 int dma_set_mask(struct device *dev, u64 mask)
323 {
324 	if (!dev->dma_mask || !dma_supported(dev, mask))
325 		return -EIO;
326 
327 	dma_check_mask(dev, mask);
328 	*dev->dma_mask = mask;
329 	return 0;
330 }
331 EXPORT_SYMBOL(dma_set_mask);
332 #endif
333 
334 #ifndef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
335 int dma_set_coherent_mask(struct device *dev, u64 mask)
336 {
337 	if (!dma_supported(dev, mask))
338 		return -EIO;
339 
340 	dma_check_mask(dev, mask);
341 	dev->coherent_dma_mask = mask;
342 	return 0;
343 }
344 EXPORT_SYMBOL(dma_set_coherent_mask);
345 #endif
346 
347 void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
348 		enum dma_data_direction dir)
349 {
350 	const struct dma_map_ops *ops = get_dma_ops(dev);
351 
352 	BUG_ON(!valid_dma_direction(dir));
353 
354 	if (dma_is_direct(ops))
355 		arch_dma_cache_sync(dev, vaddr, size, dir);
356 	else if (ops->cache_sync)
357 		ops->cache_sync(dev, vaddr, size, dir);
358 }
359 EXPORT_SYMBOL(dma_cache_sync);
360