1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch-independent dma-mapping routines 4 * 5 * Copyright (c) 2006 SUSE Linux Products GmbH 6 * Copyright (c) 2006 Tejun Heo <teheo@suse.de> 7 */ 8 #include <linux/memblock.h> /* for max_pfn */ 9 #include <linux/acpi.h> 10 #include <linux/dma-direct.h> 11 #include <linux/dma-noncoherent.h> 12 #include <linux/export.h> 13 #include <linux/gfp.h> 14 #include <linux/of_device.h> 15 #include <linux/slab.h> 16 #include <linux/vmalloc.h> 17 18 /* 19 * Managed DMA API 20 */ 21 struct dma_devres { 22 size_t size; 23 void *vaddr; 24 dma_addr_t dma_handle; 25 unsigned long attrs; 26 }; 27 28 static void dmam_release(struct device *dev, void *res) 29 { 30 struct dma_devres *this = res; 31 32 dma_free_attrs(dev, this->size, this->vaddr, this->dma_handle, 33 this->attrs); 34 } 35 36 static int dmam_match(struct device *dev, void *res, void *match_data) 37 { 38 struct dma_devres *this = res, *match = match_data; 39 40 if (this->vaddr == match->vaddr) { 41 WARN_ON(this->size != match->size || 42 this->dma_handle != match->dma_handle); 43 return 1; 44 } 45 return 0; 46 } 47 48 /** 49 * dmam_free_coherent - Managed dma_free_coherent() 50 * @dev: Device to free coherent memory for 51 * @size: Size of allocation 52 * @vaddr: Virtual address of the memory to free 53 * @dma_handle: DMA handle of the memory to free 54 * 55 * Managed dma_free_coherent(). 56 */ 57 void dmam_free_coherent(struct device *dev, size_t size, void *vaddr, 58 dma_addr_t dma_handle) 59 { 60 struct dma_devres match_data = { size, vaddr, dma_handle }; 61 62 dma_free_coherent(dev, size, vaddr, dma_handle); 63 WARN_ON(devres_destroy(dev, dmam_release, dmam_match, &match_data)); 64 } 65 EXPORT_SYMBOL(dmam_free_coherent); 66 67 /** 68 * dmam_alloc_attrs - Managed dma_alloc_attrs() 69 * @dev: Device to allocate non_coherent memory for 70 * @size: Size of allocation 71 * @dma_handle: Out argument for allocated DMA handle 72 * @gfp: Allocation flags 73 * @attrs: Flags in the DMA_ATTR_* namespace. 74 * 75 * Managed dma_alloc_attrs(). Memory allocated using this function will be 76 * automatically released on driver detach. 77 * 78 * RETURNS: 79 * Pointer to allocated memory on success, NULL on failure. 80 */ 81 void *dmam_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle, 82 gfp_t gfp, unsigned long attrs) 83 { 84 struct dma_devres *dr; 85 void *vaddr; 86 87 dr = devres_alloc(dmam_release, sizeof(*dr), gfp); 88 if (!dr) 89 return NULL; 90 91 vaddr = dma_alloc_attrs(dev, size, dma_handle, gfp, attrs); 92 if (!vaddr) { 93 devres_free(dr); 94 return NULL; 95 } 96 97 dr->vaddr = vaddr; 98 dr->dma_handle = *dma_handle; 99 dr->size = size; 100 dr->attrs = attrs; 101 102 devres_add(dev, dr); 103 104 return vaddr; 105 } 106 EXPORT_SYMBOL(dmam_alloc_attrs); 107 108 /* 109 * Create scatter-list for the already allocated DMA buffer. 110 */ 111 int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt, 112 void *cpu_addr, dma_addr_t dma_addr, size_t size, 113 unsigned long attrs) 114 { 115 struct page *page; 116 int ret; 117 118 if (!dev_is_dma_coherent(dev)) { 119 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN)) 120 return -ENXIO; 121 122 page = pfn_to_page(arch_dma_coherent_to_pfn(dev, cpu_addr, 123 dma_addr)); 124 } else { 125 page = virt_to_page(cpu_addr); 126 } 127 128 ret = sg_alloc_table(sgt, 1, GFP_KERNEL); 129 if (!ret) 130 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); 131 return ret; 132 } 133 134 int dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt, 135 void *cpu_addr, dma_addr_t dma_addr, size_t size, 136 unsigned long attrs) 137 { 138 const struct dma_map_ops *ops = get_dma_ops(dev); 139 140 if (!dma_is_direct(ops) && ops->get_sgtable) 141 return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, 142 attrs); 143 return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr, size, 144 attrs); 145 } 146 EXPORT_SYMBOL(dma_get_sgtable_attrs); 147 148 /* 149 * Create userspace mapping for the DMA-coherent memory. 150 */ 151 int dma_common_mmap(struct device *dev, struct vm_area_struct *vma, 152 void *cpu_addr, dma_addr_t dma_addr, size_t size, 153 unsigned long attrs) 154 { 155 #ifndef CONFIG_ARCH_NO_COHERENT_DMA_MMAP 156 unsigned long user_count = vma_pages(vma); 157 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT; 158 unsigned long off = vma->vm_pgoff; 159 unsigned long pfn; 160 int ret = -ENXIO; 161 162 vma->vm_page_prot = arch_dma_mmap_pgprot(dev, vma->vm_page_prot, attrs); 163 164 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) 165 return ret; 166 167 if (off >= count || user_count > count - off) 168 return -ENXIO; 169 170 if (!dev_is_dma_coherent(dev)) { 171 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN)) 172 return -ENXIO; 173 pfn = arch_dma_coherent_to_pfn(dev, cpu_addr, dma_addr); 174 } else { 175 pfn = page_to_pfn(virt_to_page(cpu_addr)); 176 } 177 178 return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff, 179 user_count << PAGE_SHIFT, vma->vm_page_prot); 180 #else 181 return -ENXIO; 182 #endif /* !CONFIG_ARCH_NO_COHERENT_DMA_MMAP */ 183 } 184 185 /** 186 * dma_mmap_attrs - map a coherent DMA allocation into user space 187 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices 188 * @vma: vm_area_struct describing requested user mapping 189 * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs 190 * @dma_addr: device-view address returned from dma_alloc_attrs 191 * @size: size of memory originally requested in dma_alloc_attrs 192 * @attrs: attributes of mapping properties requested in dma_alloc_attrs 193 * 194 * Map a coherent DMA buffer previously allocated by dma_alloc_attrs into user 195 * space. The coherent DMA buffer must not be freed by the driver until the 196 * user space mapping has been released. 197 */ 198 int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, 199 void *cpu_addr, dma_addr_t dma_addr, size_t size, 200 unsigned long attrs) 201 { 202 const struct dma_map_ops *ops = get_dma_ops(dev); 203 204 if (!dma_is_direct(ops) && ops->mmap) 205 return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs); 206 return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); 207 } 208 EXPORT_SYMBOL(dma_mmap_attrs); 209 210 static u64 dma_default_get_required_mask(struct device *dev) 211 { 212 u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT); 213 u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT)); 214 u64 mask; 215 216 if (!high_totalram) { 217 /* convert to mask just covering totalram */ 218 low_totalram = (1 << (fls(low_totalram) - 1)); 219 low_totalram += low_totalram - 1; 220 mask = low_totalram; 221 } else { 222 high_totalram = (1 << (fls(high_totalram) - 1)); 223 high_totalram += high_totalram - 1; 224 mask = (((u64)high_totalram) << 32) + 0xffffffff; 225 } 226 return mask; 227 } 228 229 u64 dma_get_required_mask(struct device *dev) 230 { 231 const struct dma_map_ops *ops = get_dma_ops(dev); 232 233 if (dma_is_direct(ops)) 234 return dma_direct_get_required_mask(dev); 235 if (ops->get_required_mask) 236 return ops->get_required_mask(dev); 237 return dma_default_get_required_mask(dev); 238 } 239 EXPORT_SYMBOL_GPL(dma_get_required_mask); 240 241 void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle, 242 gfp_t flag, unsigned long attrs) 243 { 244 const struct dma_map_ops *ops = get_dma_ops(dev); 245 void *cpu_addr; 246 247 WARN_ON_ONCE(!dev->coherent_dma_mask); 248 249 if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr)) 250 return cpu_addr; 251 252 /* let the implementation decide on the zone to allocate from: */ 253 flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); 254 255 if (dma_is_direct(ops)) 256 cpu_addr = dma_direct_alloc(dev, size, dma_handle, flag, attrs); 257 else if (ops->alloc) 258 cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs); 259 else 260 return NULL; 261 262 debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr); 263 return cpu_addr; 264 } 265 EXPORT_SYMBOL(dma_alloc_attrs); 266 267 void dma_free_attrs(struct device *dev, size_t size, void *cpu_addr, 268 dma_addr_t dma_handle, unsigned long attrs) 269 { 270 const struct dma_map_ops *ops = get_dma_ops(dev); 271 272 if (dma_release_from_dev_coherent(dev, get_order(size), cpu_addr)) 273 return; 274 /* 275 * On non-coherent platforms which implement DMA-coherent buffers via 276 * non-cacheable remaps, ops->free() may call vunmap(). Thus getting 277 * this far in IRQ context is a) at risk of a BUG_ON() or trying to 278 * sleep on some machines, and b) an indication that the driver is 279 * probably misusing the coherent API anyway. 280 */ 281 WARN_ON(irqs_disabled()); 282 283 if (!cpu_addr) 284 return; 285 286 debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); 287 if (dma_is_direct(ops)) 288 dma_direct_free(dev, size, cpu_addr, dma_handle, attrs); 289 else if (ops->free) 290 ops->free(dev, size, cpu_addr, dma_handle, attrs); 291 } 292 EXPORT_SYMBOL(dma_free_attrs); 293 294 static inline void dma_check_mask(struct device *dev, u64 mask) 295 { 296 if (sme_active() && (mask < (((u64)sme_get_me_mask() << 1) - 1))) 297 dev_warn(dev, "SME is active, device will require DMA bounce buffers\n"); 298 } 299 300 int dma_supported(struct device *dev, u64 mask) 301 { 302 const struct dma_map_ops *ops = get_dma_ops(dev); 303 304 if (dma_is_direct(ops)) 305 return dma_direct_supported(dev, mask); 306 if (!ops->dma_supported) 307 return 1; 308 return ops->dma_supported(dev, mask); 309 } 310 EXPORT_SYMBOL(dma_supported); 311 312 #ifdef CONFIG_ARCH_HAS_DMA_SET_MASK 313 void arch_dma_set_mask(struct device *dev, u64 mask); 314 #else 315 #define arch_dma_set_mask(dev, mask) do { } while (0) 316 #endif 317 318 int dma_set_mask(struct device *dev, u64 mask) 319 { 320 /* 321 * Truncate the mask to the actually supported dma_addr_t width to 322 * avoid generating unsupportable addresses. 323 */ 324 mask = (dma_addr_t)mask; 325 326 if (!dev->dma_mask || !dma_supported(dev, mask)) 327 return -EIO; 328 329 arch_dma_set_mask(dev, mask); 330 dma_check_mask(dev, mask); 331 *dev->dma_mask = mask; 332 return 0; 333 } 334 EXPORT_SYMBOL(dma_set_mask); 335 336 #ifndef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK 337 int dma_set_coherent_mask(struct device *dev, u64 mask) 338 { 339 /* 340 * Truncate the mask to the actually supported dma_addr_t width to 341 * avoid generating unsupportable addresses. 342 */ 343 mask = (dma_addr_t)mask; 344 345 if (!dma_supported(dev, mask)) 346 return -EIO; 347 348 dma_check_mask(dev, mask); 349 dev->coherent_dma_mask = mask; 350 return 0; 351 } 352 EXPORT_SYMBOL(dma_set_coherent_mask); 353 #endif 354 355 void dma_cache_sync(struct device *dev, void *vaddr, size_t size, 356 enum dma_data_direction dir) 357 { 358 const struct dma_map_ops *ops = get_dma_ops(dev); 359 360 BUG_ON(!valid_dma_direction(dir)); 361 362 if (dma_is_direct(ops)) 363 arch_dma_cache_sync(dev, vaddr, size, dir); 364 else if (ops->cache_sync) 365 ops->cache_sync(dev, vaddr, size, dir); 366 } 367 EXPORT_SYMBOL(dma_cache_sync); 368 369 size_t dma_max_mapping_size(struct device *dev) 370 { 371 const struct dma_map_ops *ops = get_dma_ops(dev); 372 size_t size = SIZE_MAX; 373 374 if (dma_is_direct(ops)) 375 size = dma_direct_max_mapping_size(dev); 376 else if (ops && ops->max_mapping_size) 377 size = ops->max_mapping_size(dev); 378 379 return size; 380 } 381 EXPORT_SYMBOL_GPL(dma_max_mapping_size); 382