1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Christoph Hellwig. 4 * 5 * DMA operations that map physical memory directly without using an IOMMU. 6 */ 7 #include <linux/memblock.h> /* for max_pfn */ 8 #include <linux/export.h> 9 #include <linux/mm.h> 10 #include <linux/dma-direct.h> 11 #include <linux/scatterlist.h> 12 #include <linux/dma-contiguous.h> 13 #include <linux/pfn.h> 14 #include <linux/vmalloc.h> 15 #include <linux/set_memory.h> 16 17 /* 18 * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use it 19 * it for entirely different regions. In that case the arch code needs to 20 * override the variable below for dma-direct to work properly. 21 */ 22 unsigned int zone_dma_bits __ro_after_init = 24; 23 24 static inline dma_addr_t phys_to_dma_direct(struct device *dev, 25 phys_addr_t phys) 26 { 27 if (force_dma_unencrypted(dev)) 28 return __phys_to_dma(dev, phys); 29 return phys_to_dma(dev, phys); 30 } 31 32 static inline struct page *dma_direct_to_page(struct device *dev, 33 dma_addr_t dma_addr) 34 { 35 return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr))); 36 } 37 38 u64 dma_direct_get_required_mask(struct device *dev) 39 { 40 phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT; 41 u64 max_dma = phys_to_dma_direct(dev, phys); 42 43 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1; 44 } 45 46 gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask, 47 u64 *phys_limit) 48 { 49 u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit); 50 51 if (force_dma_unencrypted(dev)) 52 *phys_limit = __dma_to_phys(dev, dma_limit); 53 else 54 *phys_limit = dma_to_phys(dev, dma_limit); 55 56 /* 57 * Optimistically try the zone that the physical address mask falls 58 * into first. If that returns memory that isn't actually addressable 59 * we will fallback to the next lower zone and try again. 60 * 61 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding 62 * zones. 63 */ 64 if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits)) 65 return GFP_DMA; 66 if (*phys_limit <= DMA_BIT_MASK(32)) 67 return GFP_DMA32; 68 return 0; 69 } 70 71 bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size) 72 { 73 return phys_to_dma_direct(dev, phys) + size - 1 <= 74 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit); 75 } 76 77 /* 78 * Decrypting memory is allowed to block, so if this device requires 79 * unencrypted memory it must come from atomic pools. 80 */ 81 static inline bool dma_should_alloc_from_pool(struct device *dev, gfp_t gfp, 82 unsigned long attrs) 83 { 84 if (!IS_ENABLED(CONFIG_DMA_COHERENT_POOL)) 85 return false; 86 if (gfpflags_allow_blocking(gfp)) 87 return false; 88 if (force_dma_unencrypted(dev)) 89 return true; 90 if (!IS_ENABLED(CONFIG_DMA_DIRECT_REMAP)) 91 return false; 92 if (dma_alloc_need_uncached(dev, attrs)) 93 return true; 94 return false; 95 } 96 97 static inline bool dma_should_free_from_pool(struct device *dev, 98 unsigned long attrs) 99 { 100 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL)) 101 return true; 102 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) && 103 !force_dma_unencrypted(dev)) 104 return false; 105 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP)) 106 return true; 107 return false; 108 } 109 110 static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size, 111 gfp_t gfp, unsigned long attrs) 112 { 113 int node = dev_to_node(dev); 114 struct page *page = NULL; 115 u64 phys_limit; 116 117 WARN_ON_ONCE(!PAGE_ALIGNED(size)); 118 119 if (attrs & DMA_ATTR_NO_WARN) 120 gfp |= __GFP_NOWARN; 121 122 /* we always manually zero the memory once we are done: */ 123 gfp &= ~__GFP_ZERO; 124 gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask, 125 &phys_limit); 126 page = dma_alloc_contiguous(dev, size, gfp); 127 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) { 128 dma_free_contiguous(dev, page, size); 129 page = NULL; 130 } 131 again: 132 if (!page) 133 page = alloc_pages_node(node, gfp, get_order(size)); 134 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) { 135 dma_free_contiguous(dev, page, size); 136 page = NULL; 137 138 if (IS_ENABLED(CONFIG_ZONE_DMA32) && 139 phys_limit < DMA_BIT_MASK(64) && 140 !(gfp & (GFP_DMA32 | GFP_DMA))) { 141 gfp |= GFP_DMA32; 142 goto again; 143 } 144 145 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) { 146 gfp = (gfp & ~GFP_DMA32) | GFP_DMA; 147 goto again; 148 } 149 } 150 151 return page; 152 } 153 154 void *dma_direct_alloc_pages(struct device *dev, size_t size, 155 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) 156 { 157 struct page *page; 158 void *ret; 159 int err; 160 161 size = PAGE_ALIGN(size); 162 163 if (dma_should_alloc_from_pool(dev, gfp, attrs)) { 164 ret = dma_alloc_from_pool(dev, size, &page, gfp); 165 if (!ret) 166 return NULL; 167 goto done; 168 } 169 170 page = __dma_direct_alloc_pages(dev, size, gfp, attrs); 171 if (!page) 172 return NULL; 173 174 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) && 175 !force_dma_unencrypted(dev)) { 176 /* remove any dirty cache lines on the kernel alias */ 177 if (!PageHighMem(page)) 178 arch_dma_prep_coherent(page, size); 179 /* return the page pointer as the opaque cookie */ 180 ret = page; 181 goto done; 182 } 183 184 if ((IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 185 dma_alloc_need_uncached(dev, attrs)) || 186 (IS_ENABLED(CONFIG_DMA_REMAP) && PageHighMem(page))) { 187 /* remove any dirty cache lines on the kernel alias */ 188 arch_dma_prep_coherent(page, size); 189 190 /* create a coherent mapping */ 191 ret = dma_common_contiguous_remap(page, size, 192 dma_pgprot(dev, PAGE_KERNEL, attrs), 193 __builtin_return_address(0)); 194 if (!ret) 195 goto out_free_pages; 196 if (force_dma_unencrypted(dev)) { 197 err = set_memory_decrypted((unsigned long)ret, 198 1 << get_order(size)); 199 if (err) 200 goto out_free_pages; 201 } 202 memset(ret, 0, size); 203 goto done; 204 } 205 206 if (PageHighMem(page)) { 207 /* 208 * Depending on the cma= arguments and per-arch setup 209 * dma_alloc_contiguous could return highmem pages. 210 * Without remapping there is no way to return them here, 211 * so log an error and fail. 212 */ 213 dev_info(dev, "Rejecting highmem page from CMA.\n"); 214 goto out_free_pages; 215 } 216 217 ret = page_address(page); 218 if (force_dma_unencrypted(dev)) { 219 err = set_memory_decrypted((unsigned long)ret, 220 1 << get_order(size)); 221 if (err) 222 goto out_free_pages; 223 } 224 225 memset(ret, 0, size); 226 227 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) && 228 dma_alloc_need_uncached(dev, attrs)) { 229 arch_dma_prep_coherent(page, size); 230 ret = arch_dma_set_uncached(ret, size); 231 if (IS_ERR(ret)) 232 goto out_encrypt_pages; 233 } 234 done: 235 if (force_dma_unencrypted(dev)) 236 *dma_handle = __phys_to_dma(dev, page_to_phys(page)); 237 else 238 *dma_handle = phys_to_dma(dev, page_to_phys(page)); 239 return ret; 240 241 out_encrypt_pages: 242 if (force_dma_unencrypted(dev)) { 243 err = set_memory_encrypted((unsigned long)page_address(page), 244 1 << get_order(size)); 245 /* If memory cannot be re-encrypted, it must be leaked */ 246 if (err) 247 return NULL; 248 } 249 out_free_pages: 250 dma_free_contiguous(dev, page, size); 251 return NULL; 252 } 253 254 void dma_direct_free_pages(struct device *dev, size_t size, void *cpu_addr, 255 dma_addr_t dma_addr, unsigned long attrs) 256 { 257 unsigned int page_order = get_order(size); 258 259 /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */ 260 if (dma_should_free_from_pool(dev, attrs) && 261 dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size))) 262 return; 263 264 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) && 265 !force_dma_unencrypted(dev)) { 266 /* cpu_addr is a struct page cookie, not a kernel address */ 267 dma_free_contiguous(dev, cpu_addr, size); 268 return; 269 } 270 271 if (force_dma_unencrypted(dev)) 272 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order); 273 274 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) 275 vunmap(cpu_addr); 276 else if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED)) 277 arch_dma_clear_uncached(cpu_addr, size); 278 279 dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size); 280 } 281 282 void *dma_direct_alloc(struct device *dev, size_t size, 283 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) 284 { 285 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) && 286 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 287 dma_alloc_need_uncached(dev, attrs)) 288 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs); 289 return dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs); 290 } 291 292 void dma_direct_free(struct device *dev, size_t size, 293 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs) 294 { 295 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) && 296 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 297 dma_alloc_need_uncached(dev, attrs)) 298 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs); 299 else 300 dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs); 301 } 302 303 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ 304 defined(CONFIG_SWIOTLB) 305 void dma_direct_sync_sg_for_device(struct device *dev, 306 struct scatterlist *sgl, int nents, enum dma_data_direction dir) 307 { 308 struct scatterlist *sg; 309 int i; 310 311 for_each_sg(sgl, sg, nents, i) { 312 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg)); 313 314 if (unlikely(is_swiotlb_buffer(paddr))) 315 swiotlb_tbl_sync_single(dev, paddr, sg->length, 316 dir, SYNC_FOR_DEVICE); 317 318 if (!dev_is_dma_coherent(dev)) 319 arch_sync_dma_for_device(paddr, sg->length, 320 dir); 321 } 322 } 323 #endif 324 325 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ 326 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \ 327 defined(CONFIG_SWIOTLB) 328 void dma_direct_sync_sg_for_cpu(struct device *dev, 329 struct scatterlist *sgl, int nents, enum dma_data_direction dir) 330 { 331 struct scatterlist *sg; 332 int i; 333 334 for_each_sg(sgl, sg, nents, i) { 335 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg)); 336 337 if (!dev_is_dma_coherent(dev)) 338 arch_sync_dma_for_cpu(paddr, sg->length, dir); 339 340 if (unlikely(is_swiotlb_buffer(paddr))) 341 swiotlb_tbl_sync_single(dev, paddr, sg->length, dir, 342 SYNC_FOR_CPU); 343 } 344 345 if (!dev_is_dma_coherent(dev)) 346 arch_sync_dma_for_cpu_all(); 347 } 348 349 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl, 350 int nents, enum dma_data_direction dir, unsigned long attrs) 351 { 352 struct scatterlist *sg; 353 int i; 354 355 for_each_sg(sgl, sg, nents, i) 356 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir, 357 attrs); 358 } 359 #endif 360 361 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents, 362 enum dma_data_direction dir, unsigned long attrs) 363 { 364 int i; 365 struct scatterlist *sg; 366 367 for_each_sg(sgl, sg, nents, i) { 368 sg->dma_address = dma_direct_map_page(dev, sg_page(sg), 369 sg->offset, sg->length, dir, attrs); 370 if (sg->dma_address == DMA_MAPPING_ERROR) 371 goto out_unmap; 372 sg_dma_len(sg) = sg->length; 373 } 374 375 return nents; 376 377 out_unmap: 378 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC); 379 return 0; 380 } 381 382 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr, 383 size_t size, enum dma_data_direction dir, unsigned long attrs) 384 { 385 dma_addr_t dma_addr = paddr; 386 387 if (unlikely(!dma_capable(dev, dma_addr, size, false))) { 388 dev_err_once(dev, 389 "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n", 390 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit); 391 WARN_ON_ONCE(1); 392 return DMA_MAPPING_ERROR; 393 } 394 395 return dma_addr; 396 } 397 398 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt, 399 void *cpu_addr, dma_addr_t dma_addr, size_t size, 400 unsigned long attrs) 401 { 402 struct page *page = dma_direct_to_page(dev, dma_addr); 403 int ret; 404 405 ret = sg_alloc_table(sgt, 1, GFP_KERNEL); 406 if (!ret) 407 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); 408 return ret; 409 } 410 411 bool dma_direct_can_mmap(struct device *dev) 412 { 413 return dev_is_dma_coherent(dev) || 414 IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP); 415 } 416 417 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma, 418 void *cpu_addr, dma_addr_t dma_addr, size_t size, 419 unsigned long attrs) 420 { 421 unsigned long user_count = vma_pages(vma); 422 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT; 423 unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr)); 424 int ret = -ENXIO; 425 426 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs); 427 428 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) 429 return ret; 430 431 if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff) 432 return -ENXIO; 433 return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff, 434 user_count << PAGE_SHIFT, vma->vm_page_prot); 435 } 436 437 int dma_direct_supported(struct device *dev, u64 mask) 438 { 439 u64 min_mask = (max_pfn - 1) << PAGE_SHIFT; 440 441 /* 442 * Because 32-bit DMA masks are so common we expect every architecture 443 * to be able to satisfy them - either by not supporting more physical 444 * memory, or by providing a ZONE_DMA32. If neither is the case, the 445 * architecture needs to use an IOMMU instead of the direct mapping. 446 */ 447 if (mask >= DMA_BIT_MASK(32)) 448 return 1; 449 450 /* 451 * This check needs to be against the actual bit mask value, so 452 * use __phys_to_dma() here so that the SME encryption mask isn't 453 * part of the check. 454 */ 455 if (IS_ENABLED(CONFIG_ZONE_DMA)) 456 min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits)); 457 return mask >= __phys_to_dma(dev, min_mask); 458 } 459 460 size_t dma_direct_max_mapping_size(struct device *dev) 461 { 462 /* If SWIOTLB is active, use its maximum mapping size */ 463 if (is_swiotlb_active() && 464 (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE)) 465 return swiotlb_max_mapping_size(dev); 466 return SIZE_MAX; 467 } 468 469 bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr) 470 { 471 return !dev_is_dma_coherent(dev) || 472 is_swiotlb_buffer(dma_to_phys(dev, dma_addr)); 473 } 474