1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Christoph Hellwig. 4 * 5 * DMA operations that map physical memory directly without using an IOMMU. 6 */ 7 #include <linux/memblock.h> /* for max_pfn */ 8 #include <linux/export.h> 9 #include <linux/mm.h> 10 #include <linux/dma-direct.h> 11 #include <linux/scatterlist.h> 12 #include <linux/dma-contiguous.h> 13 #include <linux/dma-noncoherent.h> 14 #include <linux/pfn.h> 15 #include <linux/vmalloc.h> 16 #include <linux/set_memory.h> 17 #include <linux/swiotlb.h> 18 19 /* 20 * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use it 21 * it for entirely different regions. In that case the arch code needs to 22 * override the variable below for dma-direct to work properly. 23 */ 24 unsigned int zone_dma_bits __ro_after_init = 24; 25 26 static inline dma_addr_t phys_to_dma_direct(struct device *dev, 27 phys_addr_t phys) 28 { 29 if (force_dma_unencrypted(dev)) 30 return __phys_to_dma(dev, phys); 31 return phys_to_dma(dev, phys); 32 } 33 34 static inline struct page *dma_direct_to_page(struct device *dev, 35 dma_addr_t dma_addr) 36 { 37 return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr))); 38 } 39 40 u64 dma_direct_get_required_mask(struct device *dev) 41 { 42 u64 max_dma = phys_to_dma_direct(dev, (max_pfn - 1) << PAGE_SHIFT); 43 44 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1; 45 } 46 47 static gfp_t __dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask, 48 u64 *phys_limit) 49 { 50 u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit); 51 52 if (force_dma_unencrypted(dev)) 53 *phys_limit = __dma_to_phys(dev, dma_limit); 54 else 55 *phys_limit = dma_to_phys(dev, dma_limit); 56 57 /* 58 * Optimistically try the zone that the physical address mask falls 59 * into first. If that returns memory that isn't actually addressable 60 * we will fallback to the next lower zone and try again. 61 * 62 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding 63 * zones. 64 */ 65 if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits)) 66 return GFP_DMA; 67 if (*phys_limit <= DMA_BIT_MASK(32)) 68 return GFP_DMA32; 69 return 0; 70 } 71 72 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size) 73 { 74 return phys_to_dma_direct(dev, phys) + size - 1 <= 75 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit); 76 } 77 78 struct page *__dma_direct_alloc_pages(struct device *dev, size_t size, 79 gfp_t gfp, unsigned long attrs) 80 { 81 size_t alloc_size = PAGE_ALIGN(size); 82 int node = dev_to_node(dev); 83 struct page *page = NULL; 84 u64 phys_limit; 85 86 if (attrs & DMA_ATTR_NO_WARN) 87 gfp |= __GFP_NOWARN; 88 89 /* we always manually zero the memory once we are done: */ 90 gfp &= ~__GFP_ZERO; 91 gfp |= __dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask, 92 &phys_limit); 93 page = dma_alloc_contiguous(dev, alloc_size, gfp); 94 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) { 95 dma_free_contiguous(dev, page, alloc_size); 96 page = NULL; 97 } 98 again: 99 if (!page) 100 page = alloc_pages_node(node, gfp, get_order(alloc_size)); 101 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) { 102 dma_free_contiguous(dev, page, size); 103 page = NULL; 104 105 if (IS_ENABLED(CONFIG_ZONE_DMA32) && 106 phys_limit < DMA_BIT_MASK(64) && 107 !(gfp & (GFP_DMA32 | GFP_DMA))) { 108 gfp |= GFP_DMA32; 109 goto again; 110 } 111 112 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) { 113 gfp = (gfp & ~GFP_DMA32) | GFP_DMA; 114 goto again; 115 } 116 } 117 118 return page; 119 } 120 121 void *dma_direct_alloc_pages(struct device *dev, size_t size, 122 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) 123 { 124 struct page *page; 125 void *ret; 126 127 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 128 dma_alloc_need_uncached(dev, attrs) && 129 !gfpflags_allow_blocking(gfp)) { 130 ret = dma_alloc_from_pool(PAGE_ALIGN(size), &page, gfp); 131 if (!ret) 132 return NULL; 133 goto done; 134 } 135 136 page = __dma_direct_alloc_pages(dev, size, gfp, attrs); 137 if (!page) 138 return NULL; 139 140 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) && 141 !force_dma_unencrypted(dev)) { 142 /* remove any dirty cache lines on the kernel alias */ 143 if (!PageHighMem(page)) 144 arch_dma_prep_coherent(page, size); 145 /* return the page pointer as the opaque cookie */ 146 ret = page; 147 goto done; 148 } 149 150 if ((IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 151 dma_alloc_need_uncached(dev, attrs)) || 152 (IS_ENABLED(CONFIG_DMA_REMAP) && PageHighMem(page))) { 153 /* remove any dirty cache lines on the kernel alias */ 154 arch_dma_prep_coherent(page, PAGE_ALIGN(size)); 155 156 /* create a coherent mapping */ 157 ret = dma_common_contiguous_remap(page, PAGE_ALIGN(size), 158 dma_pgprot(dev, PAGE_KERNEL, attrs), 159 __builtin_return_address(0)); 160 if (!ret) 161 goto out_free_pages; 162 memset(ret, 0, size); 163 goto done; 164 } 165 166 if (PageHighMem(page)) { 167 /* 168 * Depending on the cma= arguments and per-arch setup 169 * dma_alloc_contiguous could return highmem pages. 170 * Without remapping there is no way to return them here, 171 * so log an error and fail. 172 */ 173 dev_info(dev, "Rejecting highmem page from CMA.\n"); 174 goto out_free_pages; 175 } 176 177 ret = page_address(page); 178 if (force_dma_unencrypted(dev)) 179 set_memory_decrypted((unsigned long)ret, 1 << get_order(size)); 180 181 memset(ret, 0, size); 182 183 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) && 184 dma_alloc_need_uncached(dev, attrs)) { 185 arch_dma_prep_coherent(page, size); 186 ret = arch_dma_set_uncached(ret, size); 187 if (IS_ERR(ret)) 188 goto out_free_pages; 189 } 190 done: 191 if (force_dma_unencrypted(dev)) 192 *dma_handle = __phys_to_dma(dev, page_to_phys(page)); 193 else 194 *dma_handle = phys_to_dma(dev, page_to_phys(page)); 195 return ret; 196 out_free_pages: 197 dma_free_contiguous(dev, page, size); 198 return NULL; 199 } 200 201 void dma_direct_free_pages(struct device *dev, size_t size, void *cpu_addr, 202 dma_addr_t dma_addr, unsigned long attrs) 203 { 204 unsigned int page_order = get_order(size); 205 206 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) && 207 !force_dma_unencrypted(dev)) { 208 /* cpu_addr is a struct page cookie, not a kernel address */ 209 dma_free_contiguous(dev, cpu_addr, size); 210 return; 211 } 212 213 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 214 dma_free_from_pool(cpu_addr, PAGE_ALIGN(size))) 215 return; 216 217 if (force_dma_unencrypted(dev)) 218 set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order); 219 220 if (IS_ENABLED(CONFIG_DMA_REMAP) && is_vmalloc_addr(cpu_addr)) 221 vunmap(cpu_addr); 222 else if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED)) 223 arch_dma_clear_uncached(cpu_addr, size); 224 225 dma_free_contiguous(dev, dma_direct_to_page(dev, dma_addr), size); 226 } 227 228 void *dma_direct_alloc(struct device *dev, size_t size, 229 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs) 230 { 231 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) && 232 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 233 dma_alloc_need_uncached(dev, attrs)) 234 return arch_dma_alloc(dev, size, dma_handle, gfp, attrs); 235 return dma_direct_alloc_pages(dev, size, dma_handle, gfp, attrs); 236 } 237 238 void dma_direct_free(struct device *dev, size_t size, 239 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs) 240 { 241 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) && 242 !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) && 243 dma_alloc_need_uncached(dev, attrs)) 244 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs); 245 else 246 dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs); 247 } 248 249 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ 250 defined(CONFIG_SWIOTLB) 251 void dma_direct_sync_single_for_device(struct device *dev, 252 dma_addr_t addr, size_t size, enum dma_data_direction dir) 253 { 254 phys_addr_t paddr = dma_to_phys(dev, addr); 255 256 if (unlikely(is_swiotlb_buffer(paddr))) 257 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_DEVICE); 258 259 if (!dev_is_dma_coherent(dev)) 260 arch_sync_dma_for_device(paddr, size, dir); 261 } 262 EXPORT_SYMBOL(dma_direct_sync_single_for_device); 263 264 void dma_direct_sync_sg_for_device(struct device *dev, 265 struct scatterlist *sgl, int nents, enum dma_data_direction dir) 266 { 267 struct scatterlist *sg; 268 int i; 269 270 for_each_sg(sgl, sg, nents, i) { 271 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg)); 272 273 if (unlikely(is_swiotlb_buffer(paddr))) 274 swiotlb_tbl_sync_single(dev, paddr, sg->length, 275 dir, SYNC_FOR_DEVICE); 276 277 if (!dev_is_dma_coherent(dev)) 278 arch_sync_dma_for_device(paddr, sg->length, 279 dir); 280 } 281 } 282 EXPORT_SYMBOL(dma_direct_sync_sg_for_device); 283 #endif 284 285 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \ 286 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \ 287 defined(CONFIG_SWIOTLB) 288 void dma_direct_sync_single_for_cpu(struct device *dev, 289 dma_addr_t addr, size_t size, enum dma_data_direction dir) 290 { 291 phys_addr_t paddr = dma_to_phys(dev, addr); 292 293 if (!dev_is_dma_coherent(dev)) { 294 arch_sync_dma_for_cpu(paddr, size, dir); 295 arch_sync_dma_for_cpu_all(); 296 } 297 298 if (unlikely(is_swiotlb_buffer(paddr))) 299 swiotlb_tbl_sync_single(dev, paddr, size, dir, SYNC_FOR_CPU); 300 } 301 EXPORT_SYMBOL(dma_direct_sync_single_for_cpu); 302 303 void dma_direct_sync_sg_for_cpu(struct device *dev, 304 struct scatterlist *sgl, int nents, enum dma_data_direction dir) 305 { 306 struct scatterlist *sg; 307 int i; 308 309 for_each_sg(sgl, sg, nents, i) { 310 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg)); 311 312 if (!dev_is_dma_coherent(dev)) 313 arch_sync_dma_for_cpu(paddr, sg->length, dir); 314 315 if (unlikely(is_swiotlb_buffer(paddr))) 316 swiotlb_tbl_sync_single(dev, paddr, sg->length, dir, 317 SYNC_FOR_CPU); 318 } 319 320 if (!dev_is_dma_coherent(dev)) 321 arch_sync_dma_for_cpu_all(); 322 } 323 EXPORT_SYMBOL(dma_direct_sync_sg_for_cpu); 324 325 void dma_direct_unmap_page(struct device *dev, dma_addr_t addr, 326 size_t size, enum dma_data_direction dir, unsigned long attrs) 327 { 328 phys_addr_t phys = dma_to_phys(dev, addr); 329 330 if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) 331 dma_direct_sync_single_for_cpu(dev, addr, size, dir); 332 333 if (unlikely(is_swiotlb_buffer(phys))) 334 swiotlb_tbl_unmap_single(dev, phys, size, size, dir, attrs); 335 } 336 EXPORT_SYMBOL(dma_direct_unmap_page); 337 338 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl, 339 int nents, enum dma_data_direction dir, unsigned long attrs) 340 { 341 struct scatterlist *sg; 342 int i; 343 344 for_each_sg(sgl, sg, nents, i) 345 dma_direct_unmap_page(dev, sg->dma_address, sg_dma_len(sg), dir, 346 attrs); 347 } 348 EXPORT_SYMBOL(dma_direct_unmap_sg); 349 #endif 350 351 dma_addr_t dma_direct_map_page(struct device *dev, struct page *page, 352 unsigned long offset, size_t size, enum dma_data_direction dir, 353 unsigned long attrs) 354 { 355 phys_addr_t phys = page_to_phys(page) + offset; 356 dma_addr_t dma_addr = phys_to_dma(dev, phys); 357 358 if (unlikely(swiotlb_force == SWIOTLB_FORCE)) 359 return swiotlb_map(dev, phys, size, dir, attrs); 360 361 if (unlikely(!dma_capable(dev, dma_addr, size, true))) { 362 if (swiotlb_force != SWIOTLB_NO_FORCE) 363 return swiotlb_map(dev, phys, size, dir, attrs); 364 365 dev_WARN_ONCE(dev, 1, 366 "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n", 367 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit); 368 return DMA_MAPPING_ERROR; 369 } 370 371 if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) 372 arch_sync_dma_for_device(phys, size, dir); 373 return dma_addr; 374 } 375 EXPORT_SYMBOL(dma_direct_map_page); 376 377 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents, 378 enum dma_data_direction dir, unsigned long attrs) 379 { 380 int i; 381 struct scatterlist *sg; 382 383 for_each_sg(sgl, sg, nents, i) { 384 sg->dma_address = dma_direct_map_page(dev, sg_page(sg), 385 sg->offset, sg->length, dir, attrs); 386 if (sg->dma_address == DMA_MAPPING_ERROR) 387 goto out_unmap; 388 sg_dma_len(sg) = sg->length; 389 } 390 391 return nents; 392 393 out_unmap: 394 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC); 395 return 0; 396 } 397 EXPORT_SYMBOL(dma_direct_map_sg); 398 399 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr, 400 size_t size, enum dma_data_direction dir, unsigned long attrs) 401 { 402 dma_addr_t dma_addr = paddr; 403 404 if (unlikely(!dma_capable(dev, dma_addr, size, false))) { 405 dev_err_once(dev, 406 "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n", 407 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit); 408 WARN_ON_ONCE(1); 409 return DMA_MAPPING_ERROR; 410 } 411 412 return dma_addr; 413 } 414 EXPORT_SYMBOL(dma_direct_map_resource); 415 416 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt, 417 void *cpu_addr, dma_addr_t dma_addr, size_t size, 418 unsigned long attrs) 419 { 420 struct page *page = dma_direct_to_page(dev, dma_addr); 421 int ret; 422 423 ret = sg_alloc_table(sgt, 1, GFP_KERNEL); 424 if (!ret) 425 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); 426 return ret; 427 } 428 429 #ifdef CONFIG_MMU 430 bool dma_direct_can_mmap(struct device *dev) 431 { 432 return dev_is_dma_coherent(dev) || 433 IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP); 434 } 435 436 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma, 437 void *cpu_addr, dma_addr_t dma_addr, size_t size, 438 unsigned long attrs) 439 { 440 unsigned long user_count = vma_pages(vma); 441 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT; 442 unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr)); 443 int ret = -ENXIO; 444 445 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs); 446 447 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) 448 return ret; 449 450 if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff) 451 return -ENXIO; 452 return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff, 453 user_count << PAGE_SHIFT, vma->vm_page_prot); 454 } 455 #else /* CONFIG_MMU */ 456 bool dma_direct_can_mmap(struct device *dev) 457 { 458 return false; 459 } 460 461 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma, 462 void *cpu_addr, dma_addr_t dma_addr, size_t size, 463 unsigned long attrs) 464 { 465 return -ENXIO; 466 } 467 #endif /* CONFIG_MMU */ 468 469 int dma_direct_supported(struct device *dev, u64 mask) 470 { 471 u64 min_mask = (max_pfn - 1) << PAGE_SHIFT; 472 473 /* 474 * Because 32-bit DMA masks are so common we expect every architecture 475 * to be able to satisfy them - either by not supporting more physical 476 * memory, or by providing a ZONE_DMA32. If neither is the case, the 477 * architecture needs to use an IOMMU instead of the direct mapping. 478 */ 479 if (mask >= DMA_BIT_MASK(32)) 480 return 1; 481 482 /* 483 * This check needs to be against the actual bit mask value, so 484 * use __phys_to_dma() here so that the SME encryption mask isn't 485 * part of the check. 486 */ 487 if (IS_ENABLED(CONFIG_ZONE_DMA)) 488 min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits)); 489 return mask >= __phys_to_dma(dev, min_mask); 490 } 491 492 size_t dma_direct_max_mapping_size(struct device *dev) 493 { 494 /* If SWIOTLB is active, use its maximum mapping size */ 495 if (is_swiotlb_active() && 496 (dma_addressing_limited(dev) || swiotlb_force == SWIOTLB_FORCE)) 497 return swiotlb_max_mapping_size(dev); 498 return SIZE_MAX; 499 } 500