1 /****************************************************************************** 2 * xen.h 3 * 4 * Guest OS interface to Xen. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Copyright (c) 2004, K A Fraser 25 */ 26 27 #ifndef __XEN_PUBLIC_XEN_H__ 28 #define __XEN_PUBLIC_XEN_H__ 29 30 #include <asm/xen/interface.h> 31 32 /* 33 * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS). 34 */ 35 36 /* 37 * x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5. 38 * EAX = return value 39 * (argument registers may be clobbered on return) 40 * x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6. 41 * RAX = return value 42 * (argument registers not clobbered on return; RCX, R11 are) 43 */ 44 #define __HYPERVISOR_set_trap_table 0 45 #define __HYPERVISOR_mmu_update 1 46 #define __HYPERVISOR_set_gdt 2 47 #define __HYPERVISOR_stack_switch 3 48 #define __HYPERVISOR_set_callbacks 4 49 #define __HYPERVISOR_fpu_taskswitch 5 50 #define __HYPERVISOR_sched_op_compat 6 51 #define __HYPERVISOR_platform_op 7 52 #define __HYPERVISOR_set_debugreg 8 53 #define __HYPERVISOR_get_debugreg 9 54 #define __HYPERVISOR_update_descriptor 10 55 #define __HYPERVISOR_memory_op 12 56 #define __HYPERVISOR_multicall 13 57 #define __HYPERVISOR_update_va_mapping 14 58 #define __HYPERVISOR_set_timer_op 15 59 #define __HYPERVISOR_event_channel_op_compat 16 60 #define __HYPERVISOR_xen_version 17 61 #define __HYPERVISOR_console_io 18 62 #define __HYPERVISOR_physdev_op_compat 19 63 #define __HYPERVISOR_grant_table_op 20 64 #define __HYPERVISOR_vm_assist 21 65 #define __HYPERVISOR_update_va_mapping_otherdomain 22 66 #define __HYPERVISOR_iret 23 /* x86 only */ 67 #define __HYPERVISOR_vcpu_op 24 68 #define __HYPERVISOR_set_segment_base 25 /* x86/64 only */ 69 #define __HYPERVISOR_mmuext_op 26 70 #define __HYPERVISOR_xsm_op 27 71 #define __HYPERVISOR_nmi_op 28 72 #define __HYPERVISOR_sched_op 29 73 #define __HYPERVISOR_callback_op 30 74 #define __HYPERVISOR_xenoprof_op 31 75 #define __HYPERVISOR_event_channel_op 32 76 #define __HYPERVISOR_physdev_op 33 77 #define __HYPERVISOR_hvm_op 34 78 #define __HYPERVISOR_sysctl 35 79 #define __HYPERVISOR_domctl 36 80 #define __HYPERVISOR_kexec_op 37 81 #define __HYPERVISOR_tmem_op 38 82 #define __HYPERVISOR_xc_reserved_op 39 /* reserved for XenClient */ 83 #define __HYPERVISOR_xenpmu_op 40 84 #define __HYPERVISOR_dm_op 41 85 86 /* Architecture-specific hypercall definitions. */ 87 #define __HYPERVISOR_arch_0 48 88 #define __HYPERVISOR_arch_1 49 89 #define __HYPERVISOR_arch_2 50 90 #define __HYPERVISOR_arch_3 51 91 #define __HYPERVISOR_arch_4 52 92 #define __HYPERVISOR_arch_5 53 93 #define __HYPERVISOR_arch_6 54 94 #define __HYPERVISOR_arch_7 55 95 96 /* 97 * VIRTUAL INTERRUPTS 98 * 99 * Virtual interrupts that a guest OS may receive from Xen. 100 * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a 101 * global VIRQ. The former can be bound once per VCPU and cannot be re-bound. 102 * The latter can be allocated only once per guest: they must initially be 103 * allocated to VCPU0 but can subsequently be re-bound. 104 */ 105 #define VIRQ_TIMER 0 /* V. Timebase update, and/or requested timeout. */ 106 #define VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */ 107 #define VIRQ_CONSOLE 2 /* G. (DOM0) Bytes received on emergency console. */ 108 #define VIRQ_DOM_EXC 3 /* G. (DOM0) Exceptional event for some domain. */ 109 #define VIRQ_TBUF 4 /* G. (DOM0) Trace buffer has records available. */ 110 #define VIRQ_DEBUGGER 6 /* G. (DOM0) A domain has paused for debugging. */ 111 #define VIRQ_XENOPROF 7 /* V. XenOprofile interrupt: new sample available */ 112 #define VIRQ_CON_RING 8 /* G. (DOM0) Bytes received on console */ 113 #define VIRQ_PCPU_STATE 9 /* G. (DOM0) PCPU state changed */ 114 #define VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occured */ 115 #define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient */ 116 #define VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */ 117 #define VIRQ_XENPMU 13 /* PMC interrupt */ 118 119 /* Architecture-specific VIRQ definitions. */ 120 #define VIRQ_ARCH_0 16 121 #define VIRQ_ARCH_1 17 122 #define VIRQ_ARCH_2 18 123 #define VIRQ_ARCH_3 19 124 #define VIRQ_ARCH_4 20 125 #define VIRQ_ARCH_5 21 126 #define VIRQ_ARCH_6 22 127 #define VIRQ_ARCH_7 23 128 129 #define NR_VIRQS 24 130 131 /* 132 * enum neg_errnoval HYPERVISOR_mmu_update(const struct mmu_update reqs[], 133 * unsigned count, unsigned *done_out, 134 * unsigned foreigndom) 135 * @reqs is an array of mmu_update_t structures ((ptr, val) pairs). 136 * @count is the length of the above array. 137 * @pdone is an output parameter indicating number of completed operations 138 * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this 139 * hypercall invocation. Can be DOMID_SELF. 140 * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced 141 * in this hypercall invocation. The value of this field 142 * (x) encodes the PFD as follows: 143 * x == 0 => PFD == DOMID_SELF 144 * x != 0 => PFD == x - 1 145 * 146 * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command. 147 * ------------- 148 * ptr[1:0] == MMU_NORMAL_PT_UPDATE: 149 * Updates an entry in a page table belonging to PFD. If updating an L1 table, 150 * and the new table entry is valid/present, the mapped frame must belong to 151 * FD. If attempting to map an I/O page then the caller assumes the privilege 152 * of the FD. 153 * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller. 154 * FD == DOMID_XEN: Map restricted areas of Xen's heap space. 155 * ptr[:2] -- Machine address of the page-table entry to modify. 156 * val -- Value to write. 157 * 158 * There also certain implicit requirements when using this hypercall. The 159 * pages that make up a pagetable must be mapped read-only in the guest. 160 * This prevents uncontrolled guest updates to the pagetable. Xen strictly 161 * enforces this, and will disallow any pagetable update which will end up 162 * mapping pagetable page RW, and will disallow using any writable page as a 163 * pagetable. In practice it means that when constructing a page table for a 164 * process, thread, etc, we MUST be very dilligient in following these rules: 165 * 1). Start with top-level page (PGD or in Xen language: L4). Fill out 166 * the entries. 167 * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD 168 * or L2). 169 * 3). Start filling out the PTE table (L1) with the PTE entries. Once 170 * done, make sure to set each of those entries to RO (so writeable bit 171 * is unset). Once that has been completed, set the PMD (L2) for this 172 * PTE table as RO. 173 * 4). When completed with all of the PMD (L2) entries, and all of them have 174 * been set to RO, make sure to set RO the PUD (L3). Do the same 175 * operation on PGD (L4) pagetable entries that have a PUD (L3) entry. 176 * 5). Now before you can use those pages (so setting the cr3), you MUST also 177 * pin them so that the hypervisor can verify the entries. This is done 178 * via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame 179 * number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op( 180 * MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be 181 * issued. 182 * For 32-bit guests, the L4 is not used (as there is less pagetables), so 183 * instead use L3. 184 * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE 185 * hypercall. Also if so desired the OS can also try to write to the PTE 186 * and be trapped by the hypervisor (as the PTE entry is RO). 187 * 188 * To deallocate the pages, the operations are the reverse of the steps 189 * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the 190 * pagetable MUST not be in use (meaning that the cr3 is not set to it). 191 * 192 * ptr[1:0] == MMU_MACHPHYS_UPDATE: 193 * Updates an entry in the machine->pseudo-physical mapping table. 194 * ptr[:2] -- Machine address within the frame whose mapping to modify. 195 * The frame must belong to the FD, if one is specified. 196 * val -- Value to write into the mapping entry. 197 * 198 * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD: 199 * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed 200 * with those in @val. 201 * 202 * @val is usually the machine frame number along with some attributes. 203 * The attributes by default follow the architecture defined bits. Meaning that 204 * if this is a X86_64 machine and four page table layout is used, the layout 205 * of val is: 206 * - 63 if set means No execute (NX) 207 * - 46-13 the machine frame number 208 * - 12 available for guest 209 * - 11 available for guest 210 * - 10 available for guest 211 * - 9 available for guest 212 * - 8 global 213 * - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages) 214 * - 6 dirty 215 * - 5 accessed 216 * - 4 page cached disabled 217 * - 3 page write through 218 * - 2 userspace accessible 219 * - 1 writeable 220 * - 0 present 221 * 222 * The one bits that does not fit with the default layout is the PAGE_PSE 223 * also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the 224 * HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB 225 * (or 2MB) instead of using the PAGE_PSE bit. 226 * 227 * The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen 228 * using it as the Page Attribute Table (PAT) bit - for details on it please 229 * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of 230 * pages instead of using MTRRs. 231 * 232 * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits): 233 * PAT4 PAT0 234 * +-----+-----+----+----+----+-----+----+----+ 235 * | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux 236 * +-----+-----+----+----+----+-----+----+----+ 237 * | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) 238 * +-----+-----+----+----+----+-----+----+----+ 239 * | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen 240 * +-----+-----+----+----+----+-----+----+----+ 241 * 242 * The lookup of this index table translates to looking up 243 * Bit 7, Bit 4, and Bit 3 of val entry: 244 * 245 * PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3). 246 * 247 * If all bits are off, then we are using PAT0. If bit 3 turned on, 248 * then we are using PAT1, if bit 3 and bit 4, then PAT2.. 249 * 250 * As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means 251 * that if a guest that follows Linux's PAT setup and would like to set Write 252 * Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is 253 * set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the 254 * caching as: 255 * 256 * WB = none (so PAT0) 257 * WC = PWT (bit 3 on) 258 * UC = PWT | PCD (bit 3 and 4 are on). 259 * 260 * To make it work with Xen, it needs to translate the WC bit as so: 261 * 262 * PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3 263 * 264 * And to translate back it would: 265 * 266 * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7. 267 */ 268 #define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ 269 #define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ 270 #define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */ 271 272 /* 273 * MMU EXTENDED OPERATIONS 274 * 275 * enum neg_errnoval HYPERVISOR_mmuext_op(mmuext_op_t uops[], 276 * unsigned int count, 277 * unsigned int *pdone, 278 * unsigned int foreigndom) 279 */ 280 /* HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures. 281 * A foreigndom (FD) can be specified (or DOMID_SELF for none). 282 * Where the FD has some effect, it is described below. 283 * 284 * cmd: MMUEXT_(UN)PIN_*_TABLE 285 * mfn: Machine frame number to be (un)pinned as a p.t. page. 286 * The frame must belong to the FD, if one is specified. 287 * 288 * cmd: MMUEXT_NEW_BASEPTR 289 * mfn: Machine frame number of new page-table base to install in MMU. 290 * 291 * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only] 292 * mfn: Machine frame number of new page-table base to install in MMU 293 * when in user space. 294 * 295 * cmd: MMUEXT_TLB_FLUSH_LOCAL 296 * No additional arguments. Flushes local TLB. 297 * 298 * cmd: MMUEXT_INVLPG_LOCAL 299 * linear_addr: Linear address to be flushed from the local TLB. 300 * 301 * cmd: MMUEXT_TLB_FLUSH_MULTI 302 * vcpumask: Pointer to bitmap of VCPUs to be flushed. 303 * 304 * cmd: MMUEXT_INVLPG_MULTI 305 * linear_addr: Linear address to be flushed. 306 * vcpumask: Pointer to bitmap of VCPUs to be flushed. 307 * 308 * cmd: MMUEXT_TLB_FLUSH_ALL 309 * No additional arguments. Flushes all VCPUs' TLBs. 310 * 311 * cmd: MMUEXT_INVLPG_ALL 312 * linear_addr: Linear address to be flushed from all VCPUs' TLBs. 313 * 314 * cmd: MMUEXT_FLUSH_CACHE 315 * No additional arguments. Writes back and flushes cache contents. 316 * 317 * cmd: MMUEXT_FLUSH_CACHE_GLOBAL 318 * No additional arguments. Writes back and flushes cache contents 319 * on all CPUs in the system. 320 * 321 * cmd: MMUEXT_SET_LDT 322 * linear_addr: Linear address of LDT base (NB. must be page-aligned). 323 * nr_ents: Number of entries in LDT. 324 * 325 * cmd: MMUEXT_CLEAR_PAGE 326 * mfn: Machine frame number to be cleared. 327 * 328 * cmd: MMUEXT_COPY_PAGE 329 * mfn: Machine frame number of the destination page. 330 * src_mfn: Machine frame number of the source page. 331 * 332 * cmd: MMUEXT_[UN]MARK_SUPER 333 * mfn: Machine frame number of head of superpage to be [un]marked. 334 */ 335 #define MMUEXT_PIN_L1_TABLE 0 336 #define MMUEXT_PIN_L2_TABLE 1 337 #define MMUEXT_PIN_L3_TABLE 2 338 #define MMUEXT_PIN_L4_TABLE 3 339 #define MMUEXT_UNPIN_TABLE 4 340 #define MMUEXT_NEW_BASEPTR 5 341 #define MMUEXT_TLB_FLUSH_LOCAL 6 342 #define MMUEXT_INVLPG_LOCAL 7 343 #define MMUEXT_TLB_FLUSH_MULTI 8 344 #define MMUEXT_INVLPG_MULTI 9 345 #define MMUEXT_TLB_FLUSH_ALL 10 346 #define MMUEXT_INVLPG_ALL 11 347 #define MMUEXT_FLUSH_CACHE 12 348 #define MMUEXT_SET_LDT 13 349 #define MMUEXT_NEW_USER_BASEPTR 15 350 #define MMUEXT_CLEAR_PAGE 16 351 #define MMUEXT_COPY_PAGE 17 352 #define MMUEXT_FLUSH_CACHE_GLOBAL 18 353 #define MMUEXT_MARK_SUPER 19 354 #define MMUEXT_UNMARK_SUPER 20 355 356 #ifndef __ASSEMBLY__ 357 struct mmuext_op { 358 unsigned int cmd; 359 union { 360 /* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR 361 * CLEAR_PAGE, COPY_PAGE, [UN]MARK_SUPER */ 362 xen_pfn_t mfn; 363 /* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */ 364 unsigned long linear_addr; 365 } arg1; 366 union { 367 /* SET_LDT */ 368 unsigned int nr_ents; 369 /* TLB_FLUSH_MULTI, INVLPG_MULTI */ 370 void *vcpumask; 371 /* COPY_PAGE */ 372 xen_pfn_t src_mfn; 373 } arg2; 374 }; 375 DEFINE_GUEST_HANDLE_STRUCT(mmuext_op); 376 #endif 377 378 /* These are passed as 'flags' to update_va_mapping. They can be ORed. */ 379 /* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap. */ 380 /* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer. */ 381 #define UVMF_NONE (0UL<<0) /* No flushing at all. */ 382 #define UVMF_TLB_FLUSH (1UL<<0) /* Flush entire TLB(s). */ 383 #define UVMF_INVLPG (2UL<<0) /* Flush only one entry. */ 384 #define UVMF_FLUSHTYPE_MASK (3UL<<0) 385 #define UVMF_MULTI (0UL<<2) /* Flush subset of TLBs. */ 386 #define UVMF_LOCAL (0UL<<2) /* Flush local TLB. */ 387 #define UVMF_ALL (1UL<<2) /* Flush all TLBs. */ 388 389 /* 390 * Commands to HYPERVISOR_console_io(). 391 */ 392 #define CONSOLEIO_write 0 393 #define CONSOLEIO_read 1 394 395 /* 396 * Commands to HYPERVISOR_vm_assist(). 397 */ 398 #define VMASST_CMD_enable 0 399 #define VMASST_CMD_disable 1 400 401 /* x86/32 guests: simulate full 4GB segment limits. */ 402 #define VMASST_TYPE_4gb_segments 0 403 404 /* x86/32 guests: trap (vector 15) whenever above vmassist is used. */ 405 #define VMASST_TYPE_4gb_segments_notify 1 406 407 /* 408 * x86 guests: support writes to bottom-level PTEs. 409 * NB1. Page-directory entries cannot be written. 410 * NB2. Guest must continue to remove all writable mappings of PTEs. 411 */ 412 #define VMASST_TYPE_writable_pagetables 2 413 414 /* x86/PAE guests: support PDPTs above 4GB. */ 415 #define VMASST_TYPE_pae_extended_cr3 3 416 417 /* 418 * x86 guests: Sane behaviour for virtual iopl 419 * - virtual iopl updated from do_iret() hypercalls. 420 * - virtual iopl reported in bounce frames. 421 * - guest kernels assumed to be level 0 for the purpose of iopl checks. 422 */ 423 #define VMASST_TYPE_architectural_iopl 4 424 425 /* 426 * All guests: activate update indicator in vcpu_runstate_info 427 * Enable setting the XEN_RUNSTATE_UPDATE flag in guest memory mapped 428 * vcpu_runstate_info during updates of the runstate information. 429 */ 430 #define VMASST_TYPE_runstate_update_flag 5 431 432 #define MAX_VMASST_TYPE 5 433 434 #ifndef __ASSEMBLY__ 435 436 typedef uint16_t domid_t; 437 438 /* Domain ids >= DOMID_FIRST_RESERVED cannot be used for ordinary domains. */ 439 #define DOMID_FIRST_RESERVED (0x7FF0U) 440 441 /* DOMID_SELF is used in certain contexts to refer to oneself. */ 442 #define DOMID_SELF (0x7FF0U) 443 444 /* 445 * DOMID_IO is used to restrict page-table updates to mapping I/O memory. 446 * Although no Foreign Domain need be specified to map I/O pages, DOMID_IO 447 * is useful to ensure that no mappings to the OS's own heap are accidentally 448 * installed. (e.g., in Linux this could cause havoc as reference counts 449 * aren't adjusted on the I/O-mapping code path). 450 * This only makes sense in MMUEXT_SET_FOREIGNDOM, but in that context can 451 * be specified by any calling domain. 452 */ 453 #define DOMID_IO (0x7FF1U) 454 455 /* 456 * DOMID_XEN is used to allow privileged domains to map restricted parts of 457 * Xen's heap space (e.g., the machine_to_phys table). 458 * This only makes sense in MMUEXT_SET_FOREIGNDOM, and is only permitted if 459 * the caller is privileged. 460 */ 461 #define DOMID_XEN (0x7FF2U) 462 463 /* DOMID_COW is used as the owner of sharable pages */ 464 #define DOMID_COW (0x7FF3U) 465 466 /* DOMID_INVALID is used to identify pages with unknown owner. */ 467 #define DOMID_INVALID (0x7FF4U) 468 469 /* Idle domain. */ 470 #define DOMID_IDLE (0x7FFFU) 471 472 /* 473 * Send an array of these to HYPERVISOR_mmu_update(). 474 * NB. The fields are natural pointer/address size for this architecture. 475 */ 476 struct mmu_update { 477 uint64_t ptr; /* Machine address of PTE. */ 478 uint64_t val; /* New contents of PTE. */ 479 }; 480 DEFINE_GUEST_HANDLE_STRUCT(mmu_update); 481 482 /* 483 * Send an array of these to HYPERVISOR_multicall(). 484 * NB. The fields are logically the natural register size for this 485 * architecture. In cases where xen_ulong_t is larger than this then 486 * any unused bits in the upper portion must be zero. 487 */ 488 struct multicall_entry { 489 xen_ulong_t op; 490 xen_long_t result; 491 xen_ulong_t args[6]; 492 }; 493 DEFINE_GUEST_HANDLE_STRUCT(multicall_entry); 494 495 struct vcpu_time_info { 496 /* 497 * Updates to the following values are preceded and followed 498 * by an increment of 'version'. The guest can therefore 499 * detect updates by looking for changes to 'version'. If the 500 * least-significant bit of the version number is set then an 501 * update is in progress and the guest must wait to read a 502 * consistent set of values. The correct way to interact with 503 * the version number is similar to Linux's seqlock: see the 504 * implementations of read_seqbegin/read_seqretry. 505 */ 506 uint32_t version; 507 uint32_t pad0; 508 uint64_t tsc_timestamp; /* TSC at last update of time vals. */ 509 uint64_t system_time; /* Time, in nanosecs, since boot. */ 510 /* 511 * Current system time: 512 * system_time + ((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul 513 * CPU frequency (Hz): 514 * ((10^9 << 32) / tsc_to_system_mul) >> tsc_shift 515 */ 516 uint32_t tsc_to_system_mul; 517 int8_t tsc_shift; 518 int8_t pad1[3]; 519 }; /* 32 bytes */ 520 521 struct vcpu_info { 522 /* 523 * 'evtchn_upcall_pending' is written non-zero by Xen to indicate 524 * a pending notification for a particular VCPU. It is then cleared 525 * by the guest OS /before/ checking for pending work, thus avoiding 526 * a set-and-check race. Note that the mask is only accessed by Xen 527 * on the CPU that is currently hosting the VCPU. This means that the 528 * pending and mask flags can be updated by the guest without special 529 * synchronisation (i.e., no need for the x86 LOCK prefix). 530 * This may seem suboptimal because if the pending flag is set by 531 * a different CPU then an IPI may be scheduled even when the mask 532 * is set. However, note: 533 * 1. The task of 'interrupt holdoff' is covered by the per-event- 534 * channel mask bits. A 'noisy' event that is continually being 535 * triggered can be masked at source at this very precise 536 * granularity. 537 * 2. The main purpose of the per-VCPU mask is therefore to restrict 538 * reentrant execution: whether for concurrency control, or to 539 * prevent unbounded stack usage. Whatever the purpose, we expect 540 * that the mask will be asserted only for short periods at a time, 541 * and so the likelihood of a 'spurious' IPI is suitably small. 542 * The mask is read before making an event upcall to the guest: a 543 * non-zero mask therefore guarantees that the VCPU will not receive 544 * an upcall activation. The mask is cleared when the VCPU requests 545 * to block: this avoids wakeup-waiting races. 546 */ 547 uint8_t evtchn_upcall_pending; 548 uint8_t evtchn_upcall_mask; 549 xen_ulong_t evtchn_pending_sel; 550 struct arch_vcpu_info arch; 551 struct pvclock_vcpu_time_info time; 552 }; /* 64 bytes (x86) */ 553 554 /* 555 * Xen/kernel shared data -- pointer provided in start_info. 556 * NB. We expect that this struct is smaller than a page. 557 */ 558 struct shared_info { 559 struct vcpu_info vcpu_info[MAX_VIRT_CPUS]; 560 561 /* 562 * A domain can create "event channels" on which it can send and receive 563 * asynchronous event notifications. There are three classes of event that 564 * are delivered by this mechanism: 565 * 1. Bi-directional inter- and intra-domain connections. Domains must 566 * arrange out-of-band to set up a connection (usually by allocating 567 * an unbound 'listener' port and avertising that via a storage service 568 * such as xenstore). 569 * 2. Physical interrupts. A domain with suitable hardware-access 570 * privileges can bind an event-channel port to a physical interrupt 571 * source. 572 * 3. Virtual interrupts ('events'). A domain can bind an event-channel 573 * port to a virtual interrupt source, such as the virtual-timer 574 * device or the emergency console. 575 * 576 * Event channels are addressed by a "port index". Each channel is 577 * associated with two bits of information: 578 * 1. PENDING -- notifies the domain that there is a pending notification 579 * to be processed. This bit is cleared by the guest. 580 * 2. MASK -- if this bit is clear then a 0->1 transition of PENDING 581 * will cause an asynchronous upcall to be scheduled. This bit is only 582 * updated by the guest. It is read-only within Xen. If a channel 583 * becomes pending while the channel is masked then the 'edge' is lost 584 * (i.e., when the channel is unmasked, the guest must manually handle 585 * pending notifications as no upcall will be scheduled by Xen). 586 * 587 * To expedite scanning of pending notifications, any 0->1 pending 588 * transition on an unmasked channel causes a corresponding bit in a 589 * per-vcpu selector word to be set. Each bit in the selector covers a 590 * 'C long' in the PENDING bitfield array. 591 */ 592 xen_ulong_t evtchn_pending[sizeof(xen_ulong_t) * 8]; 593 xen_ulong_t evtchn_mask[sizeof(xen_ulong_t) * 8]; 594 595 /* 596 * Wallclock time: updated only by control software. Guests should base 597 * their gettimeofday() syscall on this wallclock-base value. 598 */ 599 struct pvclock_wall_clock wc; 600 601 struct arch_shared_info arch; 602 603 }; 604 605 /* 606 * Start-of-day memory layout 607 * 608 * 1. The domain is started within contiguous virtual-memory region. 609 * 2. The contiguous region begins and ends on an aligned 4MB boundary. 610 * 3. This the order of bootstrap elements in the initial virtual region: 611 * a. relocated kernel image 612 * b. initial ram disk [mod_start, mod_len] 613 * (may be omitted) 614 * c. list of allocated page frames [mfn_list, nr_pages] 615 * (unless relocated due to XEN_ELFNOTE_INIT_P2M) 616 * d. start_info_t structure [register ESI (x86)] 617 * in case of dom0 this page contains the console info, too 618 * e. unless dom0: xenstore ring page 619 * f. unless dom0: console ring page 620 * g. bootstrap page tables [pt_base, CR3 (x86)] 621 * h. bootstrap stack [register ESP (x86)] 622 * 4. Bootstrap elements are packed together, but each is 4kB-aligned. 623 * 5. The list of page frames forms a contiguous 'pseudo-physical' memory 624 * layout for the domain. In particular, the bootstrap virtual-memory 625 * region is a 1:1 mapping to the first section of the pseudo-physical map. 626 * 6. All bootstrap elements are mapped read-writable for the guest OS. The 627 * only exception is the bootstrap page table, which is mapped read-only. 628 * 7. There is guaranteed to be at least 512kB padding after the final 629 * bootstrap element. If necessary, the bootstrap virtual region is 630 * extended by an extra 4MB to ensure this. 631 */ 632 633 #define MAX_GUEST_CMDLINE 1024 634 struct start_info { 635 /* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME. */ 636 char magic[32]; /* "xen-<version>-<platform>". */ 637 unsigned long nr_pages; /* Total pages allocated to this domain. */ 638 unsigned long shared_info; /* MACHINE address of shared info struct. */ 639 uint32_t flags; /* SIF_xxx flags. */ 640 xen_pfn_t store_mfn; /* MACHINE page number of shared page. */ 641 uint32_t store_evtchn; /* Event channel for store communication. */ 642 union { 643 struct { 644 xen_pfn_t mfn; /* MACHINE page number of console page. */ 645 uint32_t evtchn; /* Event channel for console page. */ 646 } domU; 647 struct { 648 uint32_t info_off; /* Offset of console_info struct. */ 649 uint32_t info_size; /* Size of console_info struct from start.*/ 650 } dom0; 651 } console; 652 /* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME). */ 653 unsigned long pt_base; /* VIRTUAL address of page directory. */ 654 unsigned long nr_pt_frames; /* Number of bootstrap p.t. frames. */ 655 unsigned long mfn_list; /* VIRTUAL address of page-frame list. */ 656 unsigned long mod_start; /* VIRTUAL address of pre-loaded module. */ 657 unsigned long mod_len; /* Size (bytes) of pre-loaded module. */ 658 int8_t cmd_line[MAX_GUEST_CMDLINE]; 659 /* The pfn range here covers both page table and p->m table frames. */ 660 unsigned long first_p2m_pfn;/* 1st pfn forming initial P->M table. */ 661 unsigned long nr_p2m_frames;/* # of pfns forming initial P->M table. */ 662 }; 663 664 /* These flags are passed in the 'flags' field of start_info_t. */ 665 #define SIF_PRIVILEGED (1<<0) /* Is the domain privileged? */ 666 #define SIF_INITDOMAIN (1<<1) /* Is this the initial control domain? */ 667 #define SIF_MULTIBOOT_MOD (1<<2) /* Is mod_start a multiboot module? */ 668 #define SIF_MOD_START_PFN (1<<3) /* Is mod_start a PFN? */ 669 #define SIF_VIRT_P2M_4TOOLS (1<<4) /* Do Xen tools understand a virt. mapped */ 670 /* P->M making the 3 level tree obsolete? */ 671 #define SIF_PM_MASK (0xFF<<8) /* reserve 1 byte for xen-pm options */ 672 673 /* 674 * A multiboot module is a package containing modules very similar to a 675 * multiboot module array. The only differences are: 676 * - the array of module descriptors is by convention simply at the beginning 677 * of the multiboot module, 678 * - addresses in the module descriptors are based on the beginning of the 679 * multiboot module, 680 * - the number of modules is determined by a termination descriptor that has 681 * mod_start == 0. 682 * 683 * This permits to both build it statically and reference it in a configuration 684 * file, and let the PV guest easily rebase the addresses to virtual addresses 685 * and at the same time count the number of modules. 686 */ 687 struct xen_multiboot_mod_list { 688 /* Address of first byte of the module */ 689 uint32_t mod_start; 690 /* Address of last byte of the module (inclusive) */ 691 uint32_t mod_end; 692 /* Address of zero-terminated command line */ 693 uint32_t cmdline; 694 /* Unused, must be zero */ 695 uint32_t pad; 696 }; 697 /* 698 * The console structure in start_info.console.dom0 699 * 700 * This structure includes a variety of information required to 701 * have a working VGA/VESA console. 702 */ 703 struct dom0_vga_console_info { 704 uint8_t video_type; 705 #define XEN_VGATYPE_TEXT_MODE_3 0x03 706 #define XEN_VGATYPE_VESA_LFB 0x23 707 #define XEN_VGATYPE_EFI_LFB 0x70 708 709 union { 710 struct { 711 /* Font height, in pixels. */ 712 uint16_t font_height; 713 /* Cursor location (column, row). */ 714 uint16_t cursor_x, cursor_y; 715 /* Number of rows and columns (dimensions in characters). */ 716 uint16_t rows, columns; 717 } text_mode_3; 718 719 struct { 720 /* Width and height, in pixels. */ 721 uint16_t width, height; 722 /* Bytes per scan line. */ 723 uint16_t bytes_per_line; 724 /* Bits per pixel. */ 725 uint16_t bits_per_pixel; 726 /* LFB physical address, and size (in units of 64kB). */ 727 uint32_t lfb_base; 728 uint32_t lfb_size; 729 /* RGB mask offsets and sizes, as defined by VBE 1.2+ */ 730 uint8_t red_pos, red_size; 731 uint8_t green_pos, green_size; 732 uint8_t blue_pos, blue_size; 733 uint8_t rsvd_pos, rsvd_size; 734 735 /* VESA capabilities (offset 0xa, VESA command 0x4f00). */ 736 uint32_t gbl_caps; 737 /* Mode attributes (offset 0x0, VESA command 0x4f01). */ 738 uint16_t mode_attrs; 739 } vesa_lfb; 740 } u; 741 }; 742 743 typedef uint64_t cpumap_t; 744 745 typedef uint8_t xen_domain_handle_t[16]; 746 747 /* Turn a plain number into a C unsigned long constant. */ 748 #define __mk_unsigned_long(x) x ## UL 749 #define mk_unsigned_long(x) __mk_unsigned_long(x) 750 751 #define TMEM_SPEC_VERSION 1 752 753 struct tmem_op { 754 uint32_t cmd; 755 int32_t pool_id; 756 union { 757 struct { /* for cmd == TMEM_NEW_POOL */ 758 uint64_t uuid[2]; 759 uint32_t flags; 760 } new; 761 struct { 762 uint64_t oid[3]; 763 uint32_t index; 764 uint32_t tmem_offset; 765 uint32_t pfn_offset; 766 uint32_t len; 767 GUEST_HANDLE(void) gmfn; /* guest machine page frame */ 768 } gen; 769 } u; 770 }; 771 772 DEFINE_GUEST_HANDLE(u64); 773 774 #else /* __ASSEMBLY__ */ 775 776 /* In assembly code we cannot use C numeric constant suffixes. */ 777 #define mk_unsigned_long(x) x 778 779 #endif /* !__ASSEMBLY__ */ 780 781 #endif /* __XEN_PUBLIC_XEN_H__ */ 782