1 /****************************************************************************** 2 * xen.h 3 * 4 * Guest OS interface to Xen. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Copyright (c) 2004, K A Fraser 25 */ 26 27 #ifndef __XEN_PUBLIC_XEN_H__ 28 #define __XEN_PUBLIC_XEN_H__ 29 30 #include <asm/xen/interface.h> 31 32 /* 33 * XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS). 34 */ 35 36 /* 37 * x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5. 38 * EAX = return value 39 * (argument registers may be clobbered on return) 40 * x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6. 41 * RAX = return value 42 * (argument registers not clobbered on return; RCX, R11 are) 43 */ 44 #define __HYPERVISOR_set_trap_table 0 45 #define __HYPERVISOR_mmu_update 1 46 #define __HYPERVISOR_set_gdt 2 47 #define __HYPERVISOR_stack_switch 3 48 #define __HYPERVISOR_set_callbacks 4 49 #define __HYPERVISOR_fpu_taskswitch 5 50 #define __HYPERVISOR_sched_op_compat 6 51 #define __HYPERVISOR_dom0_op 7 52 #define __HYPERVISOR_set_debugreg 8 53 #define __HYPERVISOR_get_debugreg 9 54 #define __HYPERVISOR_update_descriptor 10 55 #define __HYPERVISOR_memory_op 12 56 #define __HYPERVISOR_multicall 13 57 #define __HYPERVISOR_update_va_mapping 14 58 #define __HYPERVISOR_set_timer_op 15 59 #define __HYPERVISOR_event_channel_op_compat 16 60 #define __HYPERVISOR_xen_version 17 61 #define __HYPERVISOR_console_io 18 62 #define __HYPERVISOR_physdev_op_compat 19 63 #define __HYPERVISOR_grant_table_op 20 64 #define __HYPERVISOR_vm_assist 21 65 #define __HYPERVISOR_update_va_mapping_otherdomain 22 66 #define __HYPERVISOR_iret 23 /* x86 only */ 67 #define __HYPERVISOR_vcpu_op 24 68 #define __HYPERVISOR_set_segment_base 25 /* x86/64 only */ 69 #define __HYPERVISOR_mmuext_op 26 70 #define __HYPERVISOR_xsm_op 27 71 #define __HYPERVISOR_nmi_op 28 72 #define __HYPERVISOR_sched_op 29 73 #define __HYPERVISOR_callback_op 30 74 #define __HYPERVISOR_xenoprof_op 31 75 #define __HYPERVISOR_event_channel_op 32 76 #define __HYPERVISOR_physdev_op 33 77 #define __HYPERVISOR_hvm_op 34 78 #define __HYPERVISOR_sysctl 35 79 #define __HYPERVISOR_domctl 36 80 #define __HYPERVISOR_kexec_op 37 81 #define __HYPERVISOR_tmem_op 38 82 #define __HYPERVISOR_xc_reserved_op 39 /* reserved for XenClient */ 83 84 /* Architecture-specific hypercall definitions. */ 85 #define __HYPERVISOR_arch_0 48 86 #define __HYPERVISOR_arch_1 49 87 #define __HYPERVISOR_arch_2 50 88 #define __HYPERVISOR_arch_3 51 89 #define __HYPERVISOR_arch_4 52 90 #define __HYPERVISOR_arch_5 53 91 #define __HYPERVISOR_arch_6 54 92 #define __HYPERVISOR_arch_7 55 93 94 /* 95 * VIRTUAL INTERRUPTS 96 * 97 * Virtual interrupts that a guest OS may receive from Xen. 98 * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a 99 * global VIRQ. The former can be bound once per VCPU and cannot be re-bound. 100 * The latter can be allocated only once per guest: they must initially be 101 * allocated to VCPU0 but can subsequently be re-bound. 102 */ 103 #define VIRQ_TIMER 0 /* V. Timebase update, and/or requested timeout. */ 104 #define VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */ 105 #define VIRQ_CONSOLE 2 /* G. (DOM0) Bytes received on emergency console. */ 106 #define VIRQ_DOM_EXC 3 /* G. (DOM0) Exceptional event for some domain. */ 107 #define VIRQ_TBUF 4 /* G. (DOM0) Trace buffer has records available. */ 108 #define VIRQ_DEBUGGER 6 /* G. (DOM0) A domain has paused for debugging. */ 109 #define VIRQ_XENOPROF 7 /* V. XenOprofile interrupt: new sample available */ 110 #define VIRQ_CON_RING 8 /* G. (DOM0) Bytes received on console */ 111 #define VIRQ_PCPU_STATE 9 /* G. (DOM0) PCPU state changed */ 112 #define VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occured */ 113 #define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient */ 114 #define VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */ 115 116 /* Architecture-specific VIRQ definitions. */ 117 #define VIRQ_ARCH_0 16 118 #define VIRQ_ARCH_1 17 119 #define VIRQ_ARCH_2 18 120 #define VIRQ_ARCH_3 19 121 #define VIRQ_ARCH_4 20 122 #define VIRQ_ARCH_5 21 123 #define VIRQ_ARCH_6 22 124 #define VIRQ_ARCH_7 23 125 126 #define NR_VIRQS 24 127 128 /* 129 * enum neg_errnoval HYPERVISOR_mmu_update(const struct mmu_update reqs[], 130 * unsigned count, unsigned *done_out, 131 * unsigned foreigndom) 132 * @reqs is an array of mmu_update_t structures ((ptr, val) pairs). 133 * @count is the length of the above array. 134 * @pdone is an output parameter indicating number of completed operations 135 * @foreigndom[15:0]: FD, the expected owner of data pages referenced in this 136 * hypercall invocation. Can be DOMID_SELF. 137 * @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced 138 * in this hypercall invocation. The value of this field 139 * (x) encodes the PFD as follows: 140 * x == 0 => PFD == DOMID_SELF 141 * x != 0 => PFD == x - 1 142 * 143 * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command. 144 * ------------- 145 * ptr[1:0] == MMU_NORMAL_PT_UPDATE: 146 * Updates an entry in a page table belonging to PFD. If updating an L1 table, 147 * and the new table entry is valid/present, the mapped frame must belong to 148 * FD. If attempting to map an I/O page then the caller assumes the privilege 149 * of the FD. 150 * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller. 151 * FD == DOMID_XEN: Map restricted areas of Xen's heap space. 152 * ptr[:2] -- Machine address of the page-table entry to modify. 153 * val -- Value to write. 154 * 155 * There also certain implicit requirements when using this hypercall. The 156 * pages that make up a pagetable must be mapped read-only in the guest. 157 * This prevents uncontrolled guest updates to the pagetable. Xen strictly 158 * enforces this, and will disallow any pagetable update which will end up 159 * mapping pagetable page RW, and will disallow using any writable page as a 160 * pagetable. In practice it means that when constructing a page table for a 161 * process, thread, etc, we MUST be very dilligient in following these rules: 162 * 1). Start with top-level page (PGD or in Xen language: L4). Fill out 163 * the entries. 164 * 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD 165 * or L2). 166 * 3). Start filling out the PTE table (L1) with the PTE entries. Once 167 * done, make sure to set each of those entries to RO (so writeable bit 168 * is unset). Once that has been completed, set the PMD (L2) for this 169 * PTE table as RO. 170 * 4). When completed with all of the PMD (L2) entries, and all of them have 171 * been set to RO, make sure to set RO the PUD (L3). Do the same 172 * operation on PGD (L4) pagetable entries that have a PUD (L3) entry. 173 * 5). Now before you can use those pages (so setting the cr3), you MUST also 174 * pin them so that the hypervisor can verify the entries. This is done 175 * via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame 176 * number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op( 177 * MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be 178 * issued. 179 * For 32-bit guests, the L4 is not used (as there is less pagetables), so 180 * instead use L3. 181 * At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE 182 * hypercall. Also if so desired the OS can also try to write to the PTE 183 * and be trapped by the hypervisor (as the PTE entry is RO). 184 * 185 * To deallocate the pages, the operations are the reverse of the steps 186 * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the 187 * pagetable MUST not be in use (meaning that the cr3 is not set to it). 188 * 189 * ptr[1:0] == MMU_MACHPHYS_UPDATE: 190 * Updates an entry in the machine->pseudo-physical mapping table. 191 * ptr[:2] -- Machine address within the frame whose mapping to modify. 192 * The frame must belong to the FD, if one is specified. 193 * val -- Value to write into the mapping entry. 194 * 195 * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD: 196 * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed 197 * with those in @val. 198 * 199 * @val is usually the machine frame number along with some attributes. 200 * The attributes by default follow the architecture defined bits. Meaning that 201 * if this is a X86_64 machine and four page table layout is used, the layout 202 * of val is: 203 * - 63 if set means No execute (NX) 204 * - 46-13 the machine frame number 205 * - 12 available for guest 206 * - 11 available for guest 207 * - 10 available for guest 208 * - 9 available for guest 209 * - 8 global 210 * - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages) 211 * - 6 dirty 212 * - 5 accessed 213 * - 4 page cached disabled 214 * - 3 page write through 215 * - 2 userspace accessible 216 * - 1 writeable 217 * - 0 present 218 * 219 * The one bits that does not fit with the default layout is the PAGE_PSE 220 * also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the 221 * HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB 222 * (or 2MB) instead of using the PAGE_PSE bit. 223 * 224 * The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen 225 * using it as the Page Attribute Table (PAT) bit - for details on it please 226 * refer to Intel SDM 10.12. The PAT allows to set the caching attributes of 227 * pages instead of using MTRRs. 228 * 229 * The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits): 230 * PAT4 PAT0 231 * +-----+-----+----+----+----+-----+----+----+ 232 * | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux 233 * +-----+-----+----+----+----+-----+----+----+ 234 * | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots) 235 * +-----+-----+----+----+----+-----+----+----+ 236 * | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen 237 * +-----+-----+----+----+----+-----+----+----+ 238 * 239 * The lookup of this index table translates to looking up 240 * Bit 7, Bit 4, and Bit 3 of val entry: 241 * 242 * PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3). 243 * 244 * If all bits are off, then we are using PAT0. If bit 3 turned on, 245 * then we are using PAT1, if bit 3 and bit 4, then PAT2.. 246 * 247 * As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means 248 * that if a guest that follows Linux's PAT setup and would like to set Write 249 * Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is 250 * set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the 251 * caching as: 252 * 253 * WB = none (so PAT0) 254 * WC = PWT (bit 3 on) 255 * UC = PWT | PCD (bit 3 and 4 are on). 256 * 257 * To make it work with Xen, it needs to translate the WC bit as so: 258 * 259 * PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3 260 * 261 * And to translate back it would: 262 * 263 * PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7. 264 */ 265 #define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ 266 #define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ 267 #define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */ 268 269 /* 270 * MMU EXTENDED OPERATIONS 271 * 272 * enum neg_errnoval HYPERVISOR_mmuext_op(mmuext_op_t uops[], 273 * unsigned int count, 274 * unsigned int *pdone, 275 * unsigned int foreigndom) 276 */ 277 /* HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures. 278 * A foreigndom (FD) can be specified (or DOMID_SELF for none). 279 * Where the FD has some effect, it is described below. 280 * 281 * cmd: MMUEXT_(UN)PIN_*_TABLE 282 * mfn: Machine frame number to be (un)pinned as a p.t. page. 283 * The frame must belong to the FD, if one is specified. 284 * 285 * cmd: MMUEXT_NEW_BASEPTR 286 * mfn: Machine frame number of new page-table base to install in MMU. 287 * 288 * cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only] 289 * mfn: Machine frame number of new page-table base to install in MMU 290 * when in user space. 291 * 292 * cmd: MMUEXT_TLB_FLUSH_LOCAL 293 * No additional arguments. Flushes local TLB. 294 * 295 * cmd: MMUEXT_INVLPG_LOCAL 296 * linear_addr: Linear address to be flushed from the local TLB. 297 * 298 * cmd: MMUEXT_TLB_FLUSH_MULTI 299 * vcpumask: Pointer to bitmap of VCPUs to be flushed. 300 * 301 * cmd: MMUEXT_INVLPG_MULTI 302 * linear_addr: Linear address to be flushed. 303 * vcpumask: Pointer to bitmap of VCPUs to be flushed. 304 * 305 * cmd: MMUEXT_TLB_FLUSH_ALL 306 * No additional arguments. Flushes all VCPUs' TLBs. 307 * 308 * cmd: MMUEXT_INVLPG_ALL 309 * linear_addr: Linear address to be flushed from all VCPUs' TLBs. 310 * 311 * cmd: MMUEXT_FLUSH_CACHE 312 * No additional arguments. Writes back and flushes cache contents. 313 * 314 * cmd: MMUEXT_FLUSH_CACHE_GLOBAL 315 * No additional arguments. Writes back and flushes cache contents 316 * on all CPUs in the system. 317 * 318 * cmd: MMUEXT_SET_LDT 319 * linear_addr: Linear address of LDT base (NB. must be page-aligned). 320 * nr_ents: Number of entries in LDT. 321 * 322 * cmd: MMUEXT_CLEAR_PAGE 323 * mfn: Machine frame number to be cleared. 324 * 325 * cmd: MMUEXT_COPY_PAGE 326 * mfn: Machine frame number of the destination page. 327 * src_mfn: Machine frame number of the source page. 328 * 329 * cmd: MMUEXT_[UN]MARK_SUPER 330 * mfn: Machine frame number of head of superpage to be [un]marked. 331 */ 332 #define MMUEXT_PIN_L1_TABLE 0 333 #define MMUEXT_PIN_L2_TABLE 1 334 #define MMUEXT_PIN_L3_TABLE 2 335 #define MMUEXT_PIN_L4_TABLE 3 336 #define MMUEXT_UNPIN_TABLE 4 337 #define MMUEXT_NEW_BASEPTR 5 338 #define MMUEXT_TLB_FLUSH_LOCAL 6 339 #define MMUEXT_INVLPG_LOCAL 7 340 #define MMUEXT_TLB_FLUSH_MULTI 8 341 #define MMUEXT_INVLPG_MULTI 9 342 #define MMUEXT_TLB_FLUSH_ALL 10 343 #define MMUEXT_INVLPG_ALL 11 344 #define MMUEXT_FLUSH_CACHE 12 345 #define MMUEXT_SET_LDT 13 346 #define MMUEXT_NEW_USER_BASEPTR 15 347 #define MMUEXT_CLEAR_PAGE 16 348 #define MMUEXT_COPY_PAGE 17 349 #define MMUEXT_FLUSH_CACHE_GLOBAL 18 350 #define MMUEXT_MARK_SUPER 19 351 #define MMUEXT_UNMARK_SUPER 20 352 353 #ifndef __ASSEMBLY__ 354 struct mmuext_op { 355 unsigned int cmd; 356 union { 357 /* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR 358 * CLEAR_PAGE, COPY_PAGE, [UN]MARK_SUPER */ 359 xen_pfn_t mfn; 360 /* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */ 361 unsigned long linear_addr; 362 } arg1; 363 union { 364 /* SET_LDT */ 365 unsigned int nr_ents; 366 /* TLB_FLUSH_MULTI, INVLPG_MULTI */ 367 void *vcpumask; 368 /* COPY_PAGE */ 369 xen_pfn_t src_mfn; 370 } arg2; 371 }; 372 DEFINE_GUEST_HANDLE_STRUCT(mmuext_op); 373 #endif 374 375 /* These are passed as 'flags' to update_va_mapping. They can be ORed. */ 376 /* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap. */ 377 /* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer. */ 378 #define UVMF_NONE (0UL<<0) /* No flushing at all. */ 379 #define UVMF_TLB_FLUSH (1UL<<0) /* Flush entire TLB(s). */ 380 #define UVMF_INVLPG (2UL<<0) /* Flush only one entry. */ 381 #define UVMF_FLUSHTYPE_MASK (3UL<<0) 382 #define UVMF_MULTI (0UL<<2) /* Flush subset of TLBs. */ 383 #define UVMF_LOCAL (0UL<<2) /* Flush local TLB. */ 384 #define UVMF_ALL (1UL<<2) /* Flush all TLBs. */ 385 386 /* 387 * Commands to HYPERVISOR_console_io(). 388 */ 389 #define CONSOLEIO_write 0 390 #define CONSOLEIO_read 1 391 392 /* 393 * Commands to HYPERVISOR_vm_assist(). 394 */ 395 #define VMASST_CMD_enable 0 396 #define VMASST_CMD_disable 1 397 398 /* x86/32 guests: simulate full 4GB segment limits. */ 399 #define VMASST_TYPE_4gb_segments 0 400 401 /* x86/32 guests: trap (vector 15) whenever above vmassist is used. */ 402 #define VMASST_TYPE_4gb_segments_notify 1 403 404 /* 405 * x86 guests: support writes to bottom-level PTEs. 406 * NB1. Page-directory entries cannot be written. 407 * NB2. Guest must continue to remove all writable mappings of PTEs. 408 */ 409 #define VMASST_TYPE_writable_pagetables 2 410 411 /* x86/PAE guests: support PDPTs above 4GB. */ 412 #define VMASST_TYPE_pae_extended_cr3 3 413 414 #define MAX_VMASST_TYPE 3 415 416 #ifndef __ASSEMBLY__ 417 418 typedef uint16_t domid_t; 419 420 /* Domain ids >= DOMID_FIRST_RESERVED cannot be used for ordinary domains. */ 421 #define DOMID_FIRST_RESERVED (0x7FF0U) 422 423 /* DOMID_SELF is used in certain contexts to refer to oneself. */ 424 #define DOMID_SELF (0x7FF0U) 425 426 /* 427 * DOMID_IO is used to restrict page-table updates to mapping I/O memory. 428 * Although no Foreign Domain need be specified to map I/O pages, DOMID_IO 429 * is useful to ensure that no mappings to the OS's own heap are accidentally 430 * installed. (e.g., in Linux this could cause havoc as reference counts 431 * aren't adjusted on the I/O-mapping code path). 432 * This only makes sense in MMUEXT_SET_FOREIGNDOM, but in that context can 433 * be specified by any calling domain. 434 */ 435 #define DOMID_IO (0x7FF1U) 436 437 /* 438 * DOMID_XEN is used to allow privileged domains to map restricted parts of 439 * Xen's heap space (e.g., the machine_to_phys table). 440 * This only makes sense in MMUEXT_SET_FOREIGNDOM, and is only permitted if 441 * the caller is privileged. 442 */ 443 #define DOMID_XEN (0x7FF2U) 444 445 /* DOMID_COW is used as the owner of sharable pages */ 446 #define DOMID_COW (0x7FF3U) 447 448 /* DOMID_INVALID is used to identify pages with unknown owner. */ 449 #define DOMID_INVALID (0x7FF4U) 450 451 /* Idle domain. */ 452 #define DOMID_IDLE (0x7FFFU) 453 454 /* 455 * Send an array of these to HYPERVISOR_mmu_update(). 456 * NB. The fields are natural pointer/address size for this architecture. 457 */ 458 struct mmu_update { 459 uint64_t ptr; /* Machine address of PTE. */ 460 uint64_t val; /* New contents of PTE. */ 461 }; 462 DEFINE_GUEST_HANDLE_STRUCT(mmu_update); 463 464 /* 465 * Send an array of these to HYPERVISOR_multicall(). 466 * NB. The fields are logically the natural register size for this 467 * architecture. In cases where xen_ulong_t is larger than this then 468 * any unused bits in the upper portion must be zero. 469 */ 470 struct multicall_entry { 471 xen_ulong_t op; 472 xen_long_t result; 473 xen_ulong_t args[6]; 474 }; 475 DEFINE_GUEST_HANDLE_STRUCT(multicall_entry); 476 477 struct vcpu_time_info { 478 /* 479 * Updates to the following values are preceded and followed 480 * by an increment of 'version'. The guest can therefore 481 * detect updates by looking for changes to 'version'. If the 482 * least-significant bit of the version number is set then an 483 * update is in progress and the guest must wait to read a 484 * consistent set of values. The correct way to interact with 485 * the version number is similar to Linux's seqlock: see the 486 * implementations of read_seqbegin/read_seqretry. 487 */ 488 uint32_t version; 489 uint32_t pad0; 490 uint64_t tsc_timestamp; /* TSC at last update of time vals. */ 491 uint64_t system_time; /* Time, in nanosecs, since boot. */ 492 /* 493 * Current system time: 494 * system_time + ((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul 495 * CPU frequency (Hz): 496 * ((10^9 << 32) / tsc_to_system_mul) >> tsc_shift 497 */ 498 uint32_t tsc_to_system_mul; 499 int8_t tsc_shift; 500 int8_t pad1[3]; 501 }; /* 32 bytes */ 502 503 struct vcpu_info { 504 /* 505 * 'evtchn_upcall_pending' is written non-zero by Xen to indicate 506 * a pending notification for a particular VCPU. It is then cleared 507 * by the guest OS /before/ checking for pending work, thus avoiding 508 * a set-and-check race. Note that the mask is only accessed by Xen 509 * on the CPU that is currently hosting the VCPU. This means that the 510 * pending and mask flags can be updated by the guest without special 511 * synchronisation (i.e., no need for the x86 LOCK prefix). 512 * This may seem suboptimal because if the pending flag is set by 513 * a different CPU then an IPI may be scheduled even when the mask 514 * is set. However, note: 515 * 1. The task of 'interrupt holdoff' is covered by the per-event- 516 * channel mask bits. A 'noisy' event that is continually being 517 * triggered can be masked at source at this very precise 518 * granularity. 519 * 2. The main purpose of the per-VCPU mask is therefore to restrict 520 * reentrant execution: whether for concurrency control, or to 521 * prevent unbounded stack usage. Whatever the purpose, we expect 522 * that the mask will be asserted only for short periods at a time, 523 * and so the likelihood of a 'spurious' IPI is suitably small. 524 * The mask is read before making an event upcall to the guest: a 525 * non-zero mask therefore guarantees that the VCPU will not receive 526 * an upcall activation. The mask is cleared when the VCPU requests 527 * to block: this avoids wakeup-waiting races. 528 */ 529 uint8_t evtchn_upcall_pending; 530 uint8_t evtchn_upcall_mask; 531 xen_ulong_t evtchn_pending_sel; 532 struct arch_vcpu_info arch; 533 struct pvclock_vcpu_time_info time; 534 }; /* 64 bytes (x86) */ 535 536 /* 537 * Xen/kernel shared data -- pointer provided in start_info. 538 * NB. We expect that this struct is smaller than a page. 539 */ 540 struct shared_info { 541 struct vcpu_info vcpu_info[MAX_VIRT_CPUS]; 542 543 /* 544 * A domain can create "event channels" on which it can send and receive 545 * asynchronous event notifications. There are three classes of event that 546 * are delivered by this mechanism: 547 * 1. Bi-directional inter- and intra-domain connections. Domains must 548 * arrange out-of-band to set up a connection (usually by allocating 549 * an unbound 'listener' port and avertising that via a storage service 550 * such as xenstore). 551 * 2. Physical interrupts. A domain with suitable hardware-access 552 * privileges can bind an event-channel port to a physical interrupt 553 * source. 554 * 3. Virtual interrupts ('events'). A domain can bind an event-channel 555 * port to a virtual interrupt source, such as the virtual-timer 556 * device or the emergency console. 557 * 558 * Event channels are addressed by a "port index". Each channel is 559 * associated with two bits of information: 560 * 1. PENDING -- notifies the domain that there is a pending notification 561 * to be processed. This bit is cleared by the guest. 562 * 2. MASK -- if this bit is clear then a 0->1 transition of PENDING 563 * will cause an asynchronous upcall to be scheduled. This bit is only 564 * updated by the guest. It is read-only within Xen. If a channel 565 * becomes pending while the channel is masked then the 'edge' is lost 566 * (i.e., when the channel is unmasked, the guest must manually handle 567 * pending notifications as no upcall will be scheduled by Xen). 568 * 569 * To expedite scanning of pending notifications, any 0->1 pending 570 * transition on an unmasked channel causes a corresponding bit in a 571 * per-vcpu selector word to be set. Each bit in the selector covers a 572 * 'C long' in the PENDING bitfield array. 573 */ 574 xen_ulong_t evtchn_pending[sizeof(xen_ulong_t) * 8]; 575 xen_ulong_t evtchn_mask[sizeof(xen_ulong_t) * 8]; 576 577 /* 578 * Wallclock time: updated only by control software. Guests should base 579 * their gettimeofday() syscall on this wallclock-base value. 580 */ 581 struct pvclock_wall_clock wc; 582 583 struct arch_shared_info arch; 584 585 }; 586 587 /* 588 * Start-of-day memory layout for the initial domain (DOM0): 589 * 1. The domain is started within contiguous virtual-memory region. 590 * 2. The contiguous region begins and ends on an aligned 4MB boundary. 591 * 3. The region start corresponds to the load address of the OS image. 592 * If the load address is not 4MB aligned then the address is rounded down. 593 * 4. This the order of bootstrap elements in the initial virtual region: 594 * a. relocated kernel image 595 * b. initial ram disk [mod_start, mod_len] 596 * c. list of allocated page frames [mfn_list, nr_pages] 597 * d. start_info_t structure [register ESI (x86)] 598 * e. bootstrap page tables [pt_base, CR3 (x86)] 599 * f. bootstrap stack [register ESP (x86)] 600 * 5. Bootstrap elements are packed together, but each is 4kB-aligned. 601 * 6. The initial ram disk may be omitted. 602 * 7. The list of page frames forms a contiguous 'pseudo-physical' memory 603 * layout for the domain. In particular, the bootstrap virtual-memory 604 * region is a 1:1 mapping to the first section of the pseudo-physical map. 605 * 8. All bootstrap elements are mapped read-writable for the guest OS. The 606 * only exception is the bootstrap page table, which is mapped read-only. 607 * 9. There is guaranteed to be at least 512kB padding after the final 608 * bootstrap element. If necessary, the bootstrap virtual region is 609 * extended by an extra 4MB to ensure this. 610 */ 611 612 #define MAX_GUEST_CMDLINE 1024 613 struct start_info { 614 /* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME. */ 615 char magic[32]; /* "xen-<version>-<platform>". */ 616 unsigned long nr_pages; /* Total pages allocated to this domain. */ 617 unsigned long shared_info; /* MACHINE address of shared info struct. */ 618 uint32_t flags; /* SIF_xxx flags. */ 619 xen_pfn_t store_mfn; /* MACHINE page number of shared page. */ 620 uint32_t store_evtchn; /* Event channel for store communication. */ 621 union { 622 struct { 623 xen_pfn_t mfn; /* MACHINE page number of console page. */ 624 uint32_t evtchn; /* Event channel for console page. */ 625 } domU; 626 struct { 627 uint32_t info_off; /* Offset of console_info struct. */ 628 uint32_t info_size; /* Size of console_info struct from start.*/ 629 } dom0; 630 } console; 631 /* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME). */ 632 unsigned long pt_base; /* VIRTUAL address of page directory. */ 633 unsigned long nr_pt_frames; /* Number of bootstrap p.t. frames. */ 634 unsigned long mfn_list; /* VIRTUAL address of page-frame list. */ 635 unsigned long mod_start; /* VIRTUAL address of pre-loaded module. */ 636 unsigned long mod_len; /* Size (bytes) of pre-loaded module. */ 637 int8_t cmd_line[MAX_GUEST_CMDLINE]; 638 /* The pfn range here covers both page table and p->m table frames. */ 639 unsigned long first_p2m_pfn;/* 1st pfn forming initial P->M table. */ 640 unsigned long nr_p2m_frames;/* # of pfns forming initial P->M table. */ 641 }; 642 643 /* These flags are passed in the 'flags' field of start_info_t. */ 644 #define SIF_PRIVILEGED (1<<0) /* Is the domain privileged? */ 645 #define SIF_INITDOMAIN (1<<1) /* Is this the initial control domain? */ 646 #define SIF_MULTIBOOT_MOD (1<<2) /* Is mod_start a multiboot module? */ 647 #define SIF_MOD_START_PFN (1<<3) /* Is mod_start a PFN? */ 648 #define SIF_PM_MASK (0xFF<<8) /* reserve 1 byte for xen-pm options */ 649 650 /* 651 * A multiboot module is a package containing modules very similar to a 652 * multiboot module array. The only differences are: 653 * - the array of module descriptors is by convention simply at the beginning 654 * of the multiboot module, 655 * - addresses in the module descriptors are based on the beginning of the 656 * multiboot module, 657 * - the number of modules is determined by a termination descriptor that has 658 * mod_start == 0. 659 * 660 * This permits to both build it statically and reference it in a configuration 661 * file, and let the PV guest easily rebase the addresses to virtual addresses 662 * and at the same time count the number of modules. 663 */ 664 struct xen_multiboot_mod_list { 665 /* Address of first byte of the module */ 666 uint32_t mod_start; 667 /* Address of last byte of the module (inclusive) */ 668 uint32_t mod_end; 669 /* Address of zero-terminated command line */ 670 uint32_t cmdline; 671 /* Unused, must be zero */ 672 uint32_t pad; 673 }; 674 /* 675 * The console structure in start_info.console.dom0 676 * 677 * This structure includes a variety of information required to 678 * have a working VGA/VESA console. 679 */ 680 struct dom0_vga_console_info { 681 uint8_t video_type; 682 #define XEN_VGATYPE_TEXT_MODE_3 0x03 683 #define XEN_VGATYPE_VESA_LFB 0x23 684 #define XEN_VGATYPE_EFI_LFB 0x70 685 686 union { 687 struct { 688 /* Font height, in pixels. */ 689 uint16_t font_height; 690 /* Cursor location (column, row). */ 691 uint16_t cursor_x, cursor_y; 692 /* Number of rows and columns (dimensions in characters). */ 693 uint16_t rows, columns; 694 } text_mode_3; 695 696 struct { 697 /* Width and height, in pixels. */ 698 uint16_t width, height; 699 /* Bytes per scan line. */ 700 uint16_t bytes_per_line; 701 /* Bits per pixel. */ 702 uint16_t bits_per_pixel; 703 /* LFB physical address, and size (in units of 64kB). */ 704 uint32_t lfb_base; 705 uint32_t lfb_size; 706 /* RGB mask offsets and sizes, as defined by VBE 1.2+ */ 707 uint8_t red_pos, red_size; 708 uint8_t green_pos, green_size; 709 uint8_t blue_pos, blue_size; 710 uint8_t rsvd_pos, rsvd_size; 711 712 /* VESA capabilities (offset 0xa, VESA command 0x4f00). */ 713 uint32_t gbl_caps; 714 /* Mode attributes (offset 0x0, VESA command 0x4f01). */ 715 uint16_t mode_attrs; 716 } vesa_lfb; 717 } u; 718 }; 719 720 typedef uint64_t cpumap_t; 721 722 typedef uint8_t xen_domain_handle_t[16]; 723 724 /* Turn a plain number into a C unsigned long constant. */ 725 #define __mk_unsigned_long(x) x ## UL 726 #define mk_unsigned_long(x) __mk_unsigned_long(x) 727 728 #define TMEM_SPEC_VERSION 1 729 730 struct tmem_op { 731 uint32_t cmd; 732 int32_t pool_id; 733 union { 734 struct { /* for cmd == TMEM_NEW_POOL */ 735 uint64_t uuid[2]; 736 uint32_t flags; 737 } new; 738 struct { 739 uint64_t oid[3]; 740 uint32_t index; 741 uint32_t tmem_offset; 742 uint32_t pfn_offset; 743 uint32_t len; 744 GUEST_HANDLE(void) gmfn; /* guest machine page frame */ 745 } gen; 746 } u; 747 }; 748 749 DEFINE_GUEST_HANDLE(u64); 750 751 #else /* __ASSEMBLY__ */ 752 753 /* In assembly code we cannot use C numeric constant suffixes. */ 754 #define mk_unsigned_long(x) x 755 756 #endif /* !__ASSEMBLY__ */ 757 758 #endif /* __XEN_PUBLIC_XEN_H__ */ 759