1*9e2b3e83SJuergen Gross /* SPDX-License-Identifier: MIT */ 218f19aa6SJeremy Fitzhardinge 318f19aa6SJeremy Fitzhardinge #ifndef __XEN_PUBLIC_HVM_PARAMS_H__ 418f19aa6SJeremy Fitzhardinge #define __XEN_PUBLIC_HVM_PARAMS_H__ 518f19aa6SJeremy Fitzhardinge 6a1ce3928SDavid Howells #include <xen/interface/hvm/hvm_op.h> 718f19aa6SJeremy Fitzhardinge 818f19aa6SJeremy Fitzhardinge /* 918f19aa6SJeremy Fitzhardinge * Parameter space for HVMOP_{set,get}_param. 1018f19aa6SJeremy Fitzhardinge */ 1118f19aa6SJeremy Fitzhardinge 12b6f0bcc2SShannon Zhao #define HVM_PARAM_CALLBACK_IRQ 0 1318f19aa6SJeremy Fitzhardinge /* 1418f19aa6SJeremy Fitzhardinge * How should CPU0 event-channel notifications be delivered? 15b6f0bcc2SShannon Zhao * 1618f19aa6SJeremy Fitzhardinge * If val == 0 then CPU0 event-channel notifications are not delivered. 17b6f0bcc2SShannon Zhao * If val != 0, val[63:56] encodes the type, as follows: 1818f19aa6SJeremy Fitzhardinge */ 19b6f0bcc2SShannon Zhao 20b6f0bcc2SShannon Zhao #define HVM_PARAM_CALLBACK_TYPE_GSI 0 21b6f0bcc2SShannon Zhao /* 22b6f0bcc2SShannon Zhao * val[55:0] is a delivery GSI. GSI 0 cannot be used, as it aliases val == 0, 23b6f0bcc2SShannon Zhao * and disables all notifications. 24b6f0bcc2SShannon Zhao */ 25b6f0bcc2SShannon Zhao 26b6f0bcc2SShannon Zhao #define HVM_PARAM_CALLBACK_TYPE_PCI_INTX 1 27b6f0bcc2SShannon Zhao /* 28b6f0bcc2SShannon Zhao * val[55:0] is a delivery PCI INTx line: 29b6f0bcc2SShannon Zhao * Domain = val[47:32], Bus = val[31:16] DevFn = val[15:8], IntX = val[1:0] 30b6f0bcc2SShannon Zhao */ 31b6f0bcc2SShannon Zhao 32383ff518SShannon Zhao #if defined(__i386__) || defined(__x86_64__) 33b6f0bcc2SShannon Zhao #define HVM_PARAM_CALLBACK_TYPE_VECTOR 2 34b6f0bcc2SShannon Zhao /* 35b6f0bcc2SShannon Zhao * val[7:0] is a vector number. Check for XENFEAT_hvm_callback_vector to know 36b6f0bcc2SShannon Zhao * if this delivery method is available. 37b6f0bcc2SShannon Zhao */ 38383ff518SShannon Zhao #elif defined(__arm__) || defined(__aarch64__) 39383ff518SShannon Zhao #define HVM_PARAM_CALLBACK_TYPE_PPI 2 40383ff518SShannon Zhao /* 41383ff518SShannon Zhao * val[55:16] needs to be zero. 42383ff518SShannon Zhao * val[15:8] is interrupt flag of the PPI used by event-channel: 43383ff518SShannon Zhao * bit 8: the PPI is edge(1) or level(0) triggered 44383ff518SShannon Zhao * bit 9: the PPI is active low(1) or high(0) 45383ff518SShannon Zhao * val[7:0] is a PPI number used by event-channel. 46383ff518SShannon Zhao * This is only used by ARM/ARM64 and masking/eoi the interrupt associated to 47383ff518SShannon Zhao * the notification is handled by the interrupt controller. 48383ff518SShannon Zhao */ 49383ff518SShannon Zhao #endif 5018f19aa6SJeremy Fitzhardinge 5118f19aa6SJeremy Fitzhardinge #define HVM_PARAM_STORE_PFN 1 5218f19aa6SJeremy Fitzhardinge #define HVM_PARAM_STORE_EVTCHN 2 5318f19aa6SJeremy Fitzhardinge 5418f19aa6SJeremy Fitzhardinge #define HVM_PARAM_PAE_ENABLED 4 5518f19aa6SJeremy Fitzhardinge 5618f19aa6SJeremy Fitzhardinge #define HVM_PARAM_IOREQ_PFN 5 5718f19aa6SJeremy Fitzhardinge 5818f19aa6SJeremy Fitzhardinge #define HVM_PARAM_BUFIOREQ_PFN 6 5918f19aa6SJeremy Fitzhardinge 6018f19aa6SJeremy Fitzhardinge /* 6118f19aa6SJeremy Fitzhardinge * Set mode for virtual timers (currently x86 only): 6218f19aa6SJeremy Fitzhardinge * delay_for_missed_ticks (default): 6318f19aa6SJeremy Fitzhardinge * Do not advance a vcpu's time beyond the correct delivery time for 6418f19aa6SJeremy Fitzhardinge * interrupts that have been missed due to preemption. Deliver missed 6518f19aa6SJeremy Fitzhardinge * interrupts when the vcpu is rescheduled and advance the vcpu's virtual 6618f19aa6SJeremy Fitzhardinge * time stepwise for each one. 6718f19aa6SJeremy Fitzhardinge * no_delay_for_missed_ticks: 6818f19aa6SJeremy Fitzhardinge * As above, missed interrupts are delivered, but guest time always tracks 6918f19aa6SJeremy Fitzhardinge * wallclock (i.e., real) time while doing so. 7018f19aa6SJeremy Fitzhardinge * no_missed_ticks_pending: 7118f19aa6SJeremy Fitzhardinge * No missed interrupts are held pending. Instead, to ensure ticks are 7218f19aa6SJeremy Fitzhardinge * delivered at some non-zero rate, if we detect missed ticks then the 7318f19aa6SJeremy Fitzhardinge * internal tick alarm is not disabled if the VCPU is preempted during the 7418f19aa6SJeremy Fitzhardinge * next tick period. 7518f19aa6SJeremy Fitzhardinge * one_missed_tick_pending: 7618f19aa6SJeremy Fitzhardinge * Missed interrupts are collapsed together and delivered as one 'late tick'. 7718f19aa6SJeremy Fitzhardinge * Guest time always tracks wallclock (i.e., real) time. 7818f19aa6SJeremy Fitzhardinge */ 7918f19aa6SJeremy Fitzhardinge #define HVM_PARAM_TIMER_MODE 10 8018f19aa6SJeremy Fitzhardinge #define HVMPTM_delay_for_missed_ticks 0 8118f19aa6SJeremy Fitzhardinge #define HVMPTM_no_delay_for_missed_ticks 1 8218f19aa6SJeremy Fitzhardinge #define HVMPTM_no_missed_ticks_pending 2 8318f19aa6SJeremy Fitzhardinge #define HVMPTM_one_missed_tick_pending 3 8418f19aa6SJeremy Fitzhardinge 8518f19aa6SJeremy Fitzhardinge /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */ 8618f19aa6SJeremy Fitzhardinge #define HVM_PARAM_HPET_ENABLED 11 8718f19aa6SJeremy Fitzhardinge 8818f19aa6SJeremy Fitzhardinge /* Identity-map page directory used by Intel EPT when CR0.PG=0. */ 8918f19aa6SJeremy Fitzhardinge #define HVM_PARAM_IDENT_PT 12 9018f19aa6SJeremy Fitzhardinge 9118f19aa6SJeremy Fitzhardinge /* Device Model domain, defaults to 0. */ 9218f19aa6SJeremy Fitzhardinge #define HVM_PARAM_DM_DOMAIN 13 9318f19aa6SJeremy Fitzhardinge 9418f19aa6SJeremy Fitzhardinge /* ACPI S state: currently support S0 and S3 on x86. */ 9518f19aa6SJeremy Fitzhardinge #define HVM_PARAM_ACPI_S_STATE 14 9618f19aa6SJeremy Fitzhardinge 9718f19aa6SJeremy Fitzhardinge /* TSS used on Intel when CR0.PE=0. */ 9818f19aa6SJeremy Fitzhardinge #define HVM_PARAM_VM86_TSS 15 9918f19aa6SJeremy Fitzhardinge 10018f19aa6SJeremy Fitzhardinge /* Boolean: Enable aligning all periodic vpts to reduce interrupts */ 10118f19aa6SJeremy Fitzhardinge #define HVM_PARAM_VPT_ALIGN 16 10218f19aa6SJeremy Fitzhardinge 103eb5ef071SStefano Stabellini /* Console debug shared memory ring and event channel */ 104eb5ef071SStefano Stabellini #define HVM_PARAM_CONSOLE_PFN 17 105eb5ef071SStefano Stabellini #define HVM_PARAM_CONSOLE_EVTCHN 18 106eb5ef071SStefano Stabellini 107eb5ef071SStefano Stabellini #define HVM_NR_PARAMS 19 10818f19aa6SJeremy Fitzhardinge 10918f19aa6SJeremy Fitzhardinge #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */ 110