1 /* 2 * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer 3 * 4 * Copyright (c) 2000,2001 Ghozlane Toumi <gtoumi@messel.emse.fr> 5 * 6 * Created 28 Aug 2001 by Ghozlane Toumi 7 */ 8 9 10 #ifndef _SSTFB_H_ 11 #define _SSTFB_H_ 12 13 /* 14 * 15 * Debug Stuff 16 * 17 */ 18 19 #ifdef SST_DEBUG 20 # define dprintk(X...) printk("sstfb: " X) 21 # define SST_DEBUG_REG 1 22 # define SST_DEBUG_FUNC 1 23 # define SST_DEBUG_VAR 1 24 #else 25 # define dprintk(X...) 26 # define SST_DEBUG_REG 0 27 # define SST_DEBUG_FUNC 0 28 # define SST_DEBUG_VAR 0 29 #endif 30 31 #if (SST_DEBUG_REG > 0) 32 # define r_dprintk(X...) dprintk(X) 33 #else 34 # define r_dprintk(X...) 35 #endif 36 #if (SST_DEBUG_REG > 1) 37 # define r_ddprintk(X...) dprintk(" " X) 38 #else 39 # define r_ddprintk(X...) 40 #endif 41 42 #if (SST_DEBUG_FUNC > 0) 43 # define f_dprintk(X...) dprintk(X) 44 #else 45 # define f_dprintk(X...) 46 #endif 47 #if (SST_DEBUG_FUNC > 1) 48 # define f_ddprintk(X...) dprintk(" " X) 49 #else 50 # define f_ddprintk(X...) 51 #endif 52 #if (SST_DEBUG_FUNC > 2) 53 # define f_dddprintk(X...) dprintk(" " X) 54 #else 55 # define f_dddprintk(X...) 56 #endif 57 58 #if (SST_DEBUG_VAR > 0) 59 # define v_dprintk(X...) dprintk(X) 60 # define print_var(V, X...) \ 61 { \ 62 dprintk(X); \ 63 printk(" :\n"); \ 64 sst_dbg_print_var(V); \ 65 } 66 #else 67 # define v_dprintk(X...) 68 # define print_var(X,Y...) 69 #endif 70 71 #define POW2(x) (1ul<<(x)) 72 73 /* 74 * 75 * Const 76 * 77 */ 78 79 /* pci stuff */ 80 #define PCI_INIT_ENABLE 0x40 81 # define PCI_EN_INIT_WR BIT(0) 82 # define PCI_EN_FIFO_WR BIT(1) 83 # define PCI_REMAP_DAC BIT(2) 84 #define PCI_VCLK_ENABLE 0xc0 /* enable video */ 85 #define PCI_VCLK_DISABLE 0xe0 86 87 /* register offsets from memBaseAddr */ 88 #define STATUS 0x0000 89 # define STATUS_FBI_BUSY BIT(7) 90 #define FBZMODE 0x0110 91 # define EN_CLIPPING BIT(0) /* enable clipping */ 92 # define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */ 93 # define EN_ALPHA_WRITE BIT(10) 94 # define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */ 95 #define LFBMODE 0x0114 96 # define LFB_565 0 /* bits 3:0 .16 bits RGB */ 97 # define LFB_888 4 /* 24 bits RGB */ 98 # define LFB_8888 5 /* 32 bits ARGB */ 99 # define WR_BUFF_FRONT 0 /* write buf select (front) */ 100 # define WR_BUFF_BACK (1 << 4) /* back */ 101 # define RD_BUFF_FRONT 0 /* read buff select (front) */ 102 # define RD_BUFF_BACK (1 << 6) /* back */ 103 # define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/ 104 # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */ 105 # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */ 106 # define LFB_INVERT_Y BIT(13) /* invert Y origin (LFB) */ 107 # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */ 108 # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */ 109 #define CLIP_LEFT_RIGHT 0x0118 110 #define CLIP_LOWY_HIGHY 0x011c 111 #define NOPCMD 0x0120 112 #define FASTFILLCMD 0x0124 113 #define SWAPBUFFCMD 0x0128 114 #define FBIINIT4 0x0200 /* misc controls */ 115 # define FAST_PCI_READS 0 /* 1 waitstate */ 116 # define SLOW_PCI_READS BIT(0) /* 2 ws */ 117 # define LFB_READ_AHEAD BIT(1) 118 #define BACKPORCH 0x0208 119 #define VIDEODIMENSIONS 0x020c 120 #define FBIINIT0 0x0210 /* misc+fifo controls */ 121 # define DIS_VGA_PASSTHROUGH BIT(0) 122 # define FBI_RESET BIT(1) 123 # define FIFO_RESET BIT(2) 124 #define FBIINIT1 0x0214 /* PCI + video controls */ 125 # define VIDEO_MASK 0x8080010f /* masks video related bits V1+V2*/ 126 # define FAST_PCI_WRITES 0 /* 0 ws */ 127 # define SLOW_PCI_WRITES BIT(1) /* 1 ws */ 128 # define EN_LFB_READ BIT(3) 129 # define TILES_IN_X_SHIFT 4 130 # define VIDEO_RESET BIT(8) 131 # define EN_BLANKING BIT(12) 132 # define EN_DATA_OE BIT(13) 133 # define EN_BLANK_OE BIT(14) 134 # define EN_HVSYNC_OE BIT(15) 135 # define EN_DCLK_OE BIT(16) 136 # define SEL_INPUT_VCLK_2X 0 /* bit 17 */ 137 # define SEL_INPUT_VCLK_SLAVE BIT(17) 138 # define SEL_SOURCE_VCLK_SLAVE 0 /* bits 21:20 */ 139 # define SEL_SOURCE_VCLK_2X_DIV2 (0x01 << 20) 140 # define SEL_SOURCE_VCLK_2X_SEL (0x02 << 20) 141 # define EN_24BPP BIT(22) 142 # define TILES_IN_X_MSB_SHIFT 24 /* v2 */ 143 # define VCLK_2X_SEL_DEL_SHIFT 27 /* vclk out delay 0,4,6,8ns */ 144 # define VCLK_DEL_SHIFT 29 /* vclk in delay */ 145 #define FBIINIT2 0x0218 /* Dram controls */ 146 # define EN_FAST_RAS_READ BIT(5) 147 # define EN_DRAM_OE BIT(6) 148 # define EN_FAST_RD_AHEAD_WR BIT(7) 149 # define VIDEO_OFFSET_SHIFT 11 /* unit: #rows tile 64x16/2 */ 150 # define SWAP_DACVSYNC 0 151 # define SWAP_DACDATA0 (1 << 9) 152 # define SWAP_FIFO_STALL (2 << 9) 153 # define EN_RD_AHEAD_FIFO BIT(21) 154 # define EN_DRAM_REFRESH BIT(22) 155 # define DRAM_REFRESH_16 (0x30 << 23) /* dram 16 ms */ 156 #define DAC_READ FBIINIT2 /* in remap mode */ 157 #define FBIINIT3 0x021c /* fbi controls */ 158 # define DISABLE_TEXTURE BIT(6) 159 # define Y_SWAP_ORIGIN_SHIFT 22 /* Y swap subtraction value */ 160 #define HSYNC 0x0220 161 #define VSYNC 0x0224 162 #define DAC_DATA 0x022c 163 # define DAC_READ_CMD BIT(11) /* set read dacreg mode */ 164 #define FBIINIT5 0x0244 /* v2 specific */ 165 # define FBIINIT5_MASK 0xfa40ffff /* mask video bits*/ 166 # define HDOUBLESCAN BIT(20) 167 # define VDOUBLESCAN BIT(21) 168 # define HSYNC_HIGH BIT(23) 169 # define VSYNC_HIGH BIT(24) 170 # define INTERLACE BIT(26) 171 #define FBIINIT6 0x0248 /* v2 specific */ 172 # define TILES_IN_X_LSB_SHIFT 30 /* v2 */ 173 #define FBIINIT7 0x024c /* v2 specific */ 174 175 #define BLTSRCBASEADDR 0x02c0 /* BitBLT Source base address */ 176 #define BLTDSTBASEADDR 0x02c4 /* BitBLT Destination base address */ 177 #define BLTXYSTRIDES 0x02c8 /* BitBLT Source and Destination strides */ 178 #define BLTSRCCHROMARANGE 0x02cc /* BitBLT Source Chroma key range */ 179 #define BLTDSTCHROMARANGE 0x02d0 /* BitBLT Destination Chroma key range */ 180 #define BLTCLIPX 0x02d4 /* BitBLT Min/Max X clip values */ 181 #define BLTCLIPY 0x02d8 /* BitBLT Min/Max Y clip values */ 182 #define BLTSRCXY 0x02e0 /* BitBLT Source starting XY coordinates */ 183 #define BLTDSTXY 0x02e4 /* BitBLT Destination starting XY coordinates */ 184 #define BLTSIZE 0x02e8 /* BitBLT width and height */ 185 #define BLTROP 0x02ec /* BitBLT Raster operations */ 186 # define BLTROP_COPY 0x0cccc 187 # define BLTROP_INVERT 0x05555 188 # define BLTROP_XOR 0x06666 189 #define BLTCOLOR 0x02f0 /* BitBLT and foreground background colors */ 190 #define BLTCOMMAND 0x02f8 /* BitBLT command mode (v2 specific) */ 191 # define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */ 192 # define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */ 193 # define BLT_RECFILL_BITBLT 2 /* BitBLT Rectangle Fill */ 194 # define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */ 195 #define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */ 196 # define LAUNCH_BITBLT BIT(31) /* Launch BitBLT in BltCommand, bltDstXY or bltSize */ 197 198 /* Dac Registers */ 199 #define DACREG_WMA 0x0 /* pixel write mode address */ 200 #define DACREG_LUT 0x01 /* color value */ 201 #define DACREG_RMR 0x02 /* pixel mask */ 202 #define DACREG_RMA 0x03 /* pixel read mode address */ 203 /*Dac registers in indexed mode (TI, ATT dacs) */ 204 #define DACREG_ADDR_I DACREG_WMA 205 #define DACREG_DATA_I DACREG_RMR 206 #define DACREG_RMR_I 0x00 207 #define DACREG_CR0_I 0x01 208 # define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */ 209 # define DACREG_CR0_8BIT BIT(1) /* set dac to 8 bits/read */ 210 # define DACREG_CR0_PWDOWN BIT(3) /* powerdown dac */ 211 # define DACREG_CR0_16BPP 0x30 /* mode 3 */ 212 # define DACREG_CR0_24BPP 0x50 /* mode 5 */ 213 #define DACREG_CR1_I 0x05 214 #define DACREG_CC_I 0x06 215 # define DACREG_CC_CLKA BIT(7) /* clk A controlled by regs */ 216 # define DACREG_CC_CLKA_C (2<<4) /* clk A uses reg C */ 217 # define DACREG_CC_CLKB BIT(3) /* clk B controlled by regs */ 218 # define DACREG_CC_CLKB_D 3 /* clkB uses reg D */ 219 #define DACREG_AC0_I 0x48 /* clock A reg C */ 220 #define DACREG_AC1_I 0x49 221 #define DACREG_BD0_I 0x6c /* clock B reg D */ 222 #define DACREG_BD1_I 0x6d 223 224 /* identification constants */ 225 #define DACREG_MIR_TI 0x97 226 #define DACREG_DIR_TI 0x09 227 #define DACREG_MIR_ATT 0x84 228 #define DACREG_DIR_ATT 0x09 229 /* ics dac specific registers */ 230 #define DACREG_ICS_PLLWMA 0x04 /* PLL write mode address */ 231 #define DACREG_ICS_PLLDATA 0x05 /* PLL data /parameter */ 232 #define DACREG_ICS_CMD 0x06 /* command */ 233 # define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/ 234 # define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/ 235 # define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */ 236 #define DACREG_ICS_PLLRMA 0x07 /* PLL read mode address */ 237 /* 238 * pll parameter register: 239 * indexed : write addr to PLLWMA, write data in PLLDATA. 240 * for reads use PLLRMA . 241 * 8 freq registers (0-7) for video clock (CLK0) 242 * 2 freq registers (a-b) for graphic clock (CLK1) 243 */ 244 #define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */ 245 #define DACREG_ICS_PLL_CLK0_7_INI 0x71 /* f7 */ 246 #define DACREG_ICS_PLL_CLK1_B_INI 0x79 /* fb */ 247 #define DACREG_ICS_PLL_CTRL 0x0e 248 # define DACREG_ICS_CLK0 BIT(5) 249 # define DACREG_ICS_CLK0_0 0 250 # define DACREG_ICS_CLK1_A 0 /* bit4 */ 251 252 /* sst default init registers */ 253 #define FBIINIT0_DEFAULT DIS_VGA_PASSTHROUGH 254 255 #define FBIINIT1_DEFAULT \ 256 ( \ 257 FAST_PCI_WRITES \ 258 /* SLOW_PCI_WRITES*/ \ 259 | VIDEO_RESET \ 260 | 10 << TILES_IN_X_SHIFT\ 261 | SEL_SOURCE_VCLK_2X_SEL\ 262 | EN_LFB_READ \ 263 ) 264 265 #define FBIINIT2_DEFAULT \ 266 ( \ 267 SWAP_DACVSYNC \ 268 | EN_DRAM_OE \ 269 | DRAM_REFRESH_16 \ 270 | EN_DRAM_REFRESH \ 271 | EN_FAST_RAS_READ \ 272 | EN_RD_AHEAD_FIFO \ 273 | EN_FAST_RD_AHEAD_WR \ 274 ) 275 276 #define FBIINIT3_DEFAULT \ 277 ( DISABLE_TEXTURE ) 278 279 #define FBIINIT4_DEFAULT \ 280 ( \ 281 FAST_PCI_READS \ 282 /* SLOW_PCI_READS*/ \ 283 | LFB_READ_AHEAD \ 284 ) 285 /* Careful with this one : writing back the data just read will trash the DAC 286 reading some fields give logic value on pins, but setting this field will 287 set the source signal driving the pin. conclusion : just use the default 288 as a base before writing back . 289 */ 290 #define FBIINIT6_DEFAULT (0x0) 291 292 /* 293 * 294 * Misc Const 295 * 296 */ 297 298 /* ioctl to enable/disable VGA passthrough */ 299 #define SSTFB_SET_VGAPASS _IOW('F', 0xdd, __u32) 300 #define SSTFB_GET_VGAPASS _IOR('F', 0xdd, __u32) 301 302 303 /* used to know witch clock to set */ 304 enum { 305 VID_CLOCK=0, 306 GFX_CLOCK=1, 307 }; 308 309 /* freq max */ 310 #define DAC_FREF 14318 /* DAC reference freq (Khz) */ 311 #define VCO_MAX 260000 312 313 /* 314 * driver structs 315 */ 316 317 struct pll_timing { 318 unsigned int m; 319 unsigned int n; 320 unsigned int p; 321 }; 322 323 struct dac_switch { 324 const char *name; 325 int (*detect) (struct fb_info *info); 326 int (*set_pll) (struct fb_info *info, const struct pll_timing *t, const int clock); 327 void (*set_vidmod) (struct fb_info *info, const int bpp); 328 }; 329 330 struct sst_spec { 331 char * name; 332 int default_gfx_clock; /* 50000 for voodoo1, 75000 for voodoo2 */ 333 int max_gfxclk; /* ! in Mhz ie 60 for voodoo 1 */ 334 }; 335 336 struct sstfb_par { 337 u32 palette[16]; 338 unsigned int yDim; 339 unsigned int hSyncOn; /* hsync_len */ 340 unsigned int hSyncOff; /* left_margin + xres + right_margin */ 341 unsigned int hBackPorch;/* left_margin */ 342 unsigned int vSyncOn; 343 unsigned int vSyncOff; 344 unsigned int vBackPorch; 345 struct pll_timing pll; 346 unsigned int tiles_in_X;/* num of tiles in X res */ 347 u8 __iomem *mmio_vbase; 348 struct dac_switch dac_sw; /* dac specific functions */ 349 struct pci_dev *dev; 350 int type; 351 u8 revision; 352 u8 vgapass; /* VGA pass through: 1=enabled, 0=disabled */ 353 }; 354 355 #endif /* _SSTFB_H_ */ 356