1 /* $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $ 2 * linux/drivers/video/aty128.h 3 * Register definitions for ATI Rage128 boards 4 * 5 * Anthony Tong <atong@uiuc.edu>, 1999 6 * Brad Douglas <brad@neruo.com>, 2000 7 */ 8 9 #ifndef REG_RAGE128_H 10 #define REG_RAGE128_H 11 12 #define CLOCK_CNTL_INDEX 0x0008 13 #define CLOCK_CNTL_DATA 0x000c 14 #define BIOS_0_SCRATCH 0x0010 15 #define BUS_CNTL 0x0030 16 #define BUS_CNTL1 0x0034 17 #define GEN_INT_CNTL 0x0040 18 #define CRTC_GEN_CNTL 0x0050 19 #define CRTC_EXT_CNTL 0x0054 20 #define DAC_CNTL 0x0058 21 #define I2C_CNTL_1 0x0094 22 #define PALETTE_INDEX 0x00b0 23 #define PALETTE_DATA 0x00b4 24 #define CONFIG_CNTL 0x00e0 25 #define GEN_RESET_CNTL 0x00f0 26 #define CONFIG_MEMSIZE 0x00f8 27 #define MEM_CNTL 0x0140 28 #define MEM_POWER_MISC 0x015c 29 #define AGP_BASE 0x0170 30 #define AGP_CNTL 0x0174 31 #define AGP_APER_OFFSET 0x0178 32 #define PCI_GART_PAGE 0x017c 33 #define PC_NGUI_MODE 0x0180 34 #define PC_NGUI_CTLSTAT 0x0184 35 #define MPP_TB_CONFIG 0x01C0 36 #define MPP_GP_CONFIG 0x01C8 37 #define VIPH_CONTROL 0x01D0 38 #define CRTC_H_TOTAL_DISP 0x0200 39 #define CRTC_H_SYNC_STRT_WID 0x0204 40 #define CRTC_V_TOTAL_DISP 0x0208 41 #define CRTC_V_SYNC_STRT_WID 0x020c 42 #define CRTC_VLINE_CRNT_VLINE 0x0210 43 #define CRTC_CRNT_FRAME 0x0214 44 #define CRTC_GUI_TRIG_VLINE 0x0218 45 #define CRTC_OFFSET 0x0224 46 #define CRTC_OFFSET_CNTL 0x0228 47 #define CRTC_PITCH 0x022c 48 #define OVR_CLR 0x0230 49 #define OVR_WID_LEFT_RIGHT 0x0234 50 #define OVR_WID_TOP_BOTTOM 0x0238 51 #define LVDS_GEN_CNTL 0x02d0 52 #define DDA_CONFIG 0x02e0 53 #define DDA_ON_OFF 0x02e4 54 #define VGA_DDA_CONFIG 0x02e8 55 #define VGA_DDA_ON_OFF 0x02ec 56 #define CRTC2_H_TOTAL_DISP 0x0300 57 #define CRTC2_H_SYNC_STRT_WID 0x0304 58 #define CRTC2_V_TOTAL_DISP 0x0308 59 #define CRTC2_V_SYNC_STRT_WID 0x030c 60 #define CRTC2_VLINE_CRNT_VLINE 0x0310 61 #define CRTC2_CRNT_FRAME 0x0314 62 #define CRTC2_GUI_TRIG_VLINE 0x0318 63 #define CRTC2_OFFSET 0x0324 64 #define CRTC2_OFFSET_CNTL 0x0328 65 #define CRTC2_PITCH 0x032c 66 #define DDA2_CONFIG 0x03e0 67 #define DDA2_ON_OFF 0x03e4 68 #define CRTC2_GEN_CNTL 0x03f8 69 #define CRTC2_STATUS 0x03fc 70 #define OV0_SCALE_CNTL 0x0420 71 #define SUBPIC_CNTL 0x0540 72 #define PM4_BUFFER_OFFSET 0x0700 73 #define PM4_BUFFER_CNTL 0x0704 74 #define PM4_BUFFER_WM_CNTL 0x0708 75 #define PM4_BUFFER_DL_RPTR_ADDR 0x070c 76 #define PM4_BUFFER_DL_RPTR 0x0710 77 #define PM4_BUFFER_DL_WPTR 0x0714 78 #define PM4_VC_FPU_SETUP 0x071c 79 #define PM4_FPU_CNTL 0x0720 80 #define PM4_VC_FORMAT 0x0724 81 #define PM4_VC_CNTL 0x0728 82 #define PM4_VC_I01 0x072c 83 #define PM4_VC_VLOFF 0x0730 84 #define PM4_VC_VLSIZE 0x0734 85 #define PM4_IW_INDOFF 0x0738 86 #define PM4_IW_INDSIZE 0x073c 87 #define PM4_FPU_FPX0 0x0740 88 #define PM4_FPU_FPY0 0x0744 89 #define PM4_FPU_FPX1 0x0748 90 #define PM4_FPU_FPY1 0x074c 91 #define PM4_FPU_FPX2 0x0750 92 #define PM4_FPU_FPY2 0x0754 93 #define PM4_FPU_FPY3 0x0758 94 #define PM4_FPU_FPY4 0x075c 95 #define PM4_FPU_FPY5 0x0760 96 #define PM4_FPU_FPY6 0x0764 97 #define PM4_FPU_FPR 0x0768 98 #define PM4_FPU_FPG 0x076c 99 #define PM4_FPU_FPB 0x0770 100 #define PM4_FPU_FPA 0x0774 101 #define PM4_FPU_INTXY0 0x0780 102 #define PM4_FPU_INTXY1 0x0784 103 #define PM4_FPU_INTXY2 0x0788 104 #define PM4_FPU_INTARGB 0x078c 105 #define PM4_FPU_FPTWICEAREA 0x0790 106 #define PM4_FPU_DMAJOR01 0x0794 107 #define PM4_FPU_DMAJOR12 0x0798 108 #define PM4_FPU_DMAJOR02 0x079c 109 #define PM4_FPU_STAT 0x07a0 110 #define PM4_STAT 0x07b8 111 #define PM4_TEST_CNTL 0x07d0 112 #define PM4_MICROCODE_ADDR 0x07d4 113 #define PM4_MICROCODE_RADDR 0x07d8 114 #define PM4_MICROCODE_DATAH 0x07dc 115 #define PM4_MICROCODE_DATAL 0x07e0 116 #define PM4_CMDFIFO_ADDR 0x07e4 117 #define PM4_CMDFIFO_DATAH 0x07e8 118 #define PM4_CMDFIFO_DATAL 0x07ec 119 #define PM4_BUFFER_ADDR 0x07f0 120 #define PM4_BUFFER_DATAH 0x07f4 121 #define PM4_BUFFER_DATAL 0x07f8 122 #define PM4_MICRO_CNTL 0x07fc 123 #define CAP0_TRIG_CNTL 0x0950 124 #define CAP1_TRIG_CNTL 0x09c0 125 126 /****************************************************************************** 127 * GUI Block Memory Mapped Registers * 128 * These registers are FIFOed. * 129 *****************************************************************************/ 130 #define PM4_FIFO_DATA_EVEN 0x1000 131 #define PM4_FIFO_DATA_ODD 0x1004 132 133 #define DST_OFFSET 0x1404 134 #define DST_PITCH 0x1408 135 #define DST_WIDTH 0x140c 136 #define DST_HEIGHT 0x1410 137 #define SRC_X 0x1414 138 #define SRC_Y 0x1418 139 #define DST_X 0x141c 140 #define DST_Y 0x1420 141 #define SRC_PITCH_OFFSET 0x1428 142 #define DST_PITCH_OFFSET 0x142c 143 #define SRC_Y_X 0x1434 144 #define DST_Y_X 0x1438 145 #define DST_HEIGHT_WIDTH 0x143c 146 #define DP_GUI_MASTER_CNTL 0x146c 147 #define BRUSH_SCALE 0x1470 148 #define BRUSH_Y_X 0x1474 149 #define DP_BRUSH_BKGD_CLR 0x1478 150 #define DP_BRUSH_FRGD_CLR 0x147c 151 #define DST_WIDTH_X 0x1588 152 #define DST_HEIGHT_WIDTH_8 0x158c 153 #define SRC_X_Y 0x1590 154 #define DST_X_Y 0x1594 155 #define DST_WIDTH_HEIGHT 0x1598 156 #define DST_WIDTH_X_INCY 0x159c 157 #define DST_HEIGHT_Y 0x15a0 158 #define DST_X_SUB 0x15a4 159 #define DST_Y_SUB 0x15a8 160 #define SRC_OFFSET 0x15ac 161 #define SRC_PITCH 0x15b0 162 #define DST_HEIGHT_WIDTH_BW 0x15b4 163 #define CLR_CMP_CNTL 0x15c0 164 #define CLR_CMP_CLR_SRC 0x15c4 165 #define CLR_CMP_CLR_DST 0x15c8 166 #define CLR_CMP_MASK 0x15cc 167 #define DP_SRC_FRGD_CLR 0x15d8 168 #define DP_SRC_BKGD_CLR 0x15dc 169 #define DST_BRES_ERR 0x1628 170 #define DST_BRES_INC 0x162c 171 #define DST_BRES_DEC 0x1630 172 #define DST_BRES_LNTH 0x1634 173 #define DST_BRES_LNTH_SUB 0x1638 174 #define SC_LEFT 0x1640 175 #define SC_RIGHT 0x1644 176 #define SC_TOP 0x1648 177 #define SC_BOTTOM 0x164c 178 #define SRC_SC_RIGHT 0x1654 179 #define SRC_SC_BOTTOM 0x165c 180 #define GUI_DEBUG0 0x16a0 181 #define GUI_DEBUG1 0x16a4 182 #define GUI_TIMEOUT 0x16b0 183 #define GUI_TIMEOUT0 0x16b4 184 #define GUI_TIMEOUT1 0x16b8 185 #define GUI_PROBE 0x16bc 186 #define DP_CNTL 0x16c0 187 #define DP_DATATYPE 0x16c4 188 #define DP_MIX 0x16c8 189 #define DP_WRITE_MASK 0x16cc 190 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 191 #define DEFAULT_OFFSET 0x16e0 192 #define DEFAULT_PITCH 0x16e4 193 #define DEFAULT_SC_BOTTOM_RIGHT 0x16e8 194 #define SC_TOP_LEFT 0x16ec 195 #define SC_BOTTOM_RIGHT 0x16f0 196 #define SRC_SC_BOTTOM_RIGHT 0x16f4 197 #define WAIT_UNTIL 0x1720 198 #define CACHE_CNTL 0x1724 199 #define GUI_STAT 0x1740 200 #define PC_GUI_MODE 0x1744 201 #define PC_GUI_CTLSTAT 0x1748 202 #define PC_DEBUG_MODE 0x1760 203 #define BRES_DST_ERR_DEC 0x1780 204 #define TRAIL_BRES_T12_ERR_DEC 0x1784 205 #define TRAIL_BRES_T12_INC 0x1788 206 #define DP_T12_CNTL 0x178c 207 #define DST_BRES_T1_LNTH 0x1790 208 #define DST_BRES_T2_LNTH 0x1794 209 #define SCALE_SRC_HEIGHT_WIDTH 0x1994 210 #define SCALE_OFFSET_0 0x1998 211 #define SCALE_PITCH 0x199c 212 #define SCALE_X_INC 0x19a0 213 #define SCALE_Y_INC 0x19a4 214 #define SCALE_HACC 0x19a8 215 #define SCALE_VACC 0x19ac 216 #define SCALE_DST_X_Y 0x19b0 217 #define SCALE_DST_HEIGHT_WIDTH 0x19b4 218 #define SCALE_3D_CNTL 0x1a00 219 #define SCALE_3D_DATATYPE 0x1a20 220 #define SETUP_CNTL 0x1bc4 221 #define SOLID_COLOR 0x1bc8 222 #define WINDOW_XY_OFFSET 0x1bcc 223 #define DRAW_LINE_POINT 0x1bd0 224 #define SETUP_CNTL_PM4 0x1bd4 225 #define DST_PITCH_OFFSET_C 0x1c80 226 #define DP_GUI_MASTER_CNTL_C 0x1c84 227 #define SC_TOP_LEFT_C 0x1c88 228 #define SC_BOTTOM_RIGHT_C 0x1c8c 229 230 #define CLR_CMP_MASK_3D 0x1A28 231 #define MISC_3D_STATE_CNTL_REG 0x1CA0 232 #define MC_SRC1_CNTL 0x19D8 233 #define TEX_CNTL 0x1800 234 235 /* CONSTANTS */ 236 #define GUI_ACTIVE 0x80000000 237 #define ENGINE_IDLE 0x0 238 239 #define PLL_WR_EN 0x00000080 240 241 #define CLK_PIN_CNTL 0x0001 242 #define PPLL_CNTL 0x0002 243 #define PPLL_REF_DIV 0x0003 244 #define PPLL_DIV_0 0x0004 245 #define PPLL_DIV_1 0x0005 246 #define PPLL_DIV_2 0x0006 247 #define PPLL_DIV_3 0x0007 248 #define VCLK_ECP_CNTL 0x0008 249 #define HTOTAL_CNTL 0x0009 250 #define X_MPLL_REF_FB_DIV 0x000a 251 #define XPLL_CNTL 0x000b 252 #define XDLL_CNTL 0x000c 253 #define XCLK_CNTL 0x000d 254 #define MPLL_CNTL 0x000e 255 #define MCLK_CNTL 0x000f 256 #define AGP_PLL_CNTL 0x0010 257 #define FCP_CNTL 0x0012 258 #define PLL_TEST_CNTL 0x0013 259 #define P2PLL_CNTL 0x002a 260 #define P2PLL_REF_DIV 0x002b 261 #define P2PLL_DIV_0 0x002b 262 #define POWER_MANAGEMENT 0x002f 263 264 #define PPLL_RESET 0x01 265 #define PPLL_ATOMIC_UPDATE_EN 0x10000 266 #define PPLL_VGA_ATOMIC_UPDATE_EN 0x20000 267 #define PPLL_REF_DIV_MASK 0x3FF 268 #define PPLL_FB3_DIV_MASK 0x7FF 269 #define PPLL_POST3_DIV_MASK 0x70000 270 #define PPLL_ATOMIC_UPDATE_R 0x8000 271 #define PPLL_ATOMIC_UPDATE_W 0x8000 272 #define MEM_CFG_TYPE_MASK 0x3 273 #define XCLK_SRC_SEL_MASK 0x7 274 #define XPLL_FB_DIV_MASK 0xFF00 275 #define X_MPLL_REF_DIV_MASK 0xFF 276 277 /* CRTC control values (CRTC_GEN_CNTL) */ 278 #define CRTC_CSYNC_EN 0x00000010 279 280 #define CRTC2_DBL_SCAN_EN 0x00000001 281 #define CRTC2_DISPLAY_DIS 0x00800000 282 #define CRTC2_FIFO_EXTSENSE 0x00200000 283 #define CRTC2_ICON_EN 0x00100000 284 #define CRTC2_CUR_EN 0x00010000 285 #define CRTC2_EN 0x02000000 286 #define CRTC2_DISP_REQ_EN_B 0x04000000 287 288 #define CRTC_PIX_WIDTH_MASK 0x00000700 289 #define CRTC_PIX_WIDTH_4BPP 0x00000100 290 #define CRTC_PIX_WIDTH_8BPP 0x00000200 291 #define CRTC_PIX_WIDTH_15BPP 0x00000300 292 #define CRTC_PIX_WIDTH_16BPP 0x00000400 293 #define CRTC_PIX_WIDTH_24BPP 0x00000500 294 #define CRTC_PIX_WIDTH_32BPP 0x00000600 295 296 /* DAC_CNTL bit constants */ 297 #define DAC_8BIT_EN 0x00000100 298 #define DAC_MASK 0xFF000000 299 #define DAC_BLANKING 0x00000004 300 #define DAC_RANGE_CNTL 0x00000003 301 #define DAC_CLK_SEL 0x00000010 302 #define DAC_PALETTE_ACCESS_CNTL 0x00000020 303 #define DAC_PALETTE2_SNOOP_EN 0x00000040 304 #define DAC_PDWN 0x00008000 305 306 /* CRTC_EXT_CNTL */ 307 #define CRT_CRTC_ON 0x00008000 308 309 /* GEN_RESET_CNTL bit constants */ 310 #define SOFT_RESET_GUI 0x00000001 311 #define SOFT_RESET_VCLK 0x00000100 312 #define SOFT_RESET_PCLK 0x00000200 313 #define SOFT_RESET_ECP 0x00000400 314 #define SOFT_RESET_DISPENG_XCLK 0x00000800 315 316 /* PC_GUI_CTLSTAT bit constants */ 317 #define PC_BUSY_INIT 0x10000000 318 #define PC_BUSY_GUI 0x20000000 319 #define PC_BUSY_NGUI 0x40000000 320 #define PC_BUSY 0x80000000 321 322 #define BUS_MASTER_DIS 0x00000040 323 #define PM4_BUFFER_CNTL_NONPM4 0x00000000 324 325 /* DP_DATATYPE bit constants */ 326 #define DST_8BPP 0x00000002 327 #define DST_15BPP 0x00000003 328 #define DST_16BPP 0x00000004 329 #define DST_24BPP 0x00000005 330 #define DST_32BPP 0x00000006 331 332 #define BRUSH_SOLIDCOLOR 0x00000d00 333 334 /* DP_GUI_MASTER_CNTL bit constants */ 335 #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 336 #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 337 #define GMC_SRC_CLIP_DEFAULT 0x00000000 338 #define GMC_DST_CLIP_DEFAULT 0x00000000 339 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 340 #define GMC_SRC_DSTCOLOR 0x00003000 341 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 342 #define GMC_DP_SRC_RECT 0x02000000 343 #define GMC_3D_FCN_EN_CLR 0x00000000 344 #define GMC_AUX_CLIP_CLEAR 0x20000000 345 #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 346 #define GMC_WRITE_MASK_SET 0x40000000 347 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 348 349 /* DP_GUI_MASTER_CNTL ROP3 named constants */ 350 #define ROP3_PATCOPY 0x00f00000 351 #define ROP3_SRCCOPY 0x00cc0000 352 353 #define SRC_DSTCOLOR 0x00030000 354 355 /* DP_CNTL bit constants */ 356 #define DST_X_RIGHT_TO_LEFT 0x00000000 357 #define DST_X_LEFT_TO_RIGHT 0x00000001 358 #define DST_Y_BOTTOM_TO_TOP 0x00000000 359 #define DST_Y_TOP_TO_BOTTOM 0x00000002 360 #define DST_X_MAJOR 0x00000000 361 #define DST_Y_MAJOR 0x00000004 362 #define DST_X_TILE 0x00000008 363 #define DST_Y_TILE 0x00000010 364 #define DST_LAST_PEL 0x00000020 365 #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 366 #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 367 #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 368 #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 369 #define DST_BRES_SIGN 0x00000100 370 #define DST_HOST_BIG_ENDIAN_EN 0x00000200 371 #define DST_POLYLINE_NONLAST 0x00008000 372 #define DST_RASTER_STALL 0x00010000 373 #define DST_POLY_EDGE 0x00040000 374 375 /* DP_MIX bit constants */ 376 #define DP_SRC_RECT 0x00000200 377 #define DP_SRC_HOST 0x00000300 378 #define DP_SRC_HOST_BYTEALIGN 0x00000400 379 380 /* LVDS_GEN_CNTL constants */ 381 #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 382 #define LVDS_BL_MOD_LEVEL_SHIFT 8 383 #define LVDS_BL_MOD_EN 0x00010000 384 #define LVDS_DIGION 0x00040000 385 #define LVDS_BLON 0x00080000 386 #define LVDS_ON 0x00000001 387 #define LVDS_DISPLAY_DIS 0x00000002 388 #define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004 389 #define LVDS_PANEL_24BITS_TFT 0x00000008 390 #define LVDS_FRAME_MOD_NO 0x00000000 391 #define LVDS_FRAME_MOD_2_LEVELS 0x00000010 392 #define LVDS_FRAME_MOD_4_LEVELS 0x00000020 393 #define LVDS_RST_FM 0x00000040 394 #define LVDS_EN 0x00000080 395 396 /* CRTC2_GEN_CNTL constants */ 397 #define CRTC2_EN 0x02000000 398 399 /* POWER_MANAGEMENT constants */ 400 #define PWR_MGT_ON 0x00000001 401 #define PWR_MGT_MODE_MASK 0x00000006 402 #define PWR_MGT_MODE_PIN 0x00000000 403 #define PWR_MGT_MODE_REGISTER 0x00000002 404 #define PWR_MGT_MODE_TIMER 0x00000004 405 #define PWR_MGT_MODE_PCI 0x00000006 406 #define PWR_MGT_AUTO_PWR_UP_EN 0x00000008 407 #define PWR_MGT_ACTIVITY_PIN_ON 0x00000010 408 #define PWR_MGT_STANDBY_POL 0x00000020 409 #define PWR_MGT_SUSPEND_POL 0x00000040 410 #define PWR_MGT_SELF_REFRESH 0x00000080 411 #define PWR_MGT_ACTIVITY_PIN_EN 0x00000100 412 #define PWR_MGT_KEYBD_SNOOP 0x00000200 413 #define PWR_MGT_TRISTATE_MEM_EN 0x00000800 414 #define PWR_MGT_SELW4MS 0x00001000 415 #define PWR_MGT_SLOWDOWN_MCLK 0x00002000 416 417 #define PMI_PMSCR_REG 0x60 418 419 /* used by ATI bug fix for hardware ROM */ 420 #define RAGE128_MPP_TB_CONFIG 0x01c0 421 422 #endif /* REG_RAGE128_H */ 423