1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * 6 * Authors: 7 * Santosh Yaraganavi <santosh.sy@samsung.com> 8 * Vinayak Holikatti <h.vinayak@samsung.com> 9 */ 10 11 #ifndef _UFSHCI_H 12 #define _UFSHCI_H 13 14 #include <scsi/scsi_host.h> 15 16 enum { 17 TASK_REQ_UPIU_SIZE_DWORDS = 8, 18 TASK_RSP_UPIU_SIZE_DWORDS = 8, 19 ALIGNED_UPIU_SIZE = 512, 20 }; 21 22 /* UFSHCI Registers */ 23 enum { 24 REG_CONTROLLER_CAPABILITIES = 0x00, 25 REG_MCQCAP = 0x04, 26 REG_UFS_VERSION = 0x08, 27 REG_CONTROLLER_DEV_ID = 0x10, 28 REG_CONTROLLER_PROD_ID = 0x14, 29 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, 30 REG_INTERRUPT_STATUS = 0x20, 31 REG_INTERRUPT_ENABLE = 0x24, 32 REG_CONTROLLER_STATUS = 0x30, 33 REG_CONTROLLER_ENABLE = 0x34, 34 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, 35 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, 36 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, 37 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, 38 REG_UIC_ERROR_CODE_DME = 0x48, 39 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, 40 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, 41 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, 42 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, 43 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, 44 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, 45 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, 46 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, 47 REG_UTP_TASK_REQ_DOOR_BELL = 0x78, 48 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, 49 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, 50 REG_UIC_COMMAND = 0x90, 51 REG_UIC_COMMAND_ARG_1 = 0x94, 52 REG_UIC_COMMAND_ARG_2 = 0x98, 53 REG_UIC_COMMAND_ARG_3 = 0x9C, 54 55 UFSHCI_REG_SPACE_SIZE = 0xA0, 56 57 REG_UFS_CCAP = 0x100, 58 REG_UFS_CRYPTOCAP = 0x104, 59 60 REG_UFS_MEM_CFG = 0x300, 61 REG_UFS_MCQ_CFG = 0x380, 62 REG_UFS_ESILBA = 0x384, 63 REG_UFS_ESIUBA = 0x388, 64 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, 65 }; 66 67 /* Controller capability masks */ 68 enum { 69 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F, 70 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, 71 MASK_EHSLUTRD_SUPPORTED = 0x00400000, 72 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, 73 MASK_64_ADDRESSING_SUPPORT = 0x01000000, 74 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, 75 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, 76 MASK_CRYPTO_SUPPORT = 0x10000000, 77 MASK_MCQ_SUPPORT = 0x40000000, 78 }; 79 80 /* MCQ capability mask */ 81 enum { 82 MASK_EXT_IID_SUPPORT = 0x00000400, 83 }; 84 85 enum { 86 REG_SQATTR = 0x0, 87 REG_SQLBA = 0x4, 88 REG_SQUBA = 0x8, 89 REG_SQDAO = 0xC, 90 REG_SQISAO = 0x10, 91 92 REG_CQATTR = 0x20, 93 REG_CQLBA = 0x24, 94 REG_CQUBA = 0x28, 95 REG_CQDAO = 0x2C, 96 REG_CQISAO = 0x30, 97 }; 98 99 enum { 100 REG_SQHP = 0x0, 101 REG_SQTP = 0x4, 102 }; 103 104 enum { 105 REG_CQHP = 0x0, 106 REG_CQTP = 0x4, 107 }; 108 109 enum { 110 REG_CQIS = 0x0, 111 REG_CQIE = 0x4, 112 }; 113 114 #define UFS_MASK(mask, offset) ((mask) << (offset)) 115 116 /* UFS Version 08h */ 117 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) 118 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) 119 120 /* 121 * Controller UFSHCI version 122 * - 2.x and newer use the following scheme: 123 * major << 8 + minor << 4 124 * - 1.x has been converted to match this in 125 * ufshcd_get_ufs_version() 126 */ 127 static inline u32 ufshci_version(u32 major, u32 minor) 128 { 129 return (major << 8) + (minor << 4); 130 } 131 132 /* 133 * HCDDID - Host Controller Identification Descriptor 134 * - Device ID and Device Class 10h 135 */ 136 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0) 137 #define DEVICE_ID UFS_MASK(0xFF, 24) 138 139 /* 140 * HCPMID - Host Controller Identification Descriptor 141 * - Product/Manufacturer ID 14h 142 */ 143 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0) 144 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16) 145 146 /* AHIT - Auto-Hibernate Idle Timer */ 147 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0) 148 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10) 149 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10 150 #define UFSHCI_AHIBERN8_MAX (1023 * 100000) 151 152 /* 153 * IS - Interrupt Status - 20h 154 */ 155 #define UTP_TRANSFER_REQ_COMPL 0x1 156 #define UIC_DME_END_PT_RESET 0x2 157 #define UIC_ERROR 0x4 158 #define UIC_TEST_MODE 0x8 159 #define UIC_POWER_MODE 0x10 160 #define UIC_HIBERNATE_EXIT 0x20 161 #define UIC_HIBERNATE_ENTER 0x40 162 #define UIC_LINK_LOST 0x80 163 #define UIC_LINK_STARTUP 0x100 164 #define UTP_TASK_REQ_COMPL 0x200 165 #define UIC_COMMAND_COMPL 0x400 166 #define DEVICE_FATAL_ERROR 0x800 167 #define CONTROLLER_FATAL_ERROR 0x10000 168 #define SYSTEM_BUS_FATAL_ERROR 0x20000 169 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000 170 #define MCQ_CQ_EVENT_STATUS 0x100000 171 172 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\ 173 UIC_HIBERNATE_EXIT) 174 175 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\ 176 UIC_POWER_MODE) 177 178 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK) 179 180 #define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS) 181 182 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\ 183 CONTROLLER_FATAL_ERROR |\ 184 SYSTEM_BUS_FATAL_ERROR |\ 185 CRYPTO_ENGINE_FATAL_ERROR |\ 186 UIC_LINK_LOST) 187 188 /* HCS - Host Controller Status 30h */ 189 #define DEVICE_PRESENT 0x1 190 #define UTP_TRANSFER_REQ_LIST_READY 0x2 191 #define UTP_TASK_REQ_LIST_READY 0x4 192 #define UIC_COMMAND_READY 0x8 193 #define HOST_ERROR_INDICATOR 0x10 194 #define DEVICE_ERROR_INDICATOR 0x20 195 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) 196 197 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\ 198 UTP_TASK_REQ_LIST_READY |\ 199 UIC_COMMAND_READY) 200 201 enum { 202 PWR_OK = 0x0, 203 PWR_LOCAL = 0x01, 204 PWR_REMOTE = 0x02, 205 PWR_BUSY = 0x03, 206 PWR_ERROR_CAP = 0x04, 207 PWR_FATAL_ERROR = 0x05, 208 }; 209 210 /* HCE - Host Controller Enable 34h */ 211 #define CONTROLLER_ENABLE 0x1 212 #define CONTROLLER_DISABLE 0x0 213 #define CRYPTO_GENERAL_ENABLE 0x2 214 215 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */ 216 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000 217 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F 218 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF 219 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10 220 221 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */ 222 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000 223 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF 224 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2 225 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4 226 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8 227 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20 228 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000 229 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001 230 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002 231 232 /* UECN - Host UIC Error Code Network Layer 40h */ 233 #define UIC_NETWORK_LAYER_ERROR 0x80000000 234 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7 235 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1 236 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2 237 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4 238 239 /* UECT - Host UIC Error Code Transport Layer 44h */ 240 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000 241 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F 242 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1 243 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2 244 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4 245 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8 246 #define UIC_TRANSPORT_BAD_TC 0x10 247 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20 248 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40 249 250 /* UECDME - Host UIC Error Code DME 48h */ 251 #define UIC_DME_ERROR 0x80000000 252 #define UIC_DME_ERROR_CODE_MASK 0x1 253 254 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */ 255 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF 256 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8) 257 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000 258 #define INT_AGGR_STATUS_BIT 0x100000 259 #define INT_AGGR_PARAM_WRITE 0x1000000 260 #define INT_AGGR_ENABLE 0x80000000 261 262 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */ 263 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1 264 265 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */ 266 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1 267 268 /* CQISy - CQ y Interrupt Status Register */ 269 #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1 270 271 /* UICCMD - UIC Command */ 272 #define COMMAND_OPCODE_MASK 0xFF 273 #define GEN_SELECTOR_INDEX_MASK 0xFFFF 274 275 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) 276 #define RESET_LEVEL 0xFF 277 278 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) 279 #define CONFIG_RESULT_CODE_MASK 0xFF 280 #define GENERIC_ERROR_CODE_MASK 0xFF 281 282 /* GenSelectorIndex calculation macros for M-PHY attributes */ 283 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) 284 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) 285 286 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\ 287 ((sel) & 0xFFFF)) 288 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0) 289 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16) 290 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF) 291 292 /* Link Status*/ 293 enum link_status { 294 UFSHCD_LINK_IS_DOWN = 1, 295 UFSHCD_LINK_IS_UP = 2, 296 }; 297 298 /* UIC Commands */ 299 enum uic_cmd_dme { 300 UIC_CMD_DME_GET = 0x01, 301 UIC_CMD_DME_SET = 0x02, 302 UIC_CMD_DME_PEER_GET = 0x03, 303 UIC_CMD_DME_PEER_SET = 0x04, 304 UIC_CMD_DME_POWERON = 0x10, 305 UIC_CMD_DME_POWEROFF = 0x11, 306 UIC_CMD_DME_ENABLE = 0x12, 307 UIC_CMD_DME_RESET = 0x14, 308 UIC_CMD_DME_END_PT_RST = 0x15, 309 UIC_CMD_DME_LINK_STARTUP = 0x16, 310 UIC_CMD_DME_HIBER_ENTER = 0x17, 311 UIC_CMD_DME_HIBER_EXIT = 0x18, 312 UIC_CMD_DME_TEST_MODE = 0x1A, 313 }; 314 315 /* UIC Config result code / Generic error code */ 316 enum { 317 UIC_CMD_RESULT_SUCCESS = 0x00, 318 UIC_CMD_RESULT_INVALID_ATTR = 0x01, 319 UIC_CMD_RESULT_FAILURE = 0x01, 320 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02, 321 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03, 322 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04, 323 UIC_CMD_RESULT_BAD_INDEX = 0x05, 324 UIC_CMD_RESULT_LOCKED_ATTR = 0x06, 325 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07, 326 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08, 327 UIC_CMD_RESULT_BUSY = 0x09, 328 UIC_CMD_RESULT_DME_FAILURE = 0x0A, 329 }; 330 331 #define MASK_UIC_COMMAND_RESULT 0xFF 332 333 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8) 334 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0) 335 336 /* Interrupt disable masks */ 337 enum { 338 /* Interrupt disable mask for UFSHCI v1.0 */ 339 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF, 340 INTERRUPT_MASK_RW_VER_10 = 0x30000, 341 342 /* Interrupt disable mask for UFSHCI v1.1 */ 343 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, 344 345 /* Interrupt disable mask for UFSHCI v2.1 */ 346 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF, 347 }; 348 349 /* CCAP - Crypto Capability 100h */ 350 union ufs_crypto_capabilities { 351 __le32 reg_val; 352 struct { 353 u8 num_crypto_cap; 354 u8 config_count; 355 u8 reserved; 356 u8 config_array_ptr; 357 }; 358 }; 359 360 enum ufs_crypto_key_size { 361 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0, 362 UFS_CRYPTO_KEY_SIZE_128 = 0x1, 363 UFS_CRYPTO_KEY_SIZE_192 = 0x2, 364 UFS_CRYPTO_KEY_SIZE_256 = 0x3, 365 UFS_CRYPTO_KEY_SIZE_512 = 0x4, 366 }; 367 368 enum ufs_crypto_alg { 369 UFS_CRYPTO_ALG_AES_XTS = 0x0, 370 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1, 371 UFS_CRYPTO_ALG_AES_ECB = 0x2, 372 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3, 373 }; 374 375 /* x-CRYPTOCAP - Crypto Capability X */ 376 union ufs_crypto_cap_entry { 377 __le32 reg_val; 378 struct { 379 u8 algorithm_id; 380 u8 sdus_mask; /* Supported data unit size mask */ 381 u8 key_size; 382 u8 reserved; 383 }; 384 }; 385 386 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7) 387 #define UFS_CRYPTO_KEY_MAX_SIZE 64 388 /* x-CRYPTOCFG - Crypto Configuration X */ 389 union ufs_crypto_cfg_entry { 390 __le32 reg_val[32]; 391 struct { 392 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE]; 393 u8 data_unit_size; 394 u8 crypto_cap_idx; 395 u8 reserved_1; 396 u8 config_enable; 397 u8 reserved_multi_host; 398 u8 reserved_2; 399 u8 vsb[2]; 400 u8 reserved_3[56]; 401 }; 402 }; 403 404 /* 405 * Request Descriptor Definitions 406 */ 407 408 /* Transfer request command type */ 409 enum { 410 UTP_CMD_TYPE_SCSI = 0x0, 411 UTP_CMD_TYPE_UFS = 0x1, 412 UTP_CMD_TYPE_DEV_MANAGE = 0x2, 413 }; 414 415 /* To accommodate UFS2.0 required Command type */ 416 enum { 417 UTP_CMD_TYPE_UFS_STORAGE = 0x1, 418 }; 419 420 enum { 421 UTP_SCSI_COMMAND = 0x00000000, 422 UTP_NATIVE_UFS_COMMAND = 0x10000000, 423 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000, 424 UTP_REQ_DESC_INT_CMD = 0x01000000, 425 UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000, 426 }; 427 428 /* UTP Transfer Request Data Direction (DD) */ 429 enum { 430 UTP_NO_DATA_TRANSFER = 0x00000000, 431 UTP_HOST_TO_DEVICE = 0x02000000, 432 UTP_DEVICE_TO_HOST = 0x04000000, 433 }; 434 435 /* Overall command status values */ 436 enum utp_ocs { 437 OCS_SUCCESS = 0x0, 438 OCS_INVALID_CMD_TABLE_ATTR = 0x1, 439 OCS_INVALID_PRDT_ATTR = 0x2, 440 OCS_MISMATCH_DATA_BUF_SIZE = 0x3, 441 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4, 442 OCS_PEER_COMM_FAILURE = 0x5, 443 OCS_ABORTED = 0x6, 444 OCS_FATAL_ERROR = 0x7, 445 OCS_DEVICE_FATAL_ERROR = 0x8, 446 OCS_INVALID_CRYPTO_CONFIG = 0x9, 447 OCS_GENERAL_CRYPTO_ERROR = 0xA, 448 OCS_INVALID_COMMAND_STATUS = 0x0F, 449 }; 450 451 enum { 452 MASK_OCS = 0x0F, 453 }; 454 455 /* The maximum length of the data byte count field in the PRDT is 256KB */ 456 #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024) 457 /* The granularity of the data byte count field in the PRDT is 32-bit */ 458 #define PRDT_DATA_BYTE_COUNT_PAD 4 459 460 /** 461 * struct ufshcd_sg_entry - UFSHCI PRD Entry 462 * @addr: Physical address; DW-0 and DW-1. 463 * @reserved: Reserved for future use DW-2 464 * @size: size of physical segment DW-3 465 */ 466 struct ufshcd_sg_entry { 467 __le64 addr; 468 __le32 reserved; 469 __le32 size; 470 /* 471 * followed by variant-specific fields if 472 * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined. 473 */ 474 }; 475 476 /** 477 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD) 478 * @command_upiu: Command UPIU Frame address 479 * @response_upiu: Response UPIU Frame address 480 * @prd_table: Physical Region Descriptor: an array of SG_ALL struct 481 * ufshcd_sg_entry's. Variant-specific fields may be present after each. 482 */ 483 struct utp_transfer_cmd_desc { 484 u8 command_upiu[ALIGNED_UPIU_SIZE]; 485 u8 response_upiu[ALIGNED_UPIU_SIZE]; 486 u8 prd_table[]; 487 }; 488 489 /** 490 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD 491 * @dword0: Descriptor Header DW0 492 * @dword1: Descriptor Header DW1 493 * @dword2: Descriptor Header DW2 494 * @dword3: Descriptor Header DW3 495 */ 496 struct request_desc_header { 497 __le32 dword_0; 498 __le32 dword_1; 499 __le32 dword_2; 500 __le32 dword_3; 501 }; 502 503 /** 504 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD) 505 * @header: UTRD header DW-0 to DW-3 506 * @command_desc_base_addr_lo: UCD base address low DW-4 507 * @command_desc_base_addr_hi: UCD base address high DW-5 508 * @response_upiu_length: response UPIU length DW-6 509 * @response_upiu_offset: response UPIU offset DW-6 510 * @prd_table_length: Physical region descriptor length DW-7 511 * @prd_table_offset: Physical region descriptor offset DW-7 512 */ 513 struct utp_transfer_req_desc { 514 515 /* DW 0-3 */ 516 struct request_desc_header header; 517 518 /* DW 4-5*/ 519 __le32 command_desc_base_addr_lo; 520 __le32 command_desc_base_addr_hi; 521 522 /* DW 6 */ 523 __le16 response_upiu_length; 524 __le16 response_upiu_offset; 525 526 /* DW 7 */ 527 __le16 prd_table_length; 528 __le16 prd_table_offset; 529 }; 530 531 /* MCQ Completion Queue Entry */ 532 struct cq_entry { 533 /* DW 0-1 */ 534 __le64 command_desc_base_addr; 535 536 /* DW 2 */ 537 __le16 response_upiu_length; 538 __le16 response_upiu_offset; 539 540 /* DW 3 */ 541 __le16 prd_table_length; 542 __le16 prd_table_offset; 543 544 /* DW 4 */ 545 __le32 status; 546 547 /* DW 5-7 */ 548 __le32 reserved[3]; 549 }; 550 551 static_assert(sizeof(struct cq_entry) == 32); 552 553 /* 554 * UTMRD structure. 555 */ 556 struct utp_task_req_desc { 557 /* DW 0-3 */ 558 struct request_desc_header header; 559 560 /* DW 4-11 - Task request UPIU structure */ 561 struct { 562 struct utp_upiu_header req_header; 563 __be32 input_param1; 564 __be32 input_param2; 565 __be32 input_param3; 566 __be32 __reserved1[2]; 567 } upiu_req; 568 569 /* DW 12-19 - Task Management Response UPIU structure */ 570 struct { 571 struct utp_upiu_header rsp_header; 572 __be32 output_param1; 573 __be32 output_param2; 574 __be32 __reserved2[3]; 575 } upiu_rsp; 576 }; 577 578 #endif /* End of Header */ 579