1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #ifndef _UFSHCD_H 13 #define _UFSHCD_H 14 15 #include <linux/bitfield.h> 16 #include <linux/blk-crypto-profile.h> 17 #include <linux/blk-mq.h> 18 #include <linux/devfreq.h> 19 #include <linux/msi.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/dma-direction.h> 22 #include <scsi/scsi_device.h> 23 #include <scsi/scsi_host.h> 24 #include <ufs/unipro.h> 25 #include <ufs/ufs.h> 26 #include <ufs/ufs_quirks.h> 27 #include <ufs/ufshci.h> 28 29 #define UFSHCD "ufshcd" 30 31 struct ufs_hba; 32 33 enum dev_cmd_type { 34 DEV_CMD_TYPE_NOP = 0x0, 35 DEV_CMD_TYPE_QUERY = 0x1, 36 DEV_CMD_TYPE_RPMB = 0x2, 37 }; 38 39 enum ufs_event_type { 40 /* uic specific errors */ 41 UFS_EVT_PA_ERR = 0, 42 UFS_EVT_DL_ERR, 43 UFS_EVT_NL_ERR, 44 UFS_EVT_TL_ERR, 45 UFS_EVT_DME_ERR, 46 47 /* fatal errors */ 48 UFS_EVT_AUTO_HIBERN8_ERR, 49 UFS_EVT_FATAL_ERR, 50 UFS_EVT_LINK_STARTUP_FAIL, 51 UFS_EVT_RESUME_ERR, 52 UFS_EVT_SUSPEND_ERR, 53 UFS_EVT_WL_SUSP_ERR, 54 UFS_EVT_WL_RES_ERR, 55 56 /* abnormal events */ 57 UFS_EVT_DEV_RESET, 58 UFS_EVT_HOST_RESET, 59 UFS_EVT_ABORT, 60 61 UFS_EVT_CNT, 62 }; 63 64 /** 65 * struct uic_command - UIC command structure 66 * @command: UIC command 67 * @argument1: UIC command argument 1 68 * @argument2: UIC command argument 2 69 * @argument3: UIC command argument 3 70 * @cmd_active: Indicate if UIC command is outstanding 71 * @done: UIC command completion 72 */ 73 struct uic_command { 74 u32 command; 75 u32 argument1; 76 u32 argument2; 77 u32 argument3; 78 int cmd_active; 79 struct completion done; 80 }; 81 82 /* Used to differentiate the power management options */ 83 enum ufs_pm_op { 84 UFS_RUNTIME_PM, 85 UFS_SYSTEM_PM, 86 UFS_SHUTDOWN_PM, 87 }; 88 89 /* Host <-> Device UniPro Link state */ 90 enum uic_link_state { 91 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 92 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 93 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 94 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ 95 }; 96 97 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) 98 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ 99 UIC_LINK_ACTIVE_STATE) 100 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ 101 UIC_LINK_HIBERN8_STATE) 102 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ 103 UIC_LINK_BROKEN_STATE) 104 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) 105 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ 106 UIC_LINK_ACTIVE_STATE) 107 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ 108 UIC_LINK_HIBERN8_STATE) 109 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ 110 UIC_LINK_BROKEN_STATE) 111 112 #define ufshcd_set_ufs_dev_active(h) \ 113 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) 114 #define ufshcd_set_ufs_dev_sleep(h) \ 115 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) 116 #define ufshcd_set_ufs_dev_poweroff(h) \ 117 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) 118 #define ufshcd_set_ufs_dev_deepsleep(h) \ 119 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) 120 #define ufshcd_is_ufs_dev_active(h) \ 121 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) 122 #define ufshcd_is_ufs_dev_sleep(h) \ 123 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) 124 #define ufshcd_is_ufs_dev_poweroff(h) \ 125 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) 126 #define ufshcd_is_ufs_dev_deepsleep(h) \ 127 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) 128 129 /* 130 * UFS Power management levels. 131 * Each level is in increasing order of power savings, except DeepSleep 132 * which is lower than PowerDown with power on but not PowerDown with 133 * power off. 134 */ 135 enum ufs_pm_level { 136 UFS_PM_LVL_0, 137 UFS_PM_LVL_1, 138 UFS_PM_LVL_2, 139 UFS_PM_LVL_3, 140 UFS_PM_LVL_4, 141 UFS_PM_LVL_5, 142 UFS_PM_LVL_6, 143 UFS_PM_LVL_MAX 144 }; 145 146 struct ufs_pm_lvl_states { 147 enum ufs_dev_pwr_mode dev_state; 148 enum uic_link_state link_state; 149 }; 150 151 /** 152 * struct ufshcd_lrb - local reference block 153 * @utr_descriptor_ptr: UTRD address of the command 154 * @ucd_req_ptr: UCD address of the command 155 * @ucd_rsp_ptr: Response UPIU address for this command 156 * @ucd_prdt_ptr: PRDT address of the command 157 * @utrd_dma_addr: UTRD dma address for debug 158 * @ucd_prdt_dma_addr: PRDT dma address for debug 159 * @ucd_rsp_dma_addr: UPIU response dma address for debug 160 * @ucd_req_dma_addr: UPIU request dma address for debug 161 * @cmd: pointer to SCSI command 162 * @scsi_status: SCSI status of the command 163 * @command_type: SCSI, UFS, Query. 164 * @task_tag: Task tag of the command 165 * @lun: LUN of the command 166 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) 167 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) 168 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) 169 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) 170 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) 171 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) 172 * @data_unit_num: the data unit number for the first block for inline crypto 173 * @req_abort_skip: skip request abort task flag 174 */ 175 struct ufshcd_lrb { 176 struct utp_transfer_req_desc *utr_descriptor_ptr; 177 struct utp_upiu_req *ucd_req_ptr; 178 struct utp_upiu_rsp *ucd_rsp_ptr; 179 struct ufshcd_sg_entry *ucd_prdt_ptr; 180 181 dma_addr_t utrd_dma_addr; 182 dma_addr_t ucd_req_dma_addr; 183 dma_addr_t ucd_rsp_dma_addr; 184 dma_addr_t ucd_prdt_dma_addr; 185 186 struct scsi_cmnd *cmd; 187 int scsi_status; 188 189 int command_type; 190 int task_tag; 191 u8 lun; /* UPIU LUN id field is only 8-bit wide */ 192 bool intr_cmd; 193 ktime_t issue_time_stamp; 194 u64 issue_time_stamp_local_clock; 195 ktime_t compl_time_stamp; 196 u64 compl_time_stamp_local_clock; 197 #ifdef CONFIG_SCSI_UFS_CRYPTO 198 int crypto_key_slot; 199 u64 data_unit_num; 200 #endif 201 202 bool req_abort_skip; 203 }; 204 205 /** 206 * struct ufs_query_req - parameters for building a query request 207 * @query_func: UPIU header query function 208 * @upiu_req: the query request data 209 */ 210 struct ufs_query_req { 211 u8 query_func; 212 struct utp_upiu_query upiu_req; 213 }; 214 215 /** 216 * struct ufs_query_resp - UPIU QUERY 217 * @response: device response code 218 * @upiu_res: query response data 219 */ 220 struct ufs_query_res { 221 struct utp_upiu_query upiu_res; 222 }; 223 224 /** 225 * struct ufs_query - holds relevant data structures for query request 226 * @request: request upiu and function 227 * @descriptor: buffer for sending/receiving descriptor 228 * @response: response upiu and response 229 */ 230 struct ufs_query { 231 struct ufs_query_req request; 232 u8 *descriptor; 233 struct ufs_query_res response; 234 }; 235 236 /** 237 * struct ufs_dev_cmd - all assosiated fields with device management commands 238 * @type: device management command type - Query, NOP OUT 239 * @lock: lock to allow one command at a time 240 * @complete: internal commands completion 241 * @query: Device management query information 242 */ 243 struct ufs_dev_cmd { 244 enum dev_cmd_type type; 245 struct mutex lock; 246 struct completion *complete; 247 struct ufs_query query; 248 }; 249 250 /** 251 * struct ufs_clk_info - UFS clock related info 252 * @list: list headed by hba->clk_list_head 253 * @clk: clock node 254 * @name: clock name 255 * @max_freq: maximum frequency supported by the clock 256 * @min_freq: min frequency that can be used for clock scaling 257 * @curr_freq: indicates the current frequency that it is set to 258 * @keep_link_active: indicates that the clk should not be disabled if 259 * link is active 260 * @enabled: variable to check against multiple enable/disable 261 */ 262 struct ufs_clk_info { 263 struct list_head list; 264 struct clk *clk; 265 const char *name; 266 u32 max_freq; 267 u32 min_freq; 268 u32 curr_freq; 269 bool keep_link_active; 270 bool enabled; 271 }; 272 273 enum ufs_notify_change_status { 274 PRE_CHANGE, 275 POST_CHANGE, 276 }; 277 278 struct ufs_pa_layer_attr { 279 u32 gear_rx; 280 u32 gear_tx; 281 u32 lane_rx; 282 u32 lane_tx; 283 u32 pwr_rx; 284 u32 pwr_tx; 285 u32 hs_rate; 286 }; 287 288 struct ufs_pwr_mode_info { 289 bool is_valid; 290 struct ufs_pa_layer_attr info; 291 }; 292 293 /** 294 * struct ufs_hba_variant_ops - variant specific callbacks 295 * @name: variant name 296 * @init: called when the driver is initialized 297 * @exit: called to cleanup everything done in init 298 * @get_ufs_hci_version: called to get UFS HCI version 299 * @clk_scale_notify: notifies that clks are scaled up/down 300 * @setup_clocks: called before touching any of the controller registers 301 * @hce_enable_notify: called before and after HCE enable bit is set to allow 302 * variant specific Uni-Pro initialization. 303 * @link_startup_notify: called before and after Link startup is carried out 304 * to allow variant specific Uni-Pro initialization. 305 * @pwr_change_notify: called before and after a power mode change 306 * is carried out to allow vendor spesific capabilities 307 * to be set. PRE_CHANGE can modify final_params based 308 * on desired_pwr_mode, but POST_CHANGE must not alter 309 * the final_params parameter 310 * @setup_xfer_req: called before any transfer request is issued 311 * to set some things 312 * @setup_task_mgmt: called before any task management request is issued 313 * to set some things 314 * @hibern8_notify: called around hibern8 enter/exit 315 * @apply_dev_quirks: called to apply device specific quirks 316 * @fixup_dev_quirks: called to modify device specific quirks 317 * @suspend: called during host controller PM callback 318 * @resume: called during host controller PM callback 319 * @dbg_register_dump: used to dump controller debug information 320 * @phy_initialization: used to initialize phys 321 * @device_reset: called to issue a reset pulse on the UFS device 322 * @config_scaling_param: called to configure clock scaling parameters 323 * @program_key: program or evict an inline encryption key 324 * @event_notify: called to notify important events 325 * @reinit_notify: called to notify reinit of UFSHCD during max gear switch 326 * @mcq_config_resource: called to configure MCQ platform resources 327 * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode 328 * @op_runtime_config: called to config Operation and runtime regs Pointers 329 * @get_outstanding_cqs: called to get outstanding completion queues 330 * @config_esi: called to config Event Specific Interrupt 331 */ 332 struct ufs_hba_variant_ops { 333 const char *name; 334 int (*init)(struct ufs_hba *); 335 void (*exit)(struct ufs_hba *); 336 u32 (*get_ufs_hci_version)(struct ufs_hba *); 337 int (*clk_scale_notify)(struct ufs_hba *, bool, 338 enum ufs_notify_change_status); 339 int (*setup_clocks)(struct ufs_hba *, bool, 340 enum ufs_notify_change_status); 341 int (*hce_enable_notify)(struct ufs_hba *, 342 enum ufs_notify_change_status); 343 int (*link_startup_notify)(struct ufs_hba *, 344 enum ufs_notify_change_status); 345 int (*pwr_change_notify)(struct ufs_hba *, 346 enum ufs_notify_change_status status, 347 struct ufs_pa_layer_attr *desired_pwr_mode, 348 struct ufs_pa_layer_attr *final_params); 349 void (*setup_xfer_req)(struct ufs_hba *hba, int tag, 350 bool is_scsi_cmd); 351 void (*setup_task_mgmt)(struct ufs_hba *, int, u8); 352 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, 353 enum ufs_notify_change_status); 354 int (*apply_dev_quirks)(struct ufs_hba *hba); 355 void (*fixup_dev_quirks)(struct ufs_hba *hba); 356 int (*suspend)(struct ufs_hba *, enum ufs_pm_op, 357 enum ufs_notify_change_status); 358 int (*resume)(struct ufs_hba *, enum ufs_pm_op); 359 void (*dbg_register_dump)(struct ufs_hba *hba); 360 int (*phy_initialization)(struct ufs_hba *); 361 int (*device_reset)(struct ufs_hba *hba); 362 void (*config_scaling_param)(struct ufs_hba *hba, 363 struct devfreq_dev_profile *profile, 364 struct devfreq_simple_ondemand_data *data); 365 int (*program_key)(struct ufs_hba *hba, 366 const union ufs_crypto_cfg_entry *cfg, int slot); 367 void (*event_notify)(struct ufs_hba *hba, 368 enum ufs_event_type evt, void *data); 369 void (*reinit_notify)(struct ufs_hba *); 370 int (*mcq_config_resource)(struct ufs_hba *hba); 371 int (*get_hba_mac)(struct ufs_hba *hba); 372 int (*op_runtime_config)(struct ufs_hba *hba); 373 int (*get_outstanding_cqs)(struct ufs_hba *hba, 374 unsigned long *ocqs); 375 int (*config_esi)(struct ufs_hba *hba); 376 }; 377 378 /* clock gating state */ 379 enum clk_gating_state { 380 CLKS_OFF, 381 CLKS_ON, 382 REQ_CLKS_OFF, 383 REQ_CLKS_ON, 384 }; 385 386 /** 387 * struct ufs_clk_gating - UFS clock gating related info 388 * @gate_work: worker to turn off clocks after some delay as specified in 389 * delay_ms 390 * @ungate_work: worker to turn on clocks that will be used in case of 391 * interrupt context 392 * @state: the current clocks state 393 * @delay_ms: gating delay in ms 394 * @is_suspended: clk gating is suspended when set to 1 which can be used 395 * during suspend/resume 396 * @delay_attr: sysfs attribute to control delay_attr 397 * @enable_attr: sysfs attribute to enable/disable clock gating 398 * @is_enabled: Indicates the current status of clock gating 399 * @is_initialized: Indicates whether clock gating is initialized or not 400 * @active_reqs: number of requests that are pending and should be waited for 401 * completion before gating clocks. 402 * @clk_gating_workq: workqueue for clock gating work. 403 */ 404 struct ufs_clk_gating { 405 struct delayed_work gate_work; 406 struct work_struct ungate_work; 407 enum clk_gating_state state; 408 unsigned long delay_ms; 409 bool is_suspended; 410 struct device_attribute delay_attr; 411 struct device_attribute enable_attr; 412 bool is_enabled; 413 bool is_initialized; 414 int active_reqs; 415 struct workqueue_struct *clk_gating_workq; 416 }; 417 418 /** 419 * struct ufs_clk_scaling - UFS clock scaling related data 420 * @active_reqs: number of requests that are pending. If this is zero when 421 * devfreq ->target() function is called then schedule "suspend_work" to 422 * suspend devfreq. 423 * @tot_busy_t: Total busy time in current polling window 424 * @window_start_t: Start time (in jiffies) of the current polling window 425 * @busy_start_t: Start time of current busy period 426 * @enable_attr: sysfs attribute to enable/disable clock scaling 427 * @saved_pwr_info: UFS power mode may also be changed during scaling and this 428 * one keeps track of previous power mode. 429 * @workq: workqueue to schedule devfreq suspend/resume work 430 * @suspend_work: worker to suspend devfreq 431 * @resume_work: worker to resume devfreq 432 * @min_gear: lowest HS gear to scale down to 433 * @is_enabled: tracks if scaling is currently enabled or not, controlled by 434 * clkscale_enable sysfs node 435 * @is_allowed: tracks if scaling is currently allowed or not, used to block 436 * clock scaling which is not invoked from devfreq governor 437 * @is_initialized: Indicates whether clock scaling is initialized or not 438 * @is_busy_started: tracks if busy period has started or not 439 * @is_suspended: tracks if devfreq is suspended or not 440 */ 441 struct ufs_clk_scaling { 442 int active_reqs; 443 unsigned long tot_busy_t; 444 ktime_t window_start_t; 445 ktime_t busy_start_t; 446 struct device_attribute enable_attr; 447 struct ufs_pa_layer_attr saved_pwr_info; 448 struct workqueue_struct *workq; 449 struct work_struct suspend_work; 450 struct work_struct resume_work; 451 u32 min_gear; 452 bool is_enabled; 453 bool is_allowed; 454 bool is_initialized; 455 bool is_busy_started; 456 bool is_suspended; 457 }; 458 459 #define UFS_EVENT_HIST_LENGTH 8 460 /** 461 * struct ufs_event_hist - keeps history of errors 462 * @pos: index to indicate cyclic buffer position 463 * @val: cyclic buffer for registers value 464 * @tstamp: cyclic buffer for time stamp 465 * @cnt: error counter 466 */ 467 struct ufs_event_hist { 468 int pos; 469 u32 val[UFS_EVENT_HIST_LENGTH]; 470 u64 tstamp[UFS_EVENT_HIST_LENGTH]; 471 unsigned long long cnt; 472 }; 473 474 /** 475 * struct ufs_stats - keeps usage/err statistics 476 * @last_intr_status: record the last interrupt status. 477 * @last_intr_ts: record the last interrupt timestamp. 478 * @hibern8_exit_cnt: Counter to keep track of number of exits, 479 * reset this after link-startup. 480 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. 481 * Clear after the first successful command completion. 482 * @event: array with event history. 483 */ 484 struct ufs_stats { 485 u32 last_intr_status; 486 u64 last_intr_ts; 487 488 u32 hibern8_exit_cnt; 489 u64 last_hibern8_exit_tstamp; 490 struct ufs_event_hist event[UFS_EVT_CNT]; 491 }; 492 493 /** 494 * enum ufshcd_state - UFS host controller state 495 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command 496 * processing. 497 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process 498 * SCSI commands. 499 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. 500 * SCSI commands may be submitted to the controller. 501 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail 502 * newly submitted SCSI commands with error code DID_BAD_TARGET. 503 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery 504 * failed. Fail all SCSI commands with error code DID_ERROR. 505 */ 506 enum ufshcd_state { 507 UFSHCD_STATE_RESET, 508 UFSHCD_STATE_OPERATIONAL, 509 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, 510 UFSHCD_STATE_EH_SCHEDULED_FATAL, 511 UFSHCD_STATE_ERROR, 512 }; 513 514 enum ufshcd_quirks { 515 /* Interrupt aggregation support is broken */ 516 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, 517 518 /* 519 * delay before each dme command is required as the unipro 520 * layer has shown instabilities 521 */ 522 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, 523 524 /* 525 * If UFS host controller is having issue in processing LCC (Line 526 * Control Command) coming from device then enable this quirk. 527 * When this quirk is enabled, host controller driver should disable 528 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 529 * attribute of device to 0). 530 */ 531 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, 532 533 /* 534 * The attribute PA_RXHSUNTERMCAP specifies whether or not the 535 * inbound Link supports unterminated line in HS mode. Setting this 536 * attribute to 1 fixes moving to HS gear. 537 */ 538 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, 539 540 /* 541 * This quirk needs to be enabled if the host controller only allows 542 * accessing the peer dme attributes in AUTO mode (FAST AUTO or 543 * SLOW AUTO). 544 */ 545 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, 546 547 /* 548 * This quirk needs to be enabled if the host controller doesn't 549 * advertise the correct version in UFS_VER register. If this quirk 550 * is enabled, standard UFS host driver will call the vendor specific 551 * ops (get_ufs_hci_version) to get the correct version. 552 */ 553 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, 554 555 /* 556 * Clear handling for transfer/task request list is just opposite. 557 */ 558 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, 559 560 /* 561 * This quirk needs to be enabled if host controller doesn't allow 562 * that the interrupt aggregation timer and counter are reset by s/w. 563 */ 564 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, 565 566 /* 567 * This quirks needs to be enabled if host controller cannot be 568 * enabled via HCE register. 569 */ 570 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, 571 572 /* 573 * This quirk needs to be enabled if the host controller regards 574 * resolution of the values of PRDTO and PRDTL in UTRD as byte. 575 */ 576 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, 577 578 /* 579 * This quirk needs to be enabled if the host controller reports 580 * OCS FATAL ERROR with device error through sense data 581 */ 582 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, 583 584 /* 585 * This quirk needs to be enabled if the host controller has 586 * auto-hibernate capability but it doesn't work. 587 */ 588 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, 589 590 /* 591 * This quirk needs to disable manual flush for write booster 592 */ 593 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, 594 595 /* 596 * This quirk needs to disable unipro timeout values 597 * before power mode change 598 */ 599 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, 600 601 /* 602 * Align DMA SG entries on a 4 KiB boundary. 603 */ 604 UFSHCD_QUIRK_4KB_DMA_ALIGNMENT = 1 << 14, 605 606 /* 607 * This quirk needs to be enabled if the host controller does not 608 * support UIC command 609 */ 610 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, 611 612 /* 613 * This quirk needs to be enabled if the host controller cannot 614 * support physical host configuration. 615 */ 616 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, 617 618 /* 619 * This quirk needs to be enabled if the host controller has 620 * 64-bit addressing supported capability but it doesn't work. 621 */ 622 UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, 623 624 /* 625 * This quirk needs to be enabled if the host controller has 626 * auto-hibernate capability but it's FASTAUTO only. 627 */ 628 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, 629 630 /* 631 * This quirk needs to be enabled if the host controller needs 632 * to reinit the device after switching to maximum gear. 633 */ 634 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, 635 636 /* 637 * Some host raises interrupt (per queue) in addition to 638 * CQES (traditional) when ESI is disabled. 639 * Enable this quirk will disable CQES and use per queue interrupt. 640 */ 641 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20, 642 643 /* 644 * Some host does not implement SQ Run Time Command (SQRTC) register 645 * thus need this quirk to skip related flow. 646 */ 647 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21, 648 }; 649 650 enum ufshcd_caps { 651 /* Allow dynamic clk gating */ 652 UFSHCD_CAP_CLK_GATING = 1 << 0, 653 654 /* Allow hiberb8 with clk gating */ 655 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, 656 657 /* Allow dynamic clk scaling */ 658 UFSHCD_CAP_CLK_SCALING = 1 << 2, 659 660 /* Allow auto bkops to enabled during runtime suspend */ 661 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, 662 663 /* 664 * This capability allows host controller driver to use the UFS HCI's 665 * interrupt aggregation capability. 666 * CAUTION: Enabling this might reduce overall UFS throughput. 667 */ 668 UFSHCD_CAP_INTR_AGGR = 1 << 4, 669 670 /* 671 * This capability allows the device auto-bkops to be always enabled 672 * except during suspend (both runtime and suspend). 673 * Enabling this capability means that device will always be allowed 674 * to do background operation when it's active but it might degrade 675 * the performance of ongoing read/write operations. 676 */ 677 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, 678 679 /* 680 * This capability allows host controller driver to automatically 681 * enable runtime power management by itself instead of waiting 682 * for userspace to control the power management. 683 */ 684 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, 685 686 /* 687 * This capability allows the host controller driver to turn-on 688 * WriteBooster, if the underlying device supports it and is 689 * provisioned to be used. This would increase the write performance. 690 */ 691 UFSHCD_CAP_WB_EN = 1 << 7, 692 693 /* 694 * This capability allows the host controller driver to use the 695 * inline crypto engine, if it is present 696 */ 697 UFSHCD_CAP_CRYPTO = 1 << 8, 698 699 /* 700 * This capability allows the controller regulators to be put into 701 * lpm mode aggressively during clock gating. 702 * This would increase power savings. 703 */ 704 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, 705 706 /* 707 * This capability allows the host controller driver to use DeepSleep, 708 * if it is supported by the UFS device. The host controller driver must 709 * support device hardware reset via the hba->device_reset() callback, 710 * in order to exit DeepSleep state. 711 */ 712 UFSHCD_CAP_DEEPSLEEP = 1 << 10, 713 714 /* 715 * This capability allows the host controller driver to use temperature 716 * notification if it is supported by the UFS device. 717 */ 718 UFSHCD_CAP_TEMP_NOTIF = 1 << 11, 719 720 /* 721 * Enable WriteBooster when scaling up the clock and disable 722 * WriteBooster when scaling the clock down. 723 */ 724 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, 725 }; 726 727 struct ufs_hba_variant_params { 728 struct devfreq_dev_profile devfreq_profile; 729 struct devfreq_simple_ondemand_data ondemand_data; 730 u16 hba_enable_delay_us; 731 u32 wb_flush_threshold; 732 }; 733 734 struct ufs_hba_monitor { 735 unsigned long chunk_size; 736 737 unsigned long nr_sec_rw[2]; 738 ktime_t total_busy[2]; 739 740 unsigned long nr_req[2]; 741 /* latencies*/ 742 ktime_t lat_sum[2]; 743 ktime_t lat_max[2]; 744 ktime_t lat_min[2]; 745 746 u32 nr_queued[2]; 747 ktime_t busy_start_ts[2]; 748 749 ktime_t enabled_ts; 750 bool enabled; 751 }; 752 753 /** 754 * struct ufshcd_res_info_t - MCQ related resource regions 755 * 756 * @name: resource name 757 * @resource: pointer to resource region 758 * @base: register base address 759 */ 760 struct ufshcd_res_info { 761 const char *name; 762 struct resource *resource; 763 void __iomem *base; 764 }; 765 766 enum ufshcd_res { 767 RES_UFS, 768 RES_MCQ, 769 RES_MCQ_SQD, 770 RES_MCQ_SQIS, 771 RES_MCQ_CQD, 772 RES_MCQ_CQIS, 773 RES_MCQ_VS, 774 RES_MAX, 775 }; 776 777 /** 778 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers 779 * 780 * @offset: Doorbell Address Offset 781 * @stride: Steps proportional to queue [0...31] 782 * @base: base address 783 */ 784 struct ufshcd_mcq_opr_info_t { 785 unsigned long offset; 786 unsigned long stride; 787 void __iomem *base; 788 }; 789 790 enum ufshcd_mcq_opr { 791 OPR_SQD, 792 OPR_SQIS, 793 OPR_CQD, 794 OPR_CQIS, 795 OPR_MAX, 796 }; 797 798 /** 799 * struct ufs_hba - per adapter private structure 800 * @mmio_base: UFSHCI base register address 801 * @ucdl_base_addr: UFS Command Descriptor base address 802 * @utrdl_base_addr: UTP Transfer Request Descriptor base address 803 * @utmrdl_base_addr: UTP Task Management Descriptor base address 804 * @ucdl_dma_addr: UFS Command Descriptor DMA address 805 * @utrdl_dma_addr: UTRDL DMA address 806 * @utmrdl_dma_addr: UTMRDL DMA address 807 * @host: Scsi_Host instance of the driver 808 * @dev: device handle 809 * @ufs_device_wlun: WLUN that controls the entire UFS device. 810 * @hwmon_device: device instance registered with the hwmon core. 811 * @curr_dev_pwr_mode: active UFS device power mode. 812 * @uic_link_state: active state of the link to the UFS device. 813 * @rpm_lvl: desired UFS power management level during runtime PM. 814 * @spm_lvl: desired UFS power management level during system PM. 815 * @pm_op_in_progress: whether or not a PM operation is in progress. 816 * @ahit: value of Auto-Hibernate Idle Timer register. 817 * @lrb: local reference block 818 * @outstanding_tasks: Bits representing outstanding task requests 819 * @outstanding_lock: Protects @outstanding_reqs. 820 * @outstanding_reqs: Bits representing outstanding transfer requests 821 * @capabilities: UFS Controller Capabilities 822 * @mcq_capabilities: UFS Multi Circular Queue capabilities 823 * @nutrs: Transfer Request Queue depth supported by controller 824 * @nutmrs: Task Management Queue depth supported by controller 825 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. 826 * @ufs_version: UFS Version to which controller complies 827 * @vops: pointer to variant specific operations 828 * @vps: pointer to variant specific parameters 829 * @priv: pointer to variant specific private data 830 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields) 831 * @irq: Irq number of the controller 832 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. 833 * @dev_ref_clk_freq: reference clock frequency 834 * @quirks: bitmask with information about deviations from the UFSHCI standard. 835 * @dev_quirks: bitmask with information about deviations from the UFS standard. 836 * @tmf_tag_set: TMF tag set. 837 * @tmf_queue: Used to allocate TMF tags. 838 * @tmf_rqs: array with pointers to TMF requests while these are in progress. 839 * @active_uic_cmd: handle of active UIC command 840 * @uic_cmd_mutex: mutex for UIC command 841 * @uic_async_done: completion used during UIC processing 842 * @ufshcd_state: UFSHCD state 843 * @eh_flags: Error handling flags 844 * @intr_mask: Interrupt Mask Bits 845 * @ee_ctrl_mask: Exception event control mask 846 * @ee_drv_mask: Exception event mask for driver 847 * @ee_usr_mask: Exception event mask for user (set via debugfs) 848 * @ee_ctrl_mutex: Used to serialize exception event information. 849 * @is_powered: flag to check if HBA is powered 850 * @shutting_down: flag to check if shutdown has been invoked 851 * @host_sem: semaphore used to serialize concurrent contexts 852 * @eh_wq: Workqueue that eh_work works on 853 * @eh_work: Worker to handle UFS errors that require s/w attention 854 * @eeh_work: Worker to handle exception events 855 * @errors: HBA errors 856 * @uic_error: UFS interconnect layer error status 857 * @saved_err: sticky error mask 858 * @saved_uic_err: sticky UIC error mask 859 * @ufs_stats: various error counters 860 * @force_reset: flag to force eh_work perform a full reset 861 * @force_pmc: flag to force a power mode change 862 * @silence_err_logs: flag to silence error logs 863 * @dev_cmd: ufs device management command information 864 * @last_dme_cmd_tstamp: time stamp of the last completed DME command 865 * @nop_out_timeout: NOP OUT timeout value 866 * @dev_info: information about the UFS device 867 * @auto_bkops_enabled: to track whether bkops is enabled in device 868 * @vreg_info: UFS device voltage regulator information 869 * @clk_list_head: UFS host controller clocks list node head 870 * @req_abort_count: number of times ufshcd_abort() has been called 871 * @lanes_per_direction: number of lanes per data direction between the UFS 872 * controller and the UFS device. 873 * @pwr_info: holds current power mode 874 * @max_pwr_info: keeps the device max valid pwm 875 * @clk_gating: information related to clock gating 876 * @caps: bitmask with information about UFS controller capabilities 877 * @devfreq: frequency scaling information owned by the devfreq core 878 * @clk_scaling: frequency scaling information owned by the UFS driver 879 * @system_suspending: system suspend has been started and system resume has 880 * not yet finished. 881 * @is_sys_suspended: UFS device has been suspended because of system suspend 882 * @urgent_bkops_lvl: keeps track of urgent bkops level for device 883 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for 884 * device is known or not. 885 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling 886 * @clk_scaling_lock: used to serialize device commands and clock scaling 887 * @desc_size: descriptor sizes reported by device 888 * @scsi_block_reqs_cnt: reference counting for scsi block requests 889 * @bsg_dev: struct device associated with the BSG queue 890 * @bsg_queue: BSG queue associated with the UFS controller 891 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power 892 * management) after the UFS device has finished a WriteBooster buffer 893 * flush or auto BKOP. 894 * @monitor: statistics about UFS commands 895 * @crypto_capabilities: Content of crypto capabilities register (0x100) 896 * @crypto_cap_array: Array of crypto capabilities 897 * @crypto_cfg_register: Start of the crypto cfg array 898 * @crypto_profile: the crypto profile of this hba (if applicable) 899 * @debugfs_root: UFS controller debugfs root directory 900 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay 901 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore 902 * ee_ctrl_mask 903 * @luns_avail: number of regular and well known LUNs supported by the UFS 904 * device 905 * @nr_hw_queues: number of hardware queues configured 906 * @nr_queues: number of Queues of different queue types 907 * @complete_put: whether or not to call ufshcd_rpm_put() from inside 908 * ufshcd_resume_complete() 909 * @ext_iid_sup: is EXT_IID is supported by UFSHC 910 * @mcq_sup: is mcq supported by UFSHC 911 * @mcq_enabled: is mcq ready to accept requests 912 * @res: array of resource info of MCQ registers 913 * @mcq_base: Multi circular queue registers base address 914 * @uhq: array of supported hardware queues 915 * @dev_cmd_queue: Queue for issuing device management commands 916 */ 917 struct ufs_hba { 918 void __iomem *mmio_base; 919 920 /* Virtual memory reference */ 921 struct utp_transfer_cmd_desc *ucdl_base_addr; 922 struct utp_transfer_req_desc *utrdl_base_addr; 923 struct utp_task_req_desc *utmrdl_base_addr; 924 925 /* DMA memory reference */ 926 dma_addr_t ucdl_dma_addr; 927 dma_addr_t utrdl_dma_addr; 928 dma_addr_t utmrdl_dma_addr; 929 930 struct Scsi_Host *host; 931 struct device *dev; 932 struct scsi_device *ufs_device_wlun; 933 934 #ifdef CONFIG_SCSI_UFS_HWMON 935 struct device *hwmon_device; 936 #endif 937 938 enum ufs_dev_pwr_mode curr_dev_pwr_mode; 939 enum uic_link_state uic_link_state; 940 /* Desired UFS power management level during runtime PM */ 941 enum ufs_pm_level rpm_lvl; 942 /* Desired UFS power management level during system PM */ 943 enum ufs_pm_level spm_lvl; 944 int pm_op_in_progress; 945 946 /* Auto-Hibernate Idle Timer register value */ 947 u32 ahit; 948 949 struct ufshcd_lrb *lrb; 950 951 unsigned long outstanding_tasks; 952 spinlock_t outstanding_lock; 953 unsigned long outstanding_reqs; 954 955 u32 capabilities; 956 int nutrs; 957 u32 mcq_capabilities; 958 int nutmrs; 959 u32 reserved_slot; 960 u32 ufs_version; 961 const struct ufs_hba_variant_ops *vops; 962 struct ufs_hba_variant_params *vps; 963 void *priv; 964 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 965 size_t sg_entry_size; 966 #endif 967 unsigned int irq; 968 bool is_irq_enabled; 969 enum ufs_ref_clk_freq dev_ref_clk_freq; 970 971 unsigned int quirks; /* Deviations from standard UFSHCI spec. */ 972 973 /* Device deviations from standard UFS device spec. */ 974 unsigned int dev_quirks; 975 976 struct blk_mq_tag_set tmf_tag_set; 977 struct request_queue *tmf_queue; 978 struct request **tmf_rqs; 979 980 struct uic_command *active_uic_cmd; 981 struct mutex uic_cmd_mutex; 982 struct completion *uic_async_done; 983 984 enum ufshcd_state ufshcd_state; 985 u32 eh_flags; 986 u32 intr_mask; 987 u16 ee_ctrl_mask; 988 u16 ee_drv_mask; 989 u16 ee_usr_mask; 990 struct mutex ee_ctrl_mutex; 991 bool is_powered; 992 bool shutting_down; 993 struct semaphore host_sem; 994 995 /* Work Queues */ 996 struct workqueue_struct *eh_wq; 997 struct work_struct eh_work; 998 struct work_struct eeh_work; 999 1000 /* HBA Errors */ 1001 u32 errors; 1002 u32 uic_error; 1003 u32 saved_err; 1004 u32 saved_uic_err; 1005 struct ufs_stats ufs_stats; 1006 bool force_reset; 1007 bool force_pmc; 1008 bool silence_err_logs; 1009 1010 /* Device management request data */ 1011 struct ufs_dev_cmd dev_cmd; 1012 ktime_t last_dme_cmd_tstamp; 1013 int nop_out_timeout; 1014 1015 /* Keeps information of the UFS device connected to this host */ 1016 struct ufs_dev_info dev_info; 1017 bool auto_bkops_enabled; 1018 struct ufs_vreg_info vreg_info; 1019 struct list_head clk_list_head; 1020 1021 /* Number of requests aborts */ 1022 int req_abort_count; 1023 1024 /* Number of lanes available (1 or 2) for Rx/Tx */ 1025 u32 lanes_per_direction; 1026 struct ufs_pa_layer_attr pwr_info; 1027 struct ufs_pwr_mode_info max_pwr_info; 1028 1029 struct ufs_clk_gating clk_gating; 1030 /* Control to enable/disable host capabilities */ 1031 u32 caps; 1032 1033 struct devfreq *devfreq; 1034 struct ufs_clk_scaling clk_scaling; 1035 bool system_suspending; 1036 bool is_sys_suspended; 1037 1038 enum bkops_status urgent_bkops_lvl; 1039 bool is_urgent_bkops_lvl_checked; 1040 1041 struct mutex wb_mutex; 1042 struct rw_semaphore clk_scaling_lock; 1043 atomic_t scsi_block_reqs_cnt; 1044 1045 struct device bsg_dev; 1046 struct request_queue *bsg_queue; 1047 struct delayed_work rpm_dev_flush_recheck_work; 1048 1049 struct ufs_hba_monitor monitor; 1050 1051 #ifdef CONFIG_SCSI_UFS_CRYPTO 1052 union ufs_crypto_capabilities crypto_capabilities; 1053 union ufs_crypto_cap_entry *crypto_cap_array; 1054 u32 crypto_cfg_register; 1055 struct blk_crypto_profile crypto_profile; 1056 #endif 1057 #ifdef CONFIG_DEBUG_FS 1058 struct dentry *debugfs_root; 1059 struct delayed_work debugfs_ee_work; 1060 u32 debugfs_ee_rate_limit_ms; 1061 #endif 1062 u32 luns_avail; 1063 unsigned int nr_hw_queues; 1064 unsigned int nr_queues[HCTX_MAX_TYPES]; 1065 bool complete_put; 1066 bool ext_iid_sup; 1067 bool scsi_host_added; 1068 bool mcq_sup; 1069 bool lsdb_sup; 1070 bool mcq_enabled; 1071 struct ufshcd_res_info res[RES_MAX]; 1072 void __iomem *mcq_base; 1073 struct ufs_hw_queue *uhq; 1074 struct ufs_hw_queue *dev_cmd_queue; 1075 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX]; 1076 }; 1077 1078 /** 1079 * struct ufs_hw_queue - per hardware queue structure 1080 * @mcq_sq_head: base address of submission queue head pointer 1081 * @mcq_sq_tail: base address of submission queue tail pointer 1082 * @mcq_cq_head: base address of completion queue head pointer 1083 * @mcq_cq_tail: base address of completion queue tail pointer 1084 * @sqe_base_addr: submission queue entry base address 1085 * @sqe_dma_addr: submission queue dma address 1086 * @cqe_base_addr: completion queue base address 1087 * @cqe_dma_addr: completion queue dma address 1088 * @max_entries: max number of slots in this hardware queue 1089 * @id: hardware queue ID 1090 * @sq_tp_slot: current slot to which SQ tail pointer is pointing 1091 * @sq_lock: serialize submission queue access 1092 * @cq_tail_slot: current slot to which CQ tail pointer is pointing 1093 * @cq_head_slot: current slot to which CQ head pointer is pointing 1094 * @cq_lock: Synchronize between multiple polling instances 1095 * @sq_mutex: prevent submission queue concurrent access 1096 */ 1097 struct ufs_hw_queue { 1098 void __iomem *mcq_sq_head; 1099 void __iomem *mcq_sq_tail; 1100 void __iomem *mcq_cq_head; 1101 void __iomem *mcq_cq_tail; 1102 1103 struct utp_transfer_req_desc *sqe_base_addr; 1104 dma_addr_t sqe_dma_addr; 1105 struct cq_entry *cqe_base_addr; 1106 dma_addr_t cqe_dma_addr; 1107 u32 max_entries; 1108 u32 id; 1109 u32 sq_tail_slot; 1110 spinlock_t sq_lock; 1111 u32 cq_tail_slot; 1112 u32 cq_head_slot; 1113 spinlock_t cq_lock; 1114 /* prevent concurrent access to submission queue */ 1115 struct mutex sq_mutex; 1116 }; 1117 1118 static inline bool is_mcq_enabled(struct ufs_hba *hba) 1119 { 1120 return hba->mcq_enabled; 1121 } 1122 1123 static inline unsigned int ufshcd_mcq_opr_offset(struct ufs_hba *hba, 1124 enum ufshcd_mcq_opr opr, int idx) 1125 { 1126 return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx; 1127 } 1128 1129 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 1130 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1131 { 1132 return hba->sg_entry_size; 1133 } 1134 1135 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size) 1136 { 1137 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry)); 1138 hba->sg_entry_size = sg_entry_size; 1139 } 1140 #else 1141 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1142 { 1143 return sizeof(struct ufshcd_sg_entry); 1144 } 1145 1146 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \ 1147 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) 1148 #endif 1149 1150 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba) 1151 { 1152 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); 1153 } 1154 1155 /* Returns true if clocks can be gated. Otherwise false */ 1156 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) 1157 { 1158 return hba->caps & UFSHCD_CAP_CLK_GATING; 1159 } 1160 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) 1161 { 1162 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1163 } 1164 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) 1165 { 1166 return hba->caps & UFSHCD_CAP_CLK_SCALING; 1167 } 1168 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) 1169 { 1170 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1171 } 1172 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) 1173 { 1174 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; 1175 } 1176 1177 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) 1178 { 1179 return (hba->caps & UFSHCD_CAP_INTR_AGGR) && 1180 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); 1181 } 1182 1183 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) 1184 { 1185 return !!(ufshcd_is_link_hibern8(hba) && 1186 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); 1187 } 1188 1189 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) 1190 { 1191 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && 1192 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); 1193 } 1194 1195 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) 1196 { 1197 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); 1198 } 1199 1200 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) 1201 { 1202 return hba->caps & UFSHCD_CAP_WB_EN; 1203 } 1204 1205 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) 1206 { 1207 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; 1208 } 1209 1210 #define ufsmcq_writel(hba, val, reg) \ 1211 writel((val), (hba)->mcq_base + (reg)) 1212 #define ufsmcq_readl(hba, reg) \ 1213 readl((hba)->mcq_base + (reg)) 1214 1215 #define ufsmcq_writelx(hba, val, reg) \ 1216 writel_relaxed((val), (hba)->mcq_base + (reg)) 1217 #define ufsmcq_readlx(hba, reg) \ 1218 readl_relaxed((hba)->mcq_base + (reg)) 1219 1220 #define ufshcd_writel(hba, val, reg) \ 1221 writel((val), (hba)->mmio_base + (reg)) 1222 #define ufshcd_readl(hba, reg) \ 1223 readl((hba)->mmio_base + (reg)) 1224 1225 /** 1226 * ufshcd_rmwl - perform read/modify/write for a controller register 1227 * @hba: per adapter instance 1228 * @mask: mask to apply on read value 1229 * @val: actual value to write 1230 * @reg: register address 1231 */ 1232 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) 1233 { 1234 u32 tmp; 1235 1236 tmp = ufshcd_readl(hba, reg); 1237 tmp &= ~mask; 1238 tmp |= (val & mask); 1239 ufshcd_writel(hba, tmp, reg); 1240 } 1241 1242 int ufshcd_alloc_host(struct device *, struct ufs_hba **); 1243 void ufshcd_dealloc_host(struct ufs_hba *); 1244 int ufshcd_hba_enable(struct ufs_hba *hba); 1245 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); 1246 int ufshcd_link_recovery(struct ufs_hba *hba); 1247 int ufshcd_make_hba_operational(struct ufs_hba *hba); 1248 void ufshcd_remove(struct ufs_hba *); 1249 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); 1250 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); 1251 void ufshcd_delay_us(unsigned long us, unsigned long tolerance); 1252 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); 1253 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); 1254 void ufshcd_hba_stop(struct ufs_hba *hba); 1255 void ufshcd_schedule_eh_work(struct ufs_hba *hba); 1256 void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); 1257 u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); 1258 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); 1259 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, 1260 struct ufs_hw_queue *hwq); 1261 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); 1262 void ufshcd_mcq_enable_esi(struct ufs_hba *hba); 1263 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); 1264 1265 /** 1266 * ufshcd_set_variant - set variant specific data to the hba 1267 * @hba: per adapter instance 1268 * @variant: pointer to variant specific data 1269 */ 1270 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) 1271 { 1272 BUG_ON(!hba); 1273 hba->priv = variant; 1274 } 1275 1276 /** 1277 * ufshcd_get_variant - get variant specific data from the hba 1278 * @hba: per adapter instance 1279 */ 1280 static inline void *ufshcd_get_variant(struct ufs_hba *hba) 1281 { 1282 BUG_ON(!hba); 1283 return hba->priv; 1284 } 1285 1286 #ifdef CONFIG_PM 1287 extern int ufshcd_runtime_suspend(struct device *dev); 1288 extern int ufshcd_runtime_resume(struct device *dev); 1289 #endif 1290 #ifdef CONFIG_PM_SLEEP 1291 extern int ufshcd_system_suspend(struct device *dev); 1292 extern int ufshcd_system_resume(struct device *dev); 1293 extern int ufshcd_system_freeze(struct device *dev); 1294 extern int ufshcd_system_thaw(struct device *dev); 1295 extern int ufshcd_system_restore(struct device *dev); 1296 #endif 1297 1298 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 1299 int agreed_gear, 1300 int adapt_val); 1301 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 1302 u8 attr_set, u32 mib_val, u8 peer); 1303 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 1304 u32 *mib_val, u8 peer); 1305 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, 1306 struct ufs_pa_layer_attr *desired_pwr_mode); 1307 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); 1308 1309 /* UIC command interfaces for DME primitives */ 1310 #define DME_LOCAL 0 1311 #define DME_PEER 1 1312 #define ATTR_SET_NOR 0 /* NORMAL */ 1313 #define ATTR_SET_ST 1 /* STATIC */ 1314 1315 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 1316 u32 mib_val) 1317 { 1318 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1319 mib_val, DME_LOCAL); 1320 } 1321 1322 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, 1323 u32 mib_val) 1324 { 1325 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1326 mib_val, DME_LOCAL); 1327 } 1328 1329 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 1330 u32 mib_val) 1331 { 1332 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1333 mib_val, DME_PEER); 1334 } 1335 1336 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, 1337 u32 mib_val) 1338 { 1339 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1340 mib_val, DME_PEER); 1341 } 1342 1343 static inline int ufshcd_dme_get(struct ufs_hba *hba, 1344 u32 attr_sel, u32 *mib_val) 1345 { 1346 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 1347 } 1348 1349 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 1350 u32 attr_sel, u32 *mib_val) 1351 { 1352 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 1353 } 1354 1355 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) 1356 { 1357 return (pwr_info->pwr_rx == FAST_MODE || 1358 pwr_info->pwr_rx == FASTAUTO_MODE) && 1359 (pwr_info->pwr_tx == FAST_MODE || 1360 pwr_info->pwr_tx == FASTAUTO_MODE); 1361 } 1362 1363 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) 1364 { 1365 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); 1366 } 1367 1368 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba); 1369 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); 1370 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 1371 const struct ufs_dev_quirk *fixups); 1372 #define SD_ASCII_STD true 1373 #define SD_RAW false 1374 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 1375 u8 **buf, bool ascii); 1376 1377 void ufshcd_hold(struct ufs_hba *hba); 1378 void ufshcd_release(struct ufs_hba *hba); 1379 1380 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); 1381 1382 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); 1383 1384 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); 1385 1386 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); 1387 1388 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 1389 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, 1390 struct ufs_ehs *ehs_rsp, int sg_cnt, 1391 struct scatterlist *sg_list, enum dma_data_direction dir); 1392 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); 1393 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); 1394 int ufshcd_suspend_prepare(struct device *dev); 1395 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); 1396 void ufshcd_resume_complete(struct device *dev); 1397 bool ufshcd_is_hba_active(struct ufs_hba *hba); 1398 1399 /* Wrapper functions for safely calling variant operations */ 1400 static inline int ufshcd_vops_init(struct ufs_hba *hba) 1401 { 1402 if (hba->vops && hba->vops->init) 1403 return hba->vops->init(hba); 1404 1405 return 0; 1406 } 1407 1408 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) 1409 { 1410 if (hba->vops && hba->vops->phy_initialization) 1411 return hba->vops->phy_initialization(hba); 1412 1413 return 0; 1414 } 1415 1416 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; 1417 1418 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1419 const char *prefix); 1420 1421 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); 1422 int ufshcd_write_ee_control(struct ufs_hba *hba); 1423 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 1424 const u16 *other_mask, u16 set, u16 clr); 1425 1426 #endif /* End of Header */ 1427