1dd11376bSBart Van Assche /* SPDX-License-Identifier: GPL-2.0-or-later */ 2dd11376bSBart Van Assche /* 3dd11376bSBart Van Assche * Universal Flash Storage Host controller driver 4dd11376bSBart Van Assche * Copyright (C) 2011-2013 Samsung India Software Operations 5dd11376bSBart Van Assche * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6dd11376bSBart Van Assche * 7dd11376bSBart Van Assche * Authors: 8dd11376bSBart Van Assche * Santosh Yaraganavi <santosh.sy@samsung.com> 9dd11376bSBart Van Assche * Vinayak Holikatti <h.vinayak@samsung.com> 10dd11376bSBart Van Assche */ 11dd11376bSBart Van Assche 12dd11376bSBart Van Assche #ifndef _UFSHCD_H 13dd11376bSBart Van Assche #define _UFSHCD_H 14dd11376bSBart Van Assche 15dd11376bSBart Van Assche #include <linux/bitfield.h> 16dd11376bSBart Van Assche #include <linux/blk-crypto-profile.h> 17dd11376bSBart Van Assche #include <linux/blk-mq.h> 18dd11376bSBart Van Assche #include <linux/devfreq.h> 19*e02288e0SCan Guo #include <linux/msi.h> 20dd11376bSBart Van Assche #include <linux/pm_runtime.h> 21f3e57da5SBean Huo #include <linux/dma-direction.h> 22dd11376bSBart Van Assche #include <scsi/scsi_device.h> 23dd11376bSBart Van Assche #include <ufs/unipro.h> 24dd11376bSBart Van Assche #include <ufs/ufs.h> 25dd11376bSBart Van Assche #include <ufs/ufs_quirks.h> 26dd11376bSBart Van Assche #include <ufs/ufshci.h> 27dd11376bSBart Van Assche 28dd11376bSBart Van Assche #define UFSHCD "ufshcd" 29dd11376bSBart Van Assche 30dd11376bSBart Van Assche struct ufs_hba; 31dd11376bSBart Van Assche 32dd11376bSBart Van Assche enum dev_cmd_type { 33dd11376bSBart Van Assche DEV_CMD_TYPE_NOP = 0x0, 34dd11376bSBart Van Assche DEV_CMD_TYPE_QUERY = 0x1, 356ff265fcSBean Huo DEV_CMD_TYPE_RPMB = 0x2, 36dd11376bSBart Van Assche }; 37dd11376bSBart Van Assche 38dd11376bSBart Van Assche enum ufs_event_type { 39dd11376bSBart Van Assche /* uic specific errors */ 40dd11376bSBart Van Assche UFS_EVT_PA_ERR = 0, 41dd11376bSBart Van Assche UFS_EVT_DL_ERR, 42dd11376bSBart Van Assche UFS_EVT_NL_ERR, 43dd11376bSBart Van Assche UFS_EVT_TL_ERR, 44dd11376bSBart Van Assche UFS_EVT_DME_ERR, 45dd11376bSBart Van Assche 46dd11376bSBart Van Assche /* fatal errors */ 47dd11376bSBart Van Assche UFS_EVT_AUTO_HIBERN8_ERR, 48dd11376bSBart Van Assche UFS_EVT_FATAL_ERR, 49dd11376bSBart Van Assche UFS_EVT_LINK_STARTUP_FAIL, 50dd11376bSBart Van Assche UFS_EVT_RESUME_ERR, 51dd11376bSBart Van Assche UFS_EVT_SUSPEND_ERR, 52dd11376bSBart Van Assche UFS_EVT_WL_SUSP_ERR, 53dd11376bSBart Van Assche UFS_EVT_WL_RES_ERR, 54dd11376bSBart Van Assche 55dd11376bSBart Van Assche /* abnormal events */ 56dd11376bSBart Van Assche UFS_EVT_DEV_RESET, 57dd11376bSBart Van Assche UFS_EVT_HOST_RESET, 58dd11376bSBart Van Assche UFS_EVT_ABORT, 59dd11376bSBart Van Assche 60dd11376bSBart Van Assche UFS_EVT_CNT, 61dd11376bSBart Van Assche }; 62dd11376bSBart Van Assche 63dd11376bSBart Van Assche /** 64dd11376bSBart Van Assche * struct uic_command - UIC command structure 65dd11376bSBart Van Assche * @command: UIC command 66dd11376bSBart Van Assche * @argument1: UIC command argument 1 67dd11376bSBart Van Assche * @argument2: UIC command argument 2 68dd11376bSBart Van Assche * @argument3: UIC command argument 3 69dd11376bSBart Van Assche * @cmd_active: Indicate if UIC command is outstanding 70dd11376bSBart Van Assche * @done: UIC command completion 71dd11376bSBart Van Assche */ 72dd11376bSBart Van Assche struct uic_command { 73dd11376bSBart Van Assche u32 command; 74dd11376bSBart Van Assche u32 argument1; 75dd11376bSBart Van Assche u32 argument2; 76dd11376bSBart Van Assche u32 argument3; 77dd11376bSBart Van Assche int cmd_active; 78dd11376bSBart Van Assche struct completion done; 79dd11376bSBart Van Assche }; 80dd11376bSBart Van Assche 81dd11376bSBart Van Assche /* Used to differentiate the power management options */ 82dd11376bSBart Van Assche enum ufs_pm_op { 83dd11376bSBart Van Assche UFS_RUNTIME_PM, 84dd11376bSBart Van Assche UFS_SYSTEM_PM, 85dd11376bSBart Van Assche UFS_SHUTDOWN_PM, 86dd11376bSBart Van Assche }; 87dd11376bSBart Van Assche 88dd11376bSBart Van Assche /* Host <-> Device UniPro Link state */ 89dd11376bSBart Van Assche enum uic_link_state { 90dd11376bSBart Van Assche UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 91dd11376bSBart Van Assche UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 92dd11376bSBart Van Assche UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 93dd11376bSBart Van Assche UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ 94dd11376bSBart Van Assche }; 95dd11376bSBart Van Assche 96dd11376bSBart Van Assche #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) 97dd11376bSBart Van Assche #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ 98dd11376bSBart Van Assche UIC_LINK_ACTIVE_STATE) 99dd11376bSBart Van Assche #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ 100dd11376bSBart Van Assche UIC_LINK_HIBERN8_STATE) 101dd11376bSBart Van Assche #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ 102dd11376bSBart Van Assche UIC_LINK_BROKEN_STATE) 103dd11376bSBart Van Assche #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) 104dd11376bSBart Van Assche #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ 105dd11376bSBart Van Assche UIC_LINK_ACTIVE_STATE) 106dd11376bSBart Van Assche #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ 107dd11376bSBart Van Assche UIC_LINK_HIBERN8_STATE) 108dd11376bSBart Van Assche #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ 109dd11376bSBart Van Assche UIC_LINK_BROKEN_STATE) 110dd11376bSBart Van Assche 111dd11376bSBart Van Assche #define ufshcd_set_ufs_dev_active(h) \ 112dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) 113dd11376bSBart Van Assche #define ufshcd_set_ufs_dev_sleep(h) \ 114dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) 115dd11376bSBart Van Assche #define ufshcd_set_ufs_dev_poweroff(h) \ 116dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) 117dd11376bSBart Van Assche #define ufshcd_set_ufs_dev_deepsleep(h) \ 118dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) 119dd11376bSBart Van Assche #define ufshcd_is_ufs_dev_active(h) \ 120dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) 121dd11376bSBart Van Assche #define ufshcd_is_ufs_dev_sleep(h) \ 122dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) 123dd11376bSBart Van Assche #define ufshcd_is_ufs_dev_poweroff(h) \ 124dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) 125dd11376bSBart Van Assche #define ufshcd_is_ufs_dev_deepsleep(h) \ 126dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) 127dd11376bSBart Van Assche 128dd11376bSBart Van Assche /* 129dd11376bSBart Van Assche * UFS Power management levels. 130dd11376bSBart Van Assche * Each level is in increasing order of power savings, except DeepSleep 131dd11376bSBart Van Assche * which is lower than PowerDown with power on but not PowerDown with 132dd11376bSBart Van Assche * power off. 133dd11376bSBart Van Assche */ 134dd11376bSBart Van Assche enum ufs_pm_level { 135dd11376bSBart Van Assche UFS_PM_LVL_0, 136dd11376bSBart Van Assche UFS_PM_LVL_1, 137dd11376bSBart Van Assche UFS_PM_LVL_2, 138dd11376bSBart Van Assche UFS_PM_LVL_3, 139dd11376bSBart Van Assche UFS_PM_LVL_4, 140dd11376bSBart Van Assche UFS_PM_LVL_5, 141dd11376bSBart Van Assche UFS_PM_LVL_6, 142dd11376bSBart Van Assche UFS_PM_LVL_MAX 143dd11376bSBart Van Assche }; 144dd11376bSBart Van Assche 145dd11376bSBart Van Assche struct ufs_pm_lvl_states { 146dd11376bSBart Van Assche enum ufs_dev_pwr_mode dev_state; 147dd11376bSBart Van Assche enum uic_link_state link_state; 148dd11376bSBart Van Assche }; 149dd11376bSBart Van Assche 150dd11376bSBart Van Assche /** 151dd11376bSBart Van Assche * struct ufshcd_lrb - local reference block 152dd11376bSBart Van Assche * @utr_descriptor_ptr: UTRD address of the command 153dd11376bSBart Van Assche * @ucd_req_ptr: UCD address of the command 154dd11376bSBart Van Assche * @ucd_rsp_ptr: Response UPIU address for this command 155dd11376bSBart Van Assche * @ucd_prdt_ptr: PRDT address of the command 156dd11376bSBart Van Assche * @utrd_dma_addr: UTRD dma address for debug 157dd11376bSBart Van Assche * @ucd_prdt_dma_addr: PRDT dma address for debug 158dd11376bSBart Van Assche * @ucd_rsp_dma_addr: UPIU response dma address for debug 159dd11376bSBart Van Assche * @ucd_req_dma_addr: UPIU request dma address for debug 160dd11376bSBart Van Assche * @cmd: pointer to SCSI command 161dd11376bSBart Van Assche * @scsi_status: SCSI status of the command 162dd11376bSBart Van Assche * @command_type: SCSI, UFS, Query. 163dd11376bSBart Van Assche * @task_tag: Task tag of the command 164dd11376bSBart Van Assche * @lun: LUN of the command 165dd11376bSBart Van Assche * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) 1660f85e747SDaniil Lunev * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) 1670f85e747SDaniil Lunev * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) 1680f85e747SDaniil Lunev * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) 1690f85e747SDaniil Lunev * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) 170dd11376bSBart Van Assche * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) 171dd11376bSBart Van Assche * @data_unit_num: the data unit number for the first block for inline crypto 172dd11376bSBart Van Assche * @req_abort_skip: skip request abort task flag 173dd11376bSBart Van Assche */ 174dd11376bSBart Van Assche struct ufshcd_lrb { 175dd11376bSBart Van Assche struct utp_transfer_req_desc *utr_descriptor_ptr; 176dd11376bSBart Van Assche struct utp_upiu_req *ucd_req_ptr; 177dd11376bSBart Van Assche struct utp_upiu_rsp *ucd_rsp_ptr; 178dd11376bSBart Van Assche struct ufshcd_sg_entry *ucd_prdt_ptr; 179dd11376bSBart Van Assche 180dd11376bSBart Van Assche dma_addr_t utrd_dma_addr; 181dd11376bSBart Van Assche dma_addr_t ucd_req_dma_addr; 182dd11376bSBart Van Assche dma_addr_t ucd_rsp_dma_addr; 183dd11376bSBart Van Assche dma_addr_t ucd_prdt_dma_addr; 184dd11376bSBart Van Assche 185dd11376bSBart Van Assche struct scsi_cmnd *cmd; 186dd11376bSBart Van Assche int scsi_status; 187dd11376bSBart Van Assche 188dd11376bSBart Van Assche int command_type; 189dd11376bSBart Van Assche int task_tag; 190dd11376bSBart Van Assche u8 lun; /* UPIU LUN id field is only 8-bit wide */ 191dd11376bSBart Van Assche bool intr_cmd; 192dd11376bSBart Van Assche ktime_t issue_time_stamp; 1930f85e747SDaniil Lunev u64 issue_time_stamp_local_clock; 194dd11376bSBart Van Assche ktime_t compl_time_stamp; 1950f85e747SDaniil Lunev u64 compl_time_stamp_local_clock; 196dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_CRYPTO 197dd11376bSBart Van Assche int crypto_key_slot; 198dd11376bSBart Van Assche u64 data_unit_num; 199dd11376bSBart Van Assche #endif 200dd11376bSBart Van Assche 201dd11376bSBart Van Assche bool req_abort_skip; 202dd11376bSBart Van Assche }; 203dd11376bSBart Van Assche 204dd11376bSBart Van Assche /** 205dd11376bSBart Van Assche * struct ufs_query - holds relevant data structures for query request 206dd11376bSBart Van Assche * @request: request upiu and function 207dd11376bSBart Van Assche * @descriptor: buffer for sending/receiving descriptor 208dd11376bSBart Van Assche * @response: response upiu and response 209dd11376bSBart Van Assche */ 210dd11376bSBart Van Assche struct ufs_query { 211dd11376bSBart Van Assche struct ufs_query_req request; 212dd11376bSBart Van Assche u8 *descriptor; 213dd11376bSBart Van Assche struct ufs_query_res response; 214dd11376bSBart Van Assche }; 215dd11376bSBart Van Assche 216dd11376bSBart Van Assche /** 217dd11376bSBart Van Assche * struct ufs_dev_cmd - all assosiated fields with device management commands 218dd11376bSBart Van Assche * @type: device management command type - Query, NOP OUT 219dd11376bSBart Van Assche * @lock: lock to allow one command at a time 220dd11376bSBart Van Assche * @complete: internal commands completion 221dd11376bSBart Van Assche * @query: Device management query information 222dd11376bSBart Van Assche */ 223dd11376bSBart Van Assche struct ufs_dev_cmd { 224dd11376bSBart Van Assche enum dev_cmd_type type; 225dd11376bSBart Van Assche struct mutex lock; 226dd11376bSBart Van Assche struct completion *complete; 227dd11376bSBart Van Assche struct ufs_query query; 22822a2d563SAsutosh Das struct cq_entry *cqe; 229dd11376bSBart Van Assche }; 230dd11376bSBart Van Assche 231dd11376bSBart Van Assche /** 232dd11376bSBart Van Assche * struct ufs_clk_info - UFS clock related info 233dd11376bSBart Van Assche * @list: list headed by hba->clk_list_head 234dd11376bSBart Van Assche * @clk: clock node 235dd11376bSBart Van Assche * @name: clock name 236dd11376bSBart Van Assche * @max_freq: maximum frequency supported by the clock 237dd11376bSBart Van Assche * @min_freq: min frequency that can be used for clock scaling 238dd11376bSBart Van Assche * @curr_freq: indicates the current frequency that it is set to 239dd11376bSBart Van Assche * @keep_link_active: indicates that the clk should not be disabled if 240dd11376bSBart Van Assche * link is active 241dd11376bSBart Van Assche * @enabled: variable to check against multiple enable/disable 242dd11376bSBart Van Assche */ 243dd11376bSBart Van Assche struct ufs_clk_info { 244dd11376bSBart Van Assche struct list_head list; 245dd11376bSBart Van Assche struct clk *clk; 246dd11376bSBart Van Assche const char *name; 247dd11376bSBart Van Assche u32 max_freq; 248dd11376bSBart Van Assche u32 min_freq; 249dd11376bSBart Van Assche u32 curr_freq; 250dd11376bSBart Van Assche bool keep_link_active; 251dd11376bSBart Van Assche bool enabled; 252dd11376bSBart Van Assche }; 253dd11376bSBart Van Assche 254dd11376bSBart Van Assche enum ufs_notify_change_status { 255dd11376bSBart Van Assche PRE_CHANGE, 256dd11376bSBart Van Assche POST_CHANGE, 257dd11376bSBart Van Assche }; 258dd11376bSBart Van Assche 259dd11376bSBart Van Assche struct ufs_pa_layer_attr { 260dd11376bSBart Van Assche u32 gear_rx; 261dd11376bSBart Van Assche u32 gear_tx; 262dd11376bSBart Van Assche u32 lane_rx; 263dd11376bSBart Van Assche u32 lane_tx; 264dd11376bSBart Van Assche u32 pwr_rx; 265dd11376bSBart Van Assche u32 pwr_tx; 266dd11376bSBart Van Assche u32 hs_rate; 267dd11376bSBart Van Assche }; 268dd11376bSBart Van Assche 269dd11376bSBart Van Assche struct ufs_pwr_mode_info { 270dd11376bSBart Van Assche bool is_valid; 271dd11376bSBart Van Assche struct ufs_pa_layer_attr info; 272dd11376bSBart Van Assche }; 273dd11376bSBart Van Assche 274dd11376bSBart Van Assche /** 275dd11376bSBart Van Assche * struct ufs_hba_variant_ops - variant specific callbacks 276dd11376bSBart Van Assche * @name: variant name 277dd11376bSBart Van Assche * @init: called when the driver is initialized 278dd11376bSBart Van Assche * @exit: called to cleanup everything done in init 279dd11376bSBart Van Assche * @get_ufs_hci_version: called to get UFS HCI version 280dd11376bSBart Van Assche * @clk_scale_notify: notifies that clks are scaled up/down 281dd11376bSBart Van Assche * @setup_clocks: called before touching any of the controller registers 282dd11376bSBart Van Assche * @hce_enable_notify: called before and after HCE enable bit is set to allow 283dd11376bSBart Van Assche * variant specific Uni-Pro initialization. 284dd11376bSBart Van Assche * @link_startup_notify: called before and after Link startup is carried out 285dd11376bSBart Van Assche * to allow variant specific Uni-Pro initialization. 286dd11376bSBart Van Assche * @pwr_change_notify: called before and after a power mode change 287dd11376bSBart Van Assche * is carried out to allow vendor spesific capabilities 288dd11376bSBart Van Assche * to be set. 289dd11376bSBart Van Assche * @setup_xfer_req: called before any transfer request is issued 290dd11376bSBart Van Assche * to set some things 291dd11376bSBart Van Assche * @setup_task_mgmt: called before any task management request is issued 292dd11376bSBart Van Assche * to set some things 293dd11376bSBart Van Assche * @hibern8_notify: called around hibern8 enter/exit 294dd11376bSBart Van Assche * @apply_dev_quirks: called to apply device specific quirks 295dd11376bSBart Van Assche * @fixup_dev_quirks: called to modify device specific quirks 296dd11376bSBart Van Assche * @suspend: called during host controller PM callback 297dd11376bSBart Van Assche * @resume: called during host controller PM callback 298dd11376bSBart Van Assche * @dbg_register_dump: used to dump controller debug information 299dd11376bSBart Van Assche * @phy_initialization: used to initialize phys 300dd11376bSBart Van Assche * @device_reset: called to issue a reset pulse on the UFS device 301dd11376bSBart Van Assche * @config_scaling_param: called to configure clock scaling parameters 302dd11376bSBart Van Assche * @program_key: program or evict an inline encryption key 303dd11376bSBart Van Assche * @event_notify: called to notify important events 304c2c38c57SManivannan Sadhasivam * @reinit_notify: called to notify reinit of UFSHCD during max gear switch 305c263b4efSAsutosh Das * @mcq_config_resource: called to configure MCQ platform resources 3067224c806SAsutosh Das * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode 3072468da61SAsutosh Das * @op_runtime_config: called to config Operation and runtime regs Pointers 308f87b2c41SAsutosh Das * @get_outstanding_cqs: called to get outstanding completion queues 309edb0db05SCan Guo * @config_esi: called to config Event Specific Interrupt 310dd11376bSBart Van Assche */ 311dd11376bSBart Van Assche struct ufs_hba_variant_ops { 312dd11376bSBart Van Assche const char *name; 313dd11376bSBart Van Assche int (*init)(struct ufs_hba *); 314dd11376bSBart Van Assche void (*exit)(struct ufs_hba *); 315dd11376bSBart Van Assche u32 (*get_ufs_hci_version)(struct ufs_hba *); 316dd11376bSBart Van Assche int (*clk_scale_notify)(struct ufs_hba *, bool, 317dd11376bSBart Van Assche enum ufs_notify_change_status); 318dd11376bSBart Van Assche int (*setup_clocks)(struct ufs_hba *, bool, 319dd11376bSBart Van Assche enum ufs_notify_change_status); 320dd11376bSBart Van Assche int (*hce_enable_notify)(struct ufs_hba *, 321dd11376bSBart Van Assche enum ufs_notify_change_status); 322dd11376bSBart Van Assche int (*link_startup_notify)(struct ufs_hba *, 323dd11376bSBart Van Assche enum ufs_notify_change_status); 324dd11376bSBart Van Assche int (*pwr_change_notify)(struct ufs_hba *, 325dd11376bSBart Van Assche enum ufs_notify_change_status status, 326dd11376bSBart Van Assche struct ufs_pa_layer_attr *, 327dd11376bSBart Van Assche struct ufs_pa_layer_attr *); 328dd11376bSBart Van Assche void (*setup_xfer_req)(struct ufs_hba *hba, int tag, 329dd11376bSBart Van Assche bool is_scsi_cmd); 330dd11376bSBart Van Assche void (*setup_task_mgmt)(struct ufs_hba *, int, u8); 331dd11376bSBart Van Assche void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, 332dd11376bSBart Van Assche enum ufs_notify_change_status); 333dd11376bSBart Van Assche int (*apply_dev_quirks)(struct ufs_hba *hba); 334dd11376bSBart Van Assche void (*fixup_dev_quirks)(struct ufs_hba *hba); 335dd11376bSBart Van Assche int (*suspend)(struct ufs_hba *, enum ufs_pm_op, 336dd11376bSBart Van Assche enum ufs_notify_change_status); 337dd11376bSBart Van Assche int (*resume)(struct ufs_hba *, enum ufs_pm_op); 338dd11376bSBart Van Assche void (*dbg_register_dump)(struct ufs_hba *hba); 339dd11376bSBart Van Assche int (*phy_initialization)(struct ufs_hba *); 340dd11376bSBart Van Assche int (*device_reset)(struct ufs_hba *hba); 341dd11376bSBart Van Assche void (*config_scaling_param)(struct ufs_hba *hba, 342dd11376bSBart Van Assche struct devfreq_dev_profile *profile, 343dd11376bSBart Van Assche struct devfreq_simple_ondemand_data *data); 344dd11376bSBart Van Assche int (*program_key)(struct ufs_hba *hba, 345dd11376bSBart Van Assche const union ufs_crypto_cfg_entry *cfg, int slot); 346dd11376bSBart Van Assche void (*event_notify)(struct ufs_hba *hba, 347dd11376bSBart Van Assche enum ufs_event_type evt, void *data); 348c2c38c57SManivannan Sadhasivam void (*reinit_notify)(struct ufs_hba *); 349c263b4efSAsutosh Das int (*mcq_config_resource)(struct ufs_hba *hba); 3507224c806SAsutosh Das int (*get_hba_mac)(struct ufs_hba *hba); 3512468da61SAsutosh Das int (*op_runtime_config)(struct ufs_hba *hba); 352f87b2c41SAsutosh Das int (*get_outstanding_cqs)(struct ufs_hba *hba, 353f87b2c41SAsutosh Das unsigned long *ocqs); 354edb0db05SCan Guo int (*config_esi)(struct ufs_hba *hba); 355dd11376bSBart Van Assche }; 356dd11376bSBart Van Assche 357dd11376bSBart Van Assche /* clock gating state */ 358dd11376bSBart Van Assche enum clk_gating_state { 359dd11376bSBart Van Assche CLKS_OFF, 360dd11376bSBart Van Assche CLKS_ON, 361dd11376bSBart Van Assche REQ_CLKS_OFF, 362dd11376bSBart Van Assche REQ_CLKS_ON, 363dd11376bSBart Van Assche }; 364dd11376bSBart Van Assche 365dd11376bSBart Van Assche /** 366dd11376bSBart Van Assche * struct ufs_clk_gating - UFS clock gating related info 367dd11376bSBart Van Assche * @gate_work: worker to turn off clocks after some delay as specified in 368dd11376bSBart Van Assche * delay_ms 369dd11376bSBart Van Assche * @ungate_work: worker to turn on clocks that will be used in case of 370dd11376bSBart Van Assche * interrupt context 371dd11376bSBart Van Assche * @state: the current clocks state 372dd11376bSBart Van Assche * @delay_ms: gating delay in ms 373dd11376bSBart Van Assche * @is_suspended: clk gating is suspended when set to 1 which can be used 374dd11376bSBart Van Assche * during suspend/resume 375dd11376bSBart Van Assche * @delay_attr: sysfs attribute to control delay_attr 376dd11376bSBart Van Assche * @enable_attr: sysfs attribute to enable/disable clock gating 377dd11376bSBart Van Assche * @is_enabled: Indicates the current status of clock gating 378dd11376bSBart Van Assche * @is_initialized: Indicates whether clock gating is initialized or not 379dd11376bSBart Van Assche * @active_reqs: number of requests that are pending and should be waited for 380dd11376bSBart Van Assche * completion before gating clocks. 381dd11376bSBart Van Assche * @clk_gating_workq: workqueue for clock gating work. 382dd11376bSBart Van Assche */ 383dd11376bSBart Van Assche struct ufs_clk_gating { 384dd11376bSBart Van Assche struct delayed_work gate_work; 385dd11376bSBart Van Assche struct work_struct ungate_work; 386dd11376bSBart Van Assche enum clk_gating_state state; 387dd11376bSBart Van Assche unsigned long delay_ms; 388dd11376bSBart Van Assche bool is_suspended; 389dd11376bSBart Van Assche struct device_attribute delay_attr; 390dd11376bSBart Van Assche struct device_attribute enable_attr; 391dd11376bSBart Van Assche bool is_enabled; 392dd11376bSBart Van Assche bool is_initialized; 393dd11376bSBart Van Assche int active_reqs; 394dd11376bSBart Van Assche struct workqueue_struct *clk_gating_workq; 395dd11376bSBart Van Assche }; 396dd11376bSBart Van Assche 397dd11376bSBart Van Assche struct ufs_saved_pwr_info { 398dd11376bSBart Van Assche struct ufs_pa_layer_attr info; 399dd11376bSBart Van Assche bool is_valid; 400dd11376bSBart Van Assche }; 401dd11376bSBart Van Assche 402dd11376bSBart Van Assche /** 403dd11376bSBart Van Assche * struct ufs_clk_scaling - UFS clock scaling related data 404dd11376bSBart Van Assche * @active_reqs: number of requests that are pending. If this is zero when 405dd11376bSBart Van Assche * devfreq ->target() function is called then schedule "suspend_work" to 406dd11376bSBart Van Assche * suspend devfreq. 407dd11376bSBart Van Assche * @tot_busy_t: Total busy time in current polling window 408dd11376bSBart Van Assche * @window_start_t: Start time (in jiffies) of the current polling window 409dd11376bSBart Van Assche * @busy_start_t: Start time of current busy period 410dd11376bSBart Van Assche * @enable_attr: sysfs attribute to enable/disable clock scaling 411dd11376bSBart Van Assche * @saved_pwr_info: UFS power mode may also be changed during scaling and this 412dd11376bSBart Van Assche * one keeps track of previous power mode. 413dd11376bSBart Van Assche * @workq: workqueue to schedule devfreq suspend/resume work 414dd11376bSBart Van Assche * @suspend_work: worker to suspend devfreq 415dd11376bSBart Van Assche * @resume_work: worker to resume devfreq 416dd11376bSBart Van Assche * @min_gear: lowest HS gear to scale down to 417dd11376bSBart Van Assche * @is_enabled: tracks if scaling is currently enabled or not, controlled by 418dd11376bSBart Van Assche * clkscale_enable sysfs node 419dd11376bSBart Van Assche * @is_allowed: tracks if scaling is currently allowed or not, used to block 420dd11376bSBart Van Assche * clock scaling which is not invoked from devfreq governor 421dd11376bSBart Van Assche * @is_initialized: Indicates whether clock scaling is initialized or not 422dd11376bSBart Van Assche * @is_busy_started: tracks if busy period has started or not 423dd11376bSBart Van Assche * @is_suspended: tracks if devfreq is suspended or not 424dd11376bSBart Van Assche */ 425dd11376bSBart Van Assche struct ufs_clk_scaling { 426dd11376bSBart Van Assche int active_reqs; 427dd11376bSBart Van Assche unsigned long tot_busy_t; 428dd11376bSBart Van Assche ktime_t window_start_t; 429dd11376bSBart Van Assche ktime_t busy_start_t; 430dd11376bSBart Van Assche struct device_attribute enable_attr; 431dd11376bSBart Van Assche struct ufs_saved_pwr_info saved_pwr_info; 432dd11376bSBart Van Assche struct workqueue_struct *workq; 433dd11376bSBart Van Assche struct work_struct suspend_work; 434dd11376bSBart Van Assche struct work_struct resume_work; 435dd11376bSBart Van Assche u32 min_gear; 436dd11376bSBart Van Assche bool is_enabled; 437dd11376bSBart Van Assche bool is_allowed; 438dd11376bSBart Van Assche bool is_initialized; 439dd11376bSBart Van Assche bool is_busy_started; 440dd11376bSBart Van Assche bool is_suspended; 441dd11376bSBart Van Assche }; 442dd11376bSBart Van Assche 443dd11376bSBart Van Assche #define UFS_EVENT_HIST_LENGTH 8 444dd11376bSBart Van Assche /** 445dd11376bSBart Van Assche * struct ufs_event_hist - keeps history of errors 446dd11376bSBart Van Assche * @pos: index to indicate cyclic buffer position 447dd11376bSBart Van Assche * @val: cyclic buffer for registers value 448dd11376bSBart Van Assche * @tstamp: cyclic buffer for time stamp 449dd11376bSBart Van Assche * @cnt: error counter 450dd11376bSBart Van Assche */ 451dd11376bSBart Van Assche struct ufs_event_hist { 452dd11376bSBart Van Assche int pos; 453dd11376bSBart Van Assche u32 val[UFS_EVENT_HIST_LENGTH]; 4540f85e747SDaniil Lunev u64 tstamp[UFS_EVENT_HIST_LENGTH]; 455dd11376bSBart Van Assche unsigned long long cnt; 456dd11376bSBart Van Assche }; 457dd11376bSBart Van Assche 458dd11376bSBart Van Assche /** 459dd11376bSBart Van Assche * struct ufs_stats - keeps usage/err statistics 460dd11376bSBart Van Assche * @last_intr_status: record the last interrupt status. 461dd11376bSBart Van Assche * @last_intr_ts: record the last interrupt timestamp. 462dd11376bSBart Van Assche * @hibern8_exit_cnt: Counter to keep track of number of exits, 463dd11376bSBart Van Assche * reset this after link-startup. 464dd11376bSBart Van Assche * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. 465dd11376bSBart Van Assche * Clear after the first successful command completion. 466dd11376bSBart Van Assche * @event: array with event history. 467dd11376bSBart Van Assche */ 468dd11376bSBart Van Assche struct ufs_stats { 469dd11376bSBart Van Assche u32 last_intr_status; 4700f85e747SDaniil Lunev u64 last_intr_ts; 471dd11376bSBart Van Assche 472dd11376bSBart Van Assche u32 hibern8_exit_cnt; 4730f85e747SDaniil Lunev u64 last_hibern8_exit_tstamp; 474dd11376bSBart Van Assche struct ufs_event_hist event[UFS_EVT_CNT]; 475dd11376bSBart Van Assche }; 476dd11376bSBart Van Assche 477dd11376bSBart Van Assche /** 478dd11376bSBart Van Assche * enum ufshcd_state - UFS host controller state 479dd11376bSBart Van Assche * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command 480dd11376bSBart Van Assche * processing. 481dd11376bSBart Van Assche * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process 482dd11376bSBart Van Assche * SCSI commands. 483dd11376bSBart Van Assche * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. 484dd11376bSBart Van Assche * SCSI commands may be submitted to the controller. 485dd11376bSBart Van Assche * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail 486dd11376bSBart Van Assche * newly submitted SCSI commands with error code DID_BAD_TARGET. 487dd11376bSBart Van Assche * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery 488dd11376bSBart Van Assche * failed. Fail all SCSI commands with error code DID_ERROR. 489dd11376bSBart Van Assche */ 490dd11376bSBart Van Assche enum ufshcd_state { 491dd11376bSBart Van Assche UFSHCD_STATE_RESET, 492dd11376bSBart Van Assche UFSHCD_STATE_OPERATIONAL, 493dd11376bSBart Van Assche UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, 494dd11376bSBart Van Assche UFSHCD_STATE_EH_SCHEDULED_FATAL, 495dd11376bSBart Van Assche UFSHCD_STATE_ERROR, 496dd11376bSBart Van Assche }; 497dd11376bSBart Van Assche 498dd11376bSBart Van Assche enum ufshcd_quirks { 499dd11376bSBart Van Assche /* Interrupt aggregation support is broken */ 500dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, 501dd11376bSBart Van Assche 502dd11376bSBart Van Assche /* 503dd11376bSBart Van Assche * delay before each dme command is required as the unipro 504dd11376bSBart Van Assche * layer has shown instabilities 505dd11376bSBart Van Assche */ 506dd11376bSBart Van Assche UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, 507dd11376bSBart Van Assche 508dd11376bSBart Van Assche /* 509dd11376bSBart Van Assche * If UFS host controller is having issue in processing LCC (Line 510dd11376bSBart Van Assche * Control Command) coming from device then enable this quirk. 511dd11376bSBart Van Assche * When this quirk is enabled, host controller driver should disable 512dd11376bSBart Van Assche * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 513dd11376bSBart Van Assche * attribute of device to 0). 514dd11376bSBart Van Assche */ 515dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, 516dd11376bSBart Van Assche 517dd11376bSBart Van Assche /* 518dd11376bSBart Van Assche * The attribute PA_RXHSUNTERMCAP specifies whether or not the 519dd11376bSBart Van Assche * inbound Link supports unterminated line in HS mode. Setting this 520dd11376bSBart Van Assche * attribute to 1 fixes moving to HS gear. 521dd11376bSBart Van Assche */ 522dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, 523dd11376bSBart Van Assche 524dd11376bSBart Van Assche /* 525dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller only allows 526dd11376bSBart Van Assche * accessing the peer dme attributes in AUTO mode (FAST AUTO or 527dd11376bSBart Van Assche * SLOW AUTO). 528dd11376bSBart Van Assche */ 529dd11376bSBart Van Assche UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, 530dd11376bSBart Van Assche 531dd11376bSBart Van Assche /* 532dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller doesn't 533dd11376bSBart Van Assche * advertise the correct version in UFS_VER register. If this quirk 534dd11376bSBart Van Assche * is enabled, standard UFS host driver will call the vendor specific 535dd11376bSBart Van Assche * ops (get_ufs_hci_version) to get the correct version. 536dd11376bSBart Van Assche */ 537dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, 538dd11376bSBart Van Assche 539dd11376bSBart Van Assche /* 540dd11376bSBart Van Assche * Clear handling for transfer/task request list is just opposite. 541dd11376bSBart Van Assche */ 542dd11376bSBart Van Assche UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, 543dd11376bSBart Van Assche 544dd11376bSBart Van Assche /* 545dd11376bSBart Van Assche * This quirk needs to be enabled if host controller doesn't allow 546dd11376bSBart Van Assche * that the interrupt aggregation timer and counter are reset by s/w. 547dd11376bSBart Van Assche */ 548dd11376bSBart Van Assche UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, 549dd11376bSBart Van Assche 550dd11376bSBart Van Assche /* 551dd11376bSBart Van Assche * This quirks needs to be enabled if host controller cannot be 552dd11376bSBart Van Assche * enabled via HCE register. 553dd11376bSBart Van Assche */ 554dd11376bSBart Van Assche UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, 555dd11376bSBart Van Assche 556dd11376bSBart Van Assche /* 557dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller regards 558dd11376bSBart Van Assche * resolution of the values of PRDTO and PRDTL in UTRD as byte. 559dd11376bSBart Van Assche */ 560dd11376bSBart Van Assche UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, 561dd11376bSBart Van Assche 562dd11376bSBart Van Assche /* 563dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller reports 564dd11376bSBart Van Assche * OCS FATAL ERROR with device error through sense data 565dd11376bSBart Van Assche */ 566dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, 567dd11376bSBart Van Assche 568dd11376bSBart Van Assche /* 569dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller has 570dd11376bSBart Van Assche * auto-hibernate capability but it doesn't work. 571dd11376bSBart Van Assche */ 572dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, 573dd11376bSBart Van Assche 574dd11376bSBart Van Assche /* 575dd11376bSBart Van Assche * This quirk needs to disable manual flush for write booster 576dd11376bSBart Van Assche */ 577dd11376bSBart Van Assche UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, 578dd11376bSBart Van Assche 579dd11376bSBart Van Assche /* 580dd11376bSBart Van Assche * This quirk needs to disable unipro timeout values 581dd11376bSBart Van Assche * before power mode change 582dd11376bSBart Van Assche */ 583dd11376bSBart Van Assche UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, 584dd11376bSBart Van Assche 585dd11376bSBart Van Assche /* 586dd11376bSBart Van Assche * This quirk allows only sg entries aligned with page size. 587dd11376bSBart Van Assche */ 588dd11376bSBart Van Assche UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE = 1 << 14, 589dd11376bSBart Van Assche 590dd11376bSBart Van Assche /* 591dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller does not 592dd11376bSBart Van Assche * support UIC command 593dd11376bSBart Van Assche */ 594dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, 595dd11376bSBart Van Assche 596dd11376bSBart Van Assche /* 597dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller cannot 598dd11376bSBart Van Assche * support physical host configuration. 599dd11376bSBart Van Assche */ 600dd11376bSBart Van Assche UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, 6016554400dSYoshihiro Shimoda 6026554400dSYoshihiro Shimoda /* 6036554400dSYoshihiro Shimoda * This quirk needs to be enabled if the host controller has 6046554400dSYoshihiro Shimoda * 64-bit addressing supported capability but it doesn't work. 6056554400dSYoshihiro Shimoda */ 6066554400dSYoshihiro Shimoda UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, 6072f11bbc2SYoshihiro Shimoda 6082f11bbc2SYoshihiro Shimoda /* 6092f11bbc2SYoshihiro Shimoda * This quirk needs to be enabled if the host controller has 6102f11bbc2SYoshihiro Shimoda * auto-hibernate capability but it's FASTAUTO only. 6112f11bbc2SYoshihiro Shimoda */ 6122f11bbc2SYoshihiro Shimoda UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, 61396a7141dSManivannan Sadhasivam 61496a7141dSManivannan Sadhasivam /* 61596a7141dSManivannan Sadhasivam * This quirk needs to be enabled if the host controller needs 61696a7141dSManivannan Sadhasivam * to reinit the device after switching to maximum gear. 61796a7141dSManivannan Sadhasivam */ 61896a7141dSManivannan Sadhasivam UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, 619dd11376bSBart Van Assche }; 620dd11376bSBart Van Assche 621dd11376bSBart Van Assche enum ufshcd_caps { 622dd11376bSBart Van Assche /* Allow dynamic clk gating */ 623dd11376bSBart Van Assche UFSHCD_CAP_CLK_GATING = 1 << 0, 624dd11376bSBart Van Assche 625dd11376bSBart Van Assche /* Allow hiberb8 with clk gating */ 626dd11376bSBart Van Assche UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, 627dd11376bSBart Van Assche 628dd11376bSBart Van Assche /* Allow dynamic clk scaling */ 629dd11376bSBart Van Assche UFSHCD_CAP_CLK_SCALING = 1 << 2, 630dd11376bSBart Van Assche 631dd11376bSBart Van Assche /* Allow auto bkops to enabled during runtime suspend */ 632dd11376bSBart Van Assche UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, 633dd11376bSBart Van Assche 634dd11376bSBart Van Assche /* 635dd11376bSBart Van Assche * This capability allows host controller driver to use the UFS HCI's 636dd11376bSBart Van Assche * interrupt aggregation capability. 637dd11376bSBart Van Assche * CAUTION: Enabling this might reduce overall UFS throughput. 638dd11376bSBart Van Assche */ 639dd11376bSBart Van Assche UFSHCD_CAP_INTR_AGGR = 1 << 4, 640dd11376bSBart Van Assche 641dd11376bSBart Van Assche /* 642dd11376bSBart Van Assche * This capability allows the device auto-bkops to be always enabled 643dd11376bSBart Van Assche * except during suspend (both runtime and suspend). 644dd11376bSBart Van Assche * Enabling this capability means that device will always be allowed 645dd11376bSBart Van Assche * to do background operation when it's active but it might degrade 646dd11376bSBart Van Assche * the performance of ongoing read/write operations. 647dd11376bSBart Van Assche */ 648dd11376bSBart Van Assche UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, 649dd11376bSBart Van Assche 650dd11376bSBart Van Assche /* 651dd11376bSBart Van Assche * This capability allows host controller driver to automatically 652dd11376bSBart Van Assche * enable runtime power management by itself instead of waiting 653dd11376bSBart Van Assche * for userspace to control the power management. 654dd11376bSBart Van Assche */ 655dd11376bSBart Van Assche UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, 656dd11376bSBart Van Assche 657dd11376bSBart Van Assche /* 658dd11376bSBart Van Assche * This capability allows the host controller driver to turn-on 659dd11376bSBart Van Assche * WriteBooster, if the underlying device supports it and is 660dd11376bSBart Van Assche * provisioned to be used. This would increase the write performance. 661dd11376bSBart Van Assche */ 662dd11376bSBart Van Assche UFSHCD_CAP_WB_EN = 1 << 7, 663dd11376bSBart Van Assche 664dd11376bSBart Van Assche /* 665dd11376bSBart Van Assche * This capability allows the host controller driver to use the 666dd11376bSBart Van Assche * inline crypto engine, if it is present 667dd11376bSBart Van Assche */ 668dd11376bSBart Van Assche UFSHCD_CAP_CRYPTO = 1 << 8, 669dd11376bSBart Van Assche 670dd11376bSBart Van Assche /* 671dd11376bSBart Van Assche * This capability allows the controller regulators to be put into 672dd11376bSBart Van Assche * lpm mode aggressively during clock gating. 673dd11376bSBart Van Assche * This would increase power savings. 674dd11376bSBart Van Assche */ 675dd11376bSBart Van Assche UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, 676dd11376bSBart Van Assche 677dd11376bSBart Van Assche /* 678dd11376bSBart Van Assche * This capability allows the host controller driver to use DeepSleep, 679dd11376bSBart Van Assche * if it is supported by the UFS device. The host controller driver must 680dd11376bSBart Van Assche * support device hardware reset via the hba->device_reset() callback, 681dd11376bSBart Van Assche * in order to exit DeepSleep state. 682dd11376bSBart Van Assche */ 683dd11376bSBart Van Assche UFSHCD_CAP_DEEPSLEEP = 1 << 10, 684dd11376bSBart Van Assche 685dd11376bSBart Van Assche /* 686dd11376bSBart Van Assche * This capability allows the host controller driver to use temperature 687dd11376bSBart Van Assche * notification if it is supported by the UFS device. 688dd11376bSBart Van Assche */ 689dd11376bSBart Van Assche UFSHCD_CAP_TEMP_NOTIF = 1 << 11, 69087bd0501SPeter Wang 69187bd0501SPeter Wang /* 69287bd0501SPeter Wang * Enable WriteBooster when scaling up the clock and disable 69387bd0501SPeter Wang * WriteBooster when scaling the clock down. 69487bd0501SPeter Wang */ 69587bd0501SPeter Wang UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, 696dd11376bSBart Van Assche }; 697dd11376bSBart Van Assche 698dd11376bSBart Van Assche struct ufs_hba_variant_params { 699dd11376bSBart Van Assche struct devfreq_dev_profile devfreq_profile; 700dd11376bSBart Van Assche struct devfreq_simple_ondemand_data ondemand_data; 701dd11376bSBart Van Assche u16 hba_enable_delay_us; 702dd11376bSBart Van Assche u32 wb_flush_threshold; 703dd11376bSBart Van Assche }; 704dd11376bSBart Van Assche 705dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_HPB 706dd11376bSBart Van Assche /** 707dd11376bSBart Van Assche * struct ufshpb_dev_info - UFSHPB device related info 708dd11376bSBart Van Assche * @num_lu: the number of user logical unit to check whether all lu finished 709dd11376bSBart Van Assche * initialization 710dd11376bSBart Van Assche * @rgn_size: device reported HPB region size 711dd11376bSBart Van Assche * @srgn_size: device reported HPB sub-region size 712dd11376bSBart Van Assche * @slave_conf_cnt: counter to check all lu finished initialization 713dd11376bSBart Van Assche * @hpb_disabled: flag to check if HPB is disabled 714dd11376bSBart Van Assche * @max_hpb_single_cmd: device reported bMAX_DATA_SIZE_FOR_SINGLE_CMD value 715dd11376bSBart Van Assche * @is_legacy: flag to check HPB 1.0 716dd11376bSBart Van Assche * @control_mode: either host or device 717dd11376bSBart Van Assche */ 718dd11376bSBart Van Assche struct ufshpb_dev_info { 719dd11376bSBart Van Assche int num_lu; 720dd11376bSBart Van Assche int rgn_size; 721dd11376bSBart Van Assche int srgn_size; 722dd11376bSBart Van Assche atomic_t slave_conf_cnt; 723dd11376bSBart Van Assche bool hpb_disabled; 724dd11376bSBart Van Assche u8 max_hpb_single_cmd; 725dd11376bSBart Van Assche bool is_legacy; 726dd11376bSBart Van Assche u8 control_mode; 727dd11376bSBart Van Assche }; 728dd11376bSBart Van Assche #endif 729dd11376bSBart Van Assche 730dd11376bSBart Van Assche struct ufs_hba_monitor { 731dd11376bSBart Van Assche unsigned long chunk_size; 732dd11376bSBart Van Assche 733dd11376bSBart Van Assche unsigned long nr_sec_rw[2]; 734dd11376bSBart Van Assche ktime_t total_busy[2]; 735dd11376bSBart Van Assche 736dd11376bSBart Van Assche unsigned long nr_req[2]; 737dd11376bSBart Van Assche /* latencies*/ 738dd11376bSBart Van Assche ktime_t lat_sum[2]; 739dd11376bSBart Van Assche ktime_t lat_max[2]; 740dd11376bSBart Van Assche ktime_t lat_min[2]; 741dd11376bSBart Van Assche 742dd11376bSBart Van Assche u32 nr_queued[2]; 743dd11376bSBart Van Assche ktime_t busy_start_ts[2]; 744dd11376bSBart Van Assche 745dd11376bSBart Van Assche ktime_t enabled_ts; 746dd11376bSBart Van Assche bool enabled; 747dd11376bSBart Van Assche }; 748dd11376bSBart Van Assche 749dd11376bSBart Van Assche /** 750c263b4efSAsutosh Das * struct ufshcd_res_info_t - MCQ related resource regions 751c263b4efSAsutosh Das * 752c263b4efSAsutosh Das * @name: resource name 753c263b4efSAsutosh Das * @resource: pointer to resource region 754c263b4efSAsutosh Das * @base: register base address 755c263b4efSAsutosh Das */ 756c263b4efSAsutosh Das struct ufshcd_res_info { 757c263b4efSAsutosh Das const char *name; 758c263b4efSAsutosh Das struct resource *resource; 759c263b4efSAsutosh Das void __iomem *base; 760c263b4efSAsutosh Das }; 761c263b4efSAsutosh Das 762c263b4efSAsutosh Das enum ufshcd_res { 763c263b4efSAsutosh Das RES_UFS, 764c263b4efSAsutosh Das RES_MCQ, 765c263b4efSAsutosh Das RES_MCQ_SQD, 766c263b4efSAsutosh Das RES_MCQ_SQIS, 767c263b4efSAsutosh Das RES_MCQ_CQD, 768c263b4efSAsutosh Das RES_MCQ_CQIS, 769c263b4efSAsutosh Das RES_MCQ_VS, 770c263b4efSAsutosh Das RES_MAX, 771c263b4efSAsutosh Das }; 772c263b4efSAsutosh Das 773c263b4efSAsutosh Das /** 7742468da61SAsutosh Das * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers 7752468da61SAsutosh Das * 7762468da61SAsutosh Das * @offset: Doorbell Address Offset 7772468da61SAsutosh Das * @stride: Steps proportional to queue [0...31] 7782468da61SAsutosh Das * @base: base address 7792468da61SAsutosh Das */ 7802468da61SAsutosh Das struct ufshcd_mcq_opr_info_t { 7812468da61SAsutosh Das unsigned long offset; 7822468da61SAsutosh Das unsigned long stride; 7832468da61SAsutosh Das void __iomem *base; 7842468da61SAsutosh Das }; 7852468da61SAsutosh Das 7862468da61SAsutosh Das enum ufshcd_mcq_opr { 7872468da61SAsutosh Das OPR_SQD, 7882468da61SAsutosh Das OPR_SQIS, 7892468da61SAsutosh Das OPR_CQD, 7902468da61SAsutosh Das OPR_CQIS, 7912468da61SAsutosh Das OPR_MAX, 7922468da61SAsutosh Das }; 7932468da61SAsutosh Das 7942468da61SAsutosh Das /** 795dd11376bSBart Van Assche * struct ufs_hba - per adapter private structure 796dd11376bSBart Van Assche * @mmio_base: UFSHCI base register address 797dd11376bSBart Van Assche * @ucdl_base_addr: UFS Command Descriptor base address 798dd11376bSBart Van Assche * @utrdl_base_addr: UTP Transfer Request Descriptor base address 799dd11376bSBart Van Assche * @utmrdl_base_addr: UTP Task Management Descriptor base address 800dd11376bSBart Van Assche * @ucdl_dma_addr: UFS Command Descriptor DMA address 801dd11376bSBart Van Assche * @utrdl_dma_addr: UTRDL DMA address 802dd11376bSBart Van Assche * @utmrdl_dma_addr: UTMRDL DMA address 803dd11376bSBart Van Assche * @host: Scsi_Host instance of the driver 804dd11376bSBart Van Assche * @dev: device handle 805dd11376bSBart Van Assche * @ufs_device_wlun: WLUN that controls the entire UFS device. 806dd11376bSBart Van Assche * @hwmon_device: device instance registered with the hwmon core. 807dd11376bSBart Van Assche * @curr_dev_pwr_mode: active UFS device power mode. 808dd11376bSBart Van Assche * @uic_link_state: active state of the link to the UFS device. 809dd11376bSBart Van Assche * @rpm_lvl: desired UFS power management level during runtime PM. 810dd11376bSBart Van Assche * @spm_lvl: desired UFS power management level during system PM. 811dd11376bSBart Van Assche * @pm_op_in_progress: whether or not a PM operation is in progress. 812dd11376bSBart Van Assche * @ahit: value of Auto-Hibernate Idle Timer register. 813dd11376bSBart Van Assche * @lrb: local reference block 814dd11376bSBart Van Assche * @outstanding_tasks: Bits representing outstanding task requests 815dd11376bSBart Van Assche * @outstanding_lock: Protects @outstanding_reqs. 816dd11376bSBart Van Assche * @outstanding_reqs: Bits representing outstanding transfer requests 817dd11376bSBart Van Assche * @capabilities: UFS Controller Capabilities 8186e1d850aSAsutosh Das * @mcq_capabilities: UFS Multi Circular Queue capabilities 819dd11376bSBart Van Assche * @nutrs: Transfer Request Queue depth supported by controller 820dd11376bSBart Van Assche * @nutmrs: Task Management Queue depth supported by controller 821dd11376bSBart Van Assche * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. 822dd11376bSBart Van Assche * @ufs_version: UFS Version to which controller complies 823dd11376bSBart Van Assche * @vops: pointer to variant specific operations 824dd11376bSBart Van Assche * @vps: pointer to variant specific parameters 825dd11376bSBart Van Assche * @priv: pointer to variant specific private data 826ada1e653SEric Biggers * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields) 827dd11376bSBart Van Assche * @irq: Irq number of the controller 828dd11376bSBart Van Assche * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. 829dd11376bSBart Van Assche * @dev_ref_clk_freq: reference clock frequency 830dd11376bSBart Van Assche * @quirks: bitmask with information about deviations from the UFSHCI standard. 831dd11376bSBart Van Assche * @dev_quirks: bitmask with information about deviations from the UFS standard. 832dd11376bSBart Van Assche * @tmf_tag_set: TMF tag set. 833dd11376bSBart Van Assche * @tmf_queue: Used to allocate TMF tags. 834dd11376bSBart Van Assche * @tmf_rqs: array with pointers to TMF requests while these are in progress. 835dd11376bSBart Van Assche * @active_uic_cmd: handle of active UIC command 836dd11376bSBart Van Assche * @uic_cmd_mutex: mutex for UIC command 837dd11376bSBart Van Assche * @uic_async_done: completion used during UIC processing 838dd11376bSBart Van Assche * @ufshcd_state: UFSHCD state 839dd11376bSBart Van Assche * @eh_flags: Error handling flags 840dd11376bSBart Van Assche * @intr_mask: Interrupt Mask Bits 841dd11376bSBart Van Assche * @ee_ctrl_mask: Exception event control mask 842dd11376bSBart Van Assche * @ee_drv_mask: Exception event mask for driver 843dd11376bSBart Van Assche * @ee_usr_mask: Exception event mask for user (set via debugfs) 844dd11376bSBart Van Assche * @ee_ctrl_mutex: Used to serialize exception event information. 845dd11376bSBart Van Assche * @is_powered: flag to check if HBA is powered 846dd11376bSBart Van Assche * @shutting_down: flag to check if shutdown has been invoked 847dd11376bSBart Van Assche * @host_sem: semaphore used to serialize concurrent contexts 848dd11376bSBart Van Assche * @eh_wq: Workqueue that eh_work works on 849dd11376bSBart Van Assche * @eh_work: Worker to handle UFS errors that require s/w attention 850dd11376bSBart Van Assche * @eeh_work: Worker to handle exception events 851dd11376bSBart Van Assche * @errors: HBA errors 852dd11376bSBart Van Assche * @uic_error: UFS interconnect layer error status 853dd11376bSBart Van Assche * @saved_err: sticky error mask 854dd11376bSBart Van Assche * @saved_uic_err: sticky UIC error mask 855dd11376bSBart Van Assche * @ufs_stats: various error counters 856dd11376bSBart Van Assche * @force_reset: flag to force eh_work perform a full reset 857dd11376bSBart Van Assche * @force_pmc: flag to force a power mode change 858dd11376bSBart Van Assche * @silence_err_logs: flag to silence error logs 859dd11376bSBart Van Assche * @dev_cmd: ufs device management command information 860dd11376bSBart Van Assche * @last_dme_cmd_tstamp: time stamp of the last completed DME command 861dd11376bSBart Van Assche * @nop_out_timeout: NOP OUT timeout value 862dd11376bSBart Van Assche * @dev_info: information about the UFS device 863dd11376bSBart Van Assche * @auto_bkops_enabled: to track whether bkops is enabled in device 864dd11376bSBart Van Assche * @vreg_info: UFS device voltage regulator information 865dd11376bSBart Van Assche * @clk_list_head: UFS host controller clocks list node head 866dd11376bSBart Van Assche * @req_abort_count: number of times ufshcd_abort() has been called 867dd11376bSBart Van Assche * @lanes_per_direction: number of lanes per data direction between the UFS 868dd11376bSBart Van Assche * controller and the UFS device. 869dd11376bSBart Van Assche * @pwr_info: holds current power mode 870dd11376bSBart Van Assche * @max_pwr_info: keeps the device max valid pwm 871dd11376bSBart Van Assche * @clk_gating: information related to clock gating 872dd11376bSBart Van Assche * @caps: bitmask with information about UFS controller capabilities 873dd11376bSBart Van Assche * @devfreq: frequency scaling information owned by the devfreq core 874dd11376bSBart Van Assche * @clk_scaling: frequency scaling information owned by the UFS driver 8751a547cbcSBart Van Assche * @system_suspending: system suspend has been started and system resume has 8761a547cbcSBart Van Assche * not yet finished. 8771a547cbcSBart Van Assche * @is_sys_suspended: UFS device has been suspended because of system suspend 878dd11376bSBart Van Assche * @urgent_bkops_lvl: keeps track of urgent bkops level for device 879dd11376bSBart Van Assche * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for 880dd11376bSBart Van Assche * device is known or not. 881dd11376bSBart Van Assche * @clk_scaling_lock: used to serialize device commands and clock scaling 882dd11376bSBart Van Assche * @desc_size: descriptor sizes reported by device 883dd11376bSBart Van Assche * @scsi_block_reqs_cnt: reference counting for scsi block requests 884dd11376bSBart Van Assche * @bsg_dev: struct device associated with the BSG queue 885dd11376bSBart Van Assche * @bsg_queue: BSG queue associated with the UFS controller 886dd11376bSBart Van Assche * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power 887dd11376bSBart Van Assche * management) after the UFS device has finished a WriteBooster buffer 888dd11376bSBart Van Assche * flush or auto BKOP. 889dd11376bSBart Van Assche * @ufshpb_dev: information related to HPB (Host Performance Booster). 890dd11376bSBart Van Assche * @monitor: statistics about UFS commands 891dd11376bSBart Van Assche * @crypto_capabilities: Content of crypto capabilities register (0x100) 892dd11376bSBart Van Assche * @crypto_cap_array: Array of crypto capabilities 893dd11376bSBart Van Assche * @crypto_cfg_register: Start of the crypto cfg array 894dd11376bSBart Van Assche * @crypto_profile: the crypto profile of this hba (if applicable) 895dd11376bSBart Van Assche * @debugfs_root: UFS controller debugfs root directory 896dd11376bSBart Van Assche * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay 897dd11376bSBart Van Assche * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore 898dd11376bSBart Van Assche * ee_ctrl_mask 899dd11376bSBart Van Assche * @luns_avail: number of regular and well known LUNs supported by the UFS 900dd11376bSBart Van Assche * device 90157b1c0efSAsutosh Das * @nr_hw_queues: number of hardware queues configured 90257b1c0efSAsutosh Das * @nr_queues: number of Queues of different queue types 903dd11376bSBart Van Assche * @complete_put: whether or not to call ufshcd_rpm_put() from inside 904dd11376bSBart Van Assche * ufshcd_resume_complete() 9056e1d850aSAsutosh Das * @ext_iid_sup: is EXT_IID is supported by UFSHC 906305a357dSAsutosh Das * @mcq_sup: is mcq supported by UFSHC 9072468da61SAsutosh Das * @mcq_enabled: is mcq ready to accept requests 908c263b4efSAsutosh Das * @res: array of resource info of MCQ registers 909c263b4efSAsutosh Das * @mcq_base: Multi circular queue registers base address 9104682abfaSAsutosh Das * @uhq: array of supported hardware queues 9114682abfaSAsutosh Das * @dev_cmd_queue: Queue for issuing device management commands 912dd11376bSBart Van Assche */ 913dd11376bSBart Van Assche struct ufs_hba { 914dd11376bSBart Van Assche void __iomem *mmio_base; 915dd11376bSBart Van Assche 916dd11376bSBart Van Assche /* Virtual memory reference */ 917dd11376bSBart Van Assche struct utp_transfer_cmd_desc *ucdl_base_addr; 918dd11376bSBart Van Assche struct utp_transfer_req_desc *utrdl_base_addr; 919dd11376bSBart Van Assche struct utp_task_req_desc *utmrdl_base_addr; 920dd11376bSBart Van Assche 921dd11376bSBart Van Assche /* DMA memory reference */ 922dd11376bSBart Van Assche dma_addr_t ucdl_dma_addr; 923dd11376bSBart Van Assche dma_addr_t utrdl_dma_addr; 924dd11376bSBart Van Assche dma_addr_t utmrdl_dma_addr; 925dd11376bSBart Van Assche 926dd11376bSBart Van Assche struct Scsi_Host *host; 927dd11376bSBart Van Assche struct device *dev; 928dd11376bSBart Van Assche struct scsi_device *ufs_device_wlun; 929dd11376bSBart Van Assche 930dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_HWMON 931dd11376bSBart Van Assche struct device *hwmon_device; 932dd11376bSBart Van Assche #endif 933dd11376bSBart Van Assche 934dd11376bSBart Van Assche enum ufs_dev_pwr_mode curr_dev_pwr_mode; 935dd11376bSBart Van Assche enum uic_link_state uic_link_state; 936dd11376bSBart Van Assche /* Desired UFS power management level during runtime PM */ 937dd11376bSBart Van Assche enum ufs_pm_level rpm_lvl; 938dd11376bSBart Van Assche /* Desired UFS power management level during system PM */ 939dd11376bSBart Van Assche enum ufs_pm_level spm_lvl; 940dd11376bSBart Van Assche int pm_op_in_progress; 941dd11376bSBart Van Assche 942dd11376bSBart Van Assche /* Auto-Hibernate Idle Timer register value */ 943dd11376bSBart Van Assche u32 ahit; 944dd11376bSBart Van Assche 945dd11376bSBart Van Assche struct ufshcd_lrb *lrb; 946dd11376bSBart Van Assche 947dd11376bSBart Van Assche unsigned long outstanding_tasks; 948dd11376bSBart Van Assche spinlock_t outstanding_lock; 949dd11376bSBart Van Assche unsigned long outstanding_reqs; 950dd11376bSBart Van Assche 951dd11376bSBart Van Assche u32 capabilities; 952dd11376bSBart Van Assche int nutrs; 9536e1d850aSAsutosh Das u32 mcq_capabilities; 954dd11376bSBart Van Assche int nutmrs; 955dd11376bSBart Van Assche u32 reserved_slot; 956dd11376bSBart Van Assche u32 ufs_version; 957dd11376bSBart Van Assche const struct ufs_hba_variant_ops *vops; 958dd11376bSBart Van Assche struct ufs_hba_variant_params *vps; 959dd11376bSBart Van Assche void *priv; 960ada1e653SEric Biggers #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 961ada1e653SEric Biggers size_t sg_entry_size; 962ada1e653SEric Biggers #endif 963dd11376bSBart Van Assche unsigned int irq; 964dd11376bSBart Van Assche bool is_irq_enabled; 965dd11376bSBart Van Assche enum ufs_ref_clk_freq dev_ref_clk_freq; 966dd11376bSBart Van Assche 967dd11376bSBart Van Assche unsigned int quirks; /* Deviations from standard UFSHCI spec. */ 968dd11376bSBart Van Assche 969dd11376bSBart Van Assche /* Device deviations from standard UFS device spec. */ 970dd11376bSBart Van Assche unsigned int dev_quirks; 971dd11376bSBart Van Assche 972dd11376bSBart Van Assche struct blk_mq_tag_set tmf_tag_set; 973dd11376bSBart Van Assche struct request_queue *tmf_queue; 974dd11376bSBart Van Assche struct request **tmf_rqs; 975dd11376bSBart Van Assche 976dd11376bSBart Van Assche struct uic_command *active_uic_cmd; 977dd11376bSBart Van Assche struct mutex uic_cmd_mutex; 978dd11376bSBart Van Assche struct completion *uic_async_done; 979dd11376bSBart Van Assche 980dd11376bSBart Van Assche enum ufshcd_state ufshcd_state; 981dd11376bSBart Van Assche u32 eh_flags; 982dd11376bSBart Van Assche u32 intr_mask; 983dd11376bSBart Van Assche u16 ee_ctrl_mask; 984dd11376bSBart Van Assche u16 ee_drv_mask; 985dd11376bSBart Van Assche u16 ee_usr_mask; 986dd11376bSBart Van Assche struct mutex ee_ctrl_mutex; 987dd11376bSBart Van Assche bool is_powered; 988dd11376bSBart Van Assche bool shutting_down; 989dd11376bSBart Van Assche struct semaphore host_sem; 990dd11376bSBart Van Assche 991dd11376bSBart Van Assche /* Work Queues */ 992dd11376bSBart Van Assche struct workqueue_struct *eh_wq; 993dd11376bSBart Van Assche struct work_struct eh_work; 994dd11376bSBart Van Assche struct work_struct eeh_work; 995dd11376bSBart Van Assche 996dd11376bSBart Van Assche /* HBA Errors */ 997dd11376bSBart Van Assche u32 errors; 998dd11376bSBart Van Assche u32 uic_error; 999dd11376bSBart Van Assche u32 saved_err; 1000dd11376bSBart Van Assche u32 saved_uic_err; 1001dd11376bSBart Van Assche struct ufs_stats ufs_stats; 1002dd11376bSBart Van Assche bool force_reset; 1003dd11376bSBart Van Assche bool force_pmc; 1004dd11376bSBart Van Assche bool silence_err_logs; 1005dd11376bSBart Van Assche 1006dd11376bSBart Van Assche /* Device management request data */ 1007dd11376bSBart Van Assche struct ufs_dev_cmd dev_cmd; 1008dd11376bSBart Van Assche ktime_t last_dme_cmd_tstamp; 1009dd11376bSBart Van Assche int nop_out_timeout; 1010dd11376bSBart Van Assche 1011dd11376bSBart Van Assche /* Keeps information of the UFS device connected to this host */ 1012dd11376bSBart Van Assche struct ufs_dev_info dev_info; 1013dd11376bSBart Van Assche bool auto_bkops_enabled; 1014dd11376bSBart Van Assche struct ufs_vreg_info vreg_info; 1015dd11376bSBart Van Assche struct list_head clk_list_head; 1016dd11376bSBart Van Assche 1017dd11376bSBart Van Assche /* Number of requests aborts */ 1018dd11376bSBart Van Assche int req_abort_count; 1019dd11376bSBart Van Assche 1020dd11376bSBart Van Assche /* Number of lanes available (1 or 2) for Rx/Tx */ 1021dd11376bSBart Van Assche u32 lanes_per_direction; 1022dd11376bSBart Van Assche struct ufs_pa_layer_attr pwr_info; 1023dd11376bSBart Van Assche struct ufs_pwr_mode_info max_pwr_info; 1024dd11376bSBart Van Assche 1025dd11376bSBart Van Assche struct ufs_clk_gating clk_gating; 1026dd11376bSBart Van Assche /* Control to enable/disable host capabilities */ 1027dd11376bSBart Van Assche u32 caps; 1028dd11376bSBart Van Assche 1029dd11376bSBart Van Assche struct devfreq *devfreq; 1030dd11376bSBart Van Assche struct ufs_clk_scaling clk_scaling; 10311a547cbcSBart Van Assche bool system_suspending; 1032dd11376bSBart Van Assche bool is_sys_suspended; 1033dd11376bSBart Van Assche 1034dd11376bSBart Van Assche enum bkops_status urgent_bkops_lvl; 1035dd11376bSBart Van Assche bool is_urgent_bkops_lvl_checked; 1036dd11376bSBart Van Assche 1037dd11376bSBart Van Assche struct rw_semaphore clk_scaling_lock; 1038dd11376bSBart Van Assche atomic_t scsi_block_reqs_cnt; 1039dd11376bSBart Van Assche 1040dd11376bSBart Van Assche struct device bsg_dev; 1041dd11376bSBart Van Assche struct request_queue *bsg_queue; 1042dd11376bSBart Van Assche struct delayed_work rpm_dev_flush_recheck_work; 1043dd11376bSBart Van Assche 1044dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_HPB 1045dd11376bSBart Van Assche struct ufshpb_dev_info ufshpb_dev; 1046dd11376bSBart Van Assche #endif 1047dd11376bSBart Van Assche 1048dd11376bSBart Van Assche struct ufs_hba_monitor monitor; 1049dd11376bSBart Van Assche 1050dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_CRYPTO 1051dd11376bSBart Van Assche union ufs_crypto_capabilities crypto_capabilities; 1052dd11376bSBart Van Assche union ufs_crypto_cap_entry *crypto_cap_array; 1053dd11376bSBart Van Assche u32 crypto_cfg_register; 1054dd11376bSBart Van Assche struct blk_crypto_profile crypto_profile; 1055dd11376bSBart Van Assche #endif 1056dd11376bSBart Van Assche #ifdef CONFIG_DEBUG_FS 1057dd11376bSBart Van Assche struct dentry *debugfs_root; 1058dd11376bSBart Van Assche struct delayed_work debugfs_ee_work; 1059dd11376bSBart Van Assche u32 debugfs_ee_rate_limit_ms; 1060dd11376bSBart Van Assche #endif 1061dd11376bSBart Van Assche u32 luns_avail; 106257b1c0efSAsutosh Das unsigned int nr_hw_queues; 106357b1c0efSAsutosh Das unsigned int nr_queues[HCTX_MAX_TYPES]; 1064dd11376bSBart Van Assche bool complete_put; 10656e1d850aSAsutosh Das bool ext_iid_sup; 10660cab4023SAsutosh Das bool scsi_host_added; 1067305a357dSAsutosh Das bool mcq_sup; 10682468da61SAsutosh Das bool mcq_enabled; 1069c263b4efSAsutosh Das struct ufshcd_res_info res[RES_MAX]; 1070c263b4efSAsutosh Das void __iomem *mcq_base; 10714682abfaSAsutosh Das struct ufs_hw_queue *uhq; 10724682abfaSAsutosh Das struct ufs_hw_queue *dev_cmd_queue; 10732468da61SAsutosh Das struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX]; 10744682abfaSAsutosh Das }; 10754682abfaSAsutosh Das 10764682abfaSAsutosh Das /** 10774682abfaSAsutosh Das * struct ufs_hw_queue - per hardware queue structure 10782468da61SAsutosh Das * @mcq_sq_head: base address of submission queue head pointer 10792468da61SAsutosh Das * @mcq_sq_tail: base address of submission queue tail pointer 10802468da61SAsutosh Das * @mcq_cq_head: base address of completion queue head pointer 10812468da61SAsutosh Das * @mcq_cq_tail: base address of completion queue tail pointer 10824682abfaSAsutosh Das * @sqe_base_addr: submission queue entry base address 10834682abfaSAsutosh Das * @sqe_dma_addr: submission queue dma address 10844682abfaSAsutosh Das * @cqe_base_addr: completion queue base address 10854682abfaSAsutosh Das * @cqe_dma_addr: completion queue dma address 10864682abfaSAsutosh Das * @max_entries: max number of slots in this hardware queue 10872468da61SAsutosh Das * @id: hardware queue ID 108822a2d563SAsutosh Das * @sq_tp_slot: current slot to which SQ tail pointer is pointing 108922a2d563SAsutosh Das * @sq_lock: serialize submission queue access 1090f87b2c41SAsutosh Das * @cq_tail_slot: current slot to which CQ tail pointer is pointing 1091f87b2c41SAsutosh Das * @cq_head_slot: current slot to which CQ head pointer is pointing 1092ed975065SAsutosh Das * @cq_lock: Synchronize between multiple polling instances 10934682abfaSAsutosh Das */ 10944682abfaSAsutosh Das struct ufs_hw_queue { 10952468da61SAsutosh Das void __iomem *mcq_sq_head; 10962468da61SAsutosh Das void __iomem *mcq_sq_tail; 10972468da61SAsutosh Das void __iomem *mcq_cq_head; 10982468da61SAsutosh Das void __iomem *mcq_cq_tail; 10992468da61SAsutosh Das 11004682abfaSAsutosh Das void *sqe_base_addr; 11014682abfaSAsutosh Das dma_addr_t sqe_dma_addr; 11024682abfaSAsutosh Das struct cq_entry *cqe_base_addr; 11034682abfaSAsutosh Das dma_addr_t cqe_dma_addr; 11044682abfaSAsutosh Das u32 max_entries; 11052468da61SAsutosh Das u32 id; 110622a2d563SAsutosh Das u32 sq_tail_slot; 110722a2d563SAsutosh Das spinlock_t sq_lock; 1108f87b2c41SAsutosh Das u32 cq_tail_slot; 1109f87b2c41SAsutosh Das u32 cq_head_slot; 1110ed975065SAsutosh Das spinlock_t cq_lock; 1111dd11376bSBart Van Assche }; 1112dd11376bSBart Van Assche 11132468da61SAsutosh Das static inline bool is_mcq_enabled(struct ufs_hba *hba) 11142468da61SAsutosh Das { 11152468da61SAsutosh Das return hba->mcq_enabled; 11162468da61SAsutosh Das } 11172468da61SAsutosh Das 1118ada1e653SEric Biggers #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 1119ada1e653SEric Biggers static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1120ada1e653SEric Biggers { 1121ada1e653SEric Biggers return hba->sg_entry_size; 1122ada1e653SEric Biggers } 1123ada1e653SEric Biggers 1124ada1e653SEric Biggers static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size) 1125ada1e653SEric Biggers { 1126ada1e653SEric Biggers WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry)); 1127ada1e653SEric Biggers hba->sg_entry_size = sg_entry_size; 1128ada1e653SEric Biggers } 1129ada1e653SEric Biggers #else 1130ada1e653SEric Biggers static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1131ada1e653SEric Biggers { 1132ada1e653SEric Biggers return sizeof(struct ufshcd_sg_entry); 1133ada1e653SEric Biggers } 1134ada1e653SEric Biggers 1135ada1e653SEric Biggers #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \ 1136ada1e653SEric Biggers ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) 1137ada1e653SEric Biggers #endif 1138ada1e653SEric Biggers 1139ada1e653SEric Biggers static inline size_t sizeof_utp_transfer_cmd_desc(const struct ufs_hba *hba) 1140ada1e653SEric Biggers { 1141ada1e653SEric Biggers return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); 1142ada1e653SEric Biggers } 1143ada1e653SEric Biggers 1144dd11376bSBart Van Assche /* Returns true if clocks can be gated. Otherwise false */ 1145dd11376bSBart Van Assche static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) 1146dd11376bSBart Van Assche { 1147dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_CLK_GATING; 1148dd11376bSBart Van Assche } 1149dd11376bSBart Van Assche static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) 1150dd11376bSBart Van Assche { 1151dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1152dd11376bSBart Van Assche } 1153dd11376bSBart Van Assche static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) 1154dd11376bSBart Van Assche { 1155dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_CLK_SCALING; 1156dd11376bSBart Van Assche } 1157dd11376bSBart Van Assche static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) 1158dd11376bSBart Van Assche { 1159dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1160dd11376bSBart Van Assche } 1161dd11376bSBart Van Assche static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) 1162dd11376bSBart Van Assche { 1163dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; 1164dd11376bSBart Van Assche } 1165dd11376bSBart Van Assche 1166dd11376bSBart Van Assche static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) 1167dd11376bSBart Van Assche { 1168dd11376bSBart Van Assche return (hba->caps & UFSHCD_CAP_INTR_AGGR) && 1169dd11376bSBart Van Assche !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); 1170dd11376bSBart Van Assche } 1171dd11376bSBart Van Assche 1172dd11376bSBart Van Assche static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) 1173dd11376bSBart Van Assche { 1174dd11376bSBart Van Assche return !!(ufshcd_is_link_hibern8(hba) && 1175dd11376bSBart Van Assche (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); 1176dd11376bSBart Van Assche } 1177dd11376bSBart Van Assche 1178dd11376bSBart Van Assche static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) 1179dd11376bSBart Van Assche { 1180dd11376bSBart Van Assche return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && 1181dd11376bSBart Van Assche !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); 1182dd11376bSBart Van Assche } 1183dd11376bSBart Van Assche 1184dd11376bSBart Van Assche static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) 1185dd11376bSBart Van Assche { 1186dd11376bSBart Van Assche return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); 1187dd11376bSBart Van Assche } 1188dd11376bSBart Van Assche 1189dd11376bSBart Van Assche static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) 1190dd11376bSBart Van Assche { 1191dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_WB_EN; 1192dd11376bSBart Van Assche } 1193dd11376bSBart Van Assche 119487bd0501SPeter Wang static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) 119587bd0501SPeter Wang { 119687bd0501SPeter Wang return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; 119787bd0501SPeter Wang } 119887bd0501SPeter Wang 11992468da61SAsutosh Das #define ufsmcq_writel(hba, val, reg) \ 12002468da61SAsutosh Das writel((val), (hba)->mcq_base + (reg)) 12012468da61SAsutosh Das #define ufsmcq_readl(hba, reg) \ 12022468da61SAsutosh Das readl((hba)->mcq_base + (reg)) 12032468da61SAsutosh Das 12042468da61SAsutosh Das #define ufsmcq_writelx(hba, val, reg) \ 12052468da61SAsutosh Das writel_relaxed((val), (hba)->mcq_base + (reg)) 12062468da61SAsutosh Das #define ufsmcq_readlx(hba, reg) \ 12072468da61SAsutosh Das readl_relaxed((hba)->mcq_base + (reg)) 12082468da61SAsutosh Das 1209dd11376bSBart Van Assche #define ufshcd_writel(hba, val, reg) \ 1210dd11376bSBart Van Assche writel((val), (hba)->mmio_base + (reg)) 1211dd11376bSBart Van Assche #define ufshcd_readl(hba, reg) \ 1212dd11376bSBart Van Assche readl((hba)->mmio_base + (reg)) 1213dd11376bSBart Van Assche 1214dd11376bSBart Van Assche /** 1215dd11376bSBart Van Assche * ufshcd_rmwl - perform read/modify/write for a controller register 1216dd11376bSBart Van Assche * @hba: per adapter instance 1217dd11376bSBart Van Assche * @mask: mask to apply on read value 1218dd11376bSBart Van Assche * @val: actual value to write 1219dd11376bSBart Van Assche * @reg: register address 1220dd11376bSBart Van Assche */ 1221dd11376bSBart Van Assche static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) 1222dd11376bSBart Van Assche { 1223dd11376bSBart Van Assche u32 tmp; 1224dd11376bSBart Van Assche 1225dd11376bSBart Van Assche tmp = ufshcd_readl(hba, reg); 1226dd11376bSBart Van Assche tmp &= ~mask; 1227dd11376bSBart Van Assche tmp |= (val & mask); 1228dd11376bSBart Van Assche ufshcd_writel(hba, tmp, reg); 1229dd11376bSBart Van Assche } 1230dd11376bSBart Van Assche 1231dd11376bSBart Van Assche int ufshcd_alloc_host(struct device *, struct ufs_hba **); 1232dd11376bSBart Van Assche void ufshcd_dealloc_host(struct ufs_hba *); 1233dd11376bSBart Van Assche int ufshcd_hba_enable(struct ufs_hba *hba); 1234dd11376bSBart Van Assche int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); 1235dd11376bSBart Van Assche int ufshcd_link_recovery(struct ufs_hba *hba); 1236dd11376bSBart Van Assche int ufshcd_make_hba_operational(struct ufs_hba *hba); 1237dd11376bSBart Van Assche void ufshcd_remove(struct ufs_hba *); 1238dd11376bSBart Van Assche int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); 1239dd11376bSBart Van Assche int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); 1240dd11376bSBart Van Assche void ufshcd_delay_us(unsigned long us, unsigned long tolerance); 1241dd11376bSBart Van Assche void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); 1242dd11376bSBart Van Assche void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); 1243dd11376bSBart Van Assche void ufshcd_hba_stop(struct ufs_hba *hba); 1244dd11376bSBart Van Assche void ufshcd_schedule_eh_work(struct ufs_hba *hba); 1245*e02288e0SCan Guo void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); 1246*e02288e0SCan Guo unsigned long ufshcd_mcq_poll_cqe_nolock(struct ufs_hba *hba, 1247*e02288e0SCan Guo struct ufs_hw_queue *hwq); 1248*e02288e0SCan Guo void ufshcd_mcq_enable_esi(struct ufs_hba *hba); 1249*e02288e0SCan Guo void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); 1250dd11376bSBart Van Assche 1251dd11376bSBart Van Assche /** 1252dd11376bSBart Van Assche * ufshcd_set_variant - set variant specific data to the hba 1253dd11376bSBart Van Assche * @hba: per adapter instance 1254dd11376bSBart Van Assche * @variant: pointer to variant specific data 1255dd11376bSBart Van Assche */ 1256dd11376bSBart Van Assche static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) 1257dd11376bSBart Van Assche { 1258dd11376bSBart Van Assche BUG_ON(!hba); 1259dd11376bSBart Van Assche hba->priv = variant; 1260dd11376bSBart Van Assche } 1261dd11376bSBart Van Assche 1262dd11376bSBart Van Assche /** 1263dd11376bSBart Van Assche * ufshcd_get_variant - get variant specific data from the hba 1264dd11376bSBart Van Assche * @hba: per adapter instance 1265dd11376bSBart Van Assche */ 1266dd11376bSBart Van Assche static inline void *ufshcd_get_variant(struct ufs_hba *hba) 1267dd11376bSBart Van Assche { 1268dd11376bSBart Van Assche BUG_ON(!hba); 1269dd11376bSBart Van Assche return hba->priv; 1270dd11376bSBart Van Assche } 1271dd11376bSBart Van Assche 1272dd11376bSBart Van Assche #ifdef CONFIG_PM 1273dd11376bSBart Van Assche extern int ufshcd_runtime_suspend(struct device *dev); 1274dd11376bSBart Van Assche extern int ufshcd_runtime_resume(struct device *dev); 1275dd11376bSBart Van Assche #endif 1276dd11376bSBart Van Assche #ifdef CONFIG_PM_SLEEP 1277dd11376bSBart Van Assche extern int ufshcd_system_suspend(struct device *dev); 1278dd11376bSBart Van Assche extern int ufshcd_system_resume(struct device *dev); 1279dd11376bSBart Van Assche #endif 1280dd11376bSBart Van Assche extern int ufshcd_shutdown(struct ufs_hba *hba); 1281dd11376bSBart Van Assche extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 1282dd11376bSBart Van Assche int agreed_gear, 1283dd11376bSBart Van Assche int adapt_val); 1284dd11376bSBart Van Assche extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 1285dd11376bSBart Van Assche u8 attr_set, u32 mib_val, u8 peer); 1286dd11376bSBart Van Assche extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 1287dd11376bSBart Van Assche u32 *mib_val, u8 peer); 1288dd11376bSBart Van Assche extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, 1289dd11376bSBart Van Assche struct ufs_pa_layer_attr *desired_pwr_mode); 1290fc53683bSStanley Chu extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); 1291dd11376bSBart Van Assche 1292dd11376bSBart Van Assche /* UIC command interfaces for DME primitives */ 1293dd11376bSBart Van Assche #define DME_LOCAL 0 1294dd11376bSBart Van Assche #define DME_PEER 1 1295dd11376bSBart Van Assche #define ATTR_SET_NOR 0 /* NORMAL */ 1296dd11376bSBart Van Assche #define ATTR_SET_ST 1 /* STATIC */ 1297dd11376bSBart Van Assche 1298dd11376bSBart Van Assche static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 1299dd11376bSBart Van Assche u32 mib_val) 1300dd11376bSBart Van Assche { 1301dd11376bSBart Van Assche return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1302dd11376bSBart Van Assche mib_val, DME_LOCAL); 1303dd11376bSBart Van Assche } 1304dd11376bSBart Van Assche 1305dd11376bSBart Van Assche static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, 1306dd11376bSBart Van Assche u32 mib_val) 1307dd11376bSBart Van Assche { 1308dd11376bSBart Van Assche return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1309dd11376bSBart Van Assche mib_val, DME_LOCAL); 1310dd11376bSBart Van Assche } 1311dd11376bSBart Van Assche 1312dd11376bSBart Van Assche static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 1313dd11376bSBart Van Assche u32 mib_val) 1314dd11376bSBart Van Assche { 1315dd11376bSBart Van Assche return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1316dd11376bSBart Van Assche mib_val, DME_PEER); 1317dd11376bSBart Van Assche } 1318dd11376bSBart Van Assche 1319dd11376bSBart Van Assche static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, 1320dd11376bSBart Van Assche u32 mib_val) 1321dd11376bSBart Van Assche { 1322dd11376bSBart Van Assche return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1323dd11376bSBart Van Assche mib_val, DME_PEER); 1324dd11376bSBart Van Assche } 1325dd11376bSBart Van Assche 1326dd11376bSBart Van Assche static inline int ufshcd_dme_get(struct ufs_hba *hba, 1327dd11376bSBart Van Assche u32 attr_sel, u32 *mib_val) 1328dd11376bSBart Van Assche { 1329dd11376bSBart Van Assche return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 1330dd11376bSBart Van Assche } 1331dd11376bSBart Van Assche 1332dd11376bSBart Van Assche static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 1333dd11376bSBart Van Assche u32 attr_sel, u32 *mib_val) 1334dd11376bSBart Van Assche { 1335dd11376bSBart Van Assche return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 1336dd11376bSBart Van Assche } 1337dd11376bSBart Van Assche 1338dd11376bSBart Van Assche static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) 1339dd11376bSBart Van Assche { 1340dd11376bSBart Van Assche return (pwr_info->pwr_rx == FAST_MODE || 1341dd11376bSBart Van Assche pwr_info->pwr_rx == FASTAUTO_MODE) && 1342dd11376bSBart Van Assche (pwr_info->pwr_tx == FAST_MODE || 1343dd11376bSBart Van Assche pwr_info->pwr_tx == FASTAUTO_MODE); 1344dd11376bSBart Van Assche } 1345dd11376bSBart Van Assche 1346dd11376bSBart Van Assche static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) 1347dd11376bSBart Van Assche { 1348dd11376bSBart Van Assche return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); 1349dd11376bSBart Van Assche } 1350dd11376bSBart Van Assche 1351dd11376bSBart Van Assche void ufshcd_auto_hibern8_enable(struct ufs_hba *hba); 1352dd11376bSBart Van Assche void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); 1353dd11376bSBart Van Assche void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 1354dd11376bSBart Van Assche const struct ufs_dev_quirk *fixups); 1355dd11376bSBart Van Assche #define SD_ASCII_STD true 1356dd11376bSBart Van Assche #define SD_RAW false 1357dd11376bSBart Van Assche int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 1358dd11376bSBart Van Assche u8 **buf, bool ascii); 1359dd11376bSBart Van Assche 1360dd11376bSBart Van Assche int ufshcd_hold(struct ufs_hba *hba, bool async); 1361dd11376bSBart Van Assche void ufshcd_release(struct ufs_hba *hba); 1362dd11376bSBart Van Assche 1363dd11376bSBart Van Assche void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); 1364dd11376bSBart Van Assche 1365dd11376bSBart Van Assche u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); 1366dd11376bSBart Van Assche 13671d6f9decSStanley Chu int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); 13681d6f9decSStanley Chu 1369dd11376bSBart Van Assche int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); 1370dd11376bSBart Van Assche 1371dd11376bSBart Van Assche int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 1372dd11376bSBart Van Assche struct utp_upiu_req *req_upiu, 1373dd11376bSBart Van Assche struct utp_upiu_req *rsp_upiu, 1374dd11376bSBart Van Assche int msgcode, 1375dd11376bSBart Van Assche u8 *desc_buff, int *buff_len, 1376dd11376bSBart Van Assche enum query_opcode desc_op); 13776ff265fcSBean Huo int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 13786ff265fcSBean Huo struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, 13796ff265fcSBean Huo struct ufs_ehs *ehs_rsp, int sg_cnt, 13806ff265fcSBean Huo struct scatterlist *sg_list, enum dma_data_direction dir); 1381dd11376bSBart Van Assche int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); 13826c4148ceSJinyoung Choi int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); 1383dd11376bSBart Van Assche int ufshcd_suspend_prepare(struct device *dev); 1384dd11376bSBart Van Assche int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); 1385dd11376bSBart Van Assche void ufshcd_resume_complete(struct device *dev); 1386dd11376bSBart Van Assche 1387dd11376bSBart Van Assche /* Wrapper functions for safely calling variant operations */ 1388dd11376bSBart Van Assche static inline int ufshcd_vops_init(struct ufs_hba *hba) 1389dd11376bSBart Van Assche { 1390dd11376bSBart Van Assche if (hba->vops && hba->vops->init) 1391dd11376bSBart Van Assche return hba->vops->init(hba); 1392dd11376bSBart Van Assche 1393dd11376bSBart Van Assche return 0; 1394dd11376bSBart Van Assche } 1395dd11376bSBart Van Assche 1396dd11376bSBart Van Assche static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) 1397dd11376bSBart Van Assche { 1398dd11376bSBart Van Assche if (hba->vops && hba->vops->phy_initialization) 1399dd11376bSBart Van Assche return hba->vops->phy_initialization(hba); 1400dd11376bSBart Van Assche 1401dd11376bSBart Van Assche return 0; 1402dd11376bSBart Van Assche } 1403dd11376bSBart Van Assche 140435d11ec2SKrzysztof Kozlowski extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; 1405dd11376bSBart Van Assche 1406dd11376bSBart Van Assche int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1407dd11376bSBart Van Assche const char *prefix); 1408dd11376bSBart Van Assche 1409dd11376bSBart Van Assche int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); 1410dd11376bSBart Van Assche int ufshcd_write_ee_control(struct ufs_hba *hba); 141135d11ec2SKrzysztof Kozlowski int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 141235d11ec2SKrzysztof Kozlowski const u16 *other_mask, u16 set, u16 clr); 1413dd11376bSBart Van Assche 1414dd11376bSBart Van Assche #endif /* End of Header */ 1415