1*dd11376bSBart Van Assche /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*dd11376bSBart Van Assche /* 3*dd11376bSBart Van Assche * Universal Flash Storage Host controller driver 4*dd11376bSBart Van Assche * Copyright (C) 2011-2013 Samsung India Software Operations 5*dd11376bSBart Van Assche * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6*dd11376bSBart Van Assche * 7*dd11376bSBart Van Assche * Authors: 8*dd11376bSBart Van Assche * Santosh Yaraganavi <santosh.sy@samsung.com> 9*dd11376bSBart Van Assche * Vinayak Holikatti <h.vinayak@samsung.com> 10*dd11376bSBart Van Assche */ 11*dd11376bSBart Van Assche 12*dd11376bSBart Van Assche #ifndef _UFSHCD_H 13*dd11376bSBart Van Assche #define _UFSHCD_H 14*dd11376bSBart Van Assche 15*dd11376bSBart Van Assche #include <linux/bitfield.h> 16*dd11376bSBart Van Assche #include <linux/blk-crypto-profile.h> 17*dd11376bSBart Van Assche #include <linux/blk-mq.h> 18*dd11376bSBart Van Assche #include <linux/devfreq.h> 19*dd11376bSBart Van Assche #include <linux/pm_runtime.h> 20*dd11376bSBart Van Assche #include <scsi/scsi_device.h> 21*dd11376bSBart Van Assche #include <ufs/unipro.h> 22*dd11376bSBart Van Assche #include <ufs/ufs.h> 23*dd11376bSBart Van Assche #include <ufs/ufs_quirks.h> 24*dd11376bSBart Van Assche #include <ufs/ufshci.h> 25*dd11376bSBart Van Assche 26*dd11376bSBart Van Assche #define UFSHCD "ufshcd" 27*dd11376bSBart Van Assche 28*dd11376bSBart Van Assche struct ufs_hba; 29*dd11376bSBart Van Assche 30*dd11376bSBart Van Assche enum dev_cmd_type { 31*dd11376bSBart Van Assche DEV_CMD_TYPE_NOP = 0x0, 32*dd11376bSBart Van Assche DEV_CMD_TYPE_QUERY = 0x1, 33*dd11376bSBart Van Assche }; 34*dd11376bSBart Van Assche 35*dd11376bSBart Van Assche enum ufs_event_type { 36*dd11376bSBart Van Assche /* uic specific errors */ 37*dd11376bSBart Van Assche UFS_EVT_PA_ERR = 0, 38*dd11376bSBart Van Assche UFS_EVT_DL_ERR, 39*dd11376bSBart Van Assche UFS_EVT_NL_ERR, 40*dd11376bSBart Van Assche UFS_EVT_TL_ERR, 41*dd11376bSBart Van Assche UFS_EVT_DME_ERR, 42*dd11376bSBart Van Assche 43*dd11376bSBart Van Assche /* fatal errors */ 44*dd11376bSBart Van Assche UFS_EVT_AUTO_HIBERN8_ERR, 45*dd11376bSBart Van Assche UFS_EVT_FATAL_ERR, 46*dd11376bSBart Van Assche UFS_EVT_LINK_STARTUP_FAIL, 47*dd11376bSBart Van Assche UFS_EVT_RESUME_ERR, 48*dd11376bSBart Van Assche UFS_EVT_SUSPEND_ERR, 49*dd11376bSBart Van Assche UFS_EVT_WL_SUSP_ERR, 50*dd11376bSBart Van Assche UFS_EVT_WL_RES_ERR, 51*dd11376bSBart Van Assche 52*dd11376bSBart Van Assche /* abnormal events */ 53*dd11376bSBart Van Assche UFS_EVT_DEV_RESET, 54*dd11376bSBart Van Assche UFS_EVT_HOST_RESET, 55*dd11376bSBart Van Assche UFS_EVT_ABORT, 56*dd11376bSBart Van Assche 57*dd11376bSBart Van Assche UFS_EVT_CNT, 58*dd11376bSBart Van Assche }; 59*dd11376bSBart Van Assche 60*dd11376bSBart Van Assche /** 61*dd11376bSBart Van Assche * struct uic_command - UIC command structure 62*dd11376bSBart Van Assche * @command: UIC command 63*dd11376bSBart Van Assche * @argument1: UIC command argument 1 64*dd11376bSBart Van Assche * @argument2: UIC command argument 2 65*dd11376bSBart Van Assche * @argument3: UIC command argument 3 66*dd11376bSBart Van Assche * @cmd_active: Indicate if UIC command is outstanding 67*dd11376bSBart Van Assche * @done: UIC command completion 68*dd11376bSBart Van Assche */ 69*dd11376bSBart Van Assche struct uic_command { 70*dd11376bSBart Van Assche u32 command; 71*dd11376bSBart Van Assche u32 argument1; 72*dd11376bSBart Van Assche u32 argument2; 73*dd11376bSBart Van Assche u32 argument3; 74*dd11376bSBart Van Assche int cmd_active; 75*dd11376bSBart Van Assche struct completion done; 76*dd11376bSBart Van Assche }; 77*dd11376bSBart Van Assche 78*dd11376bSBart Van Assche /* Used to differentiate the power management options */ 79*dd11376bSBart Van Assche enum ufs_pm_op { 80*dd11376bSBart Van Assche UFS_RUNTIME_PM, 81*dd11376bSBart Van Assche UFS_SYSTEM_PM, 82*dd11376bSBart Van Assche UFS_SHUTDOWN_PM, 83*dd11376bSBart Van Assche }; 84*dd11376bSBart Van Assche 85*dd11376bSBart Van Assche /* Host <-> Device UniPro Link state */ 86*dd11376bSBart Van Assche enum uic_link_state { 87*dd11376bSBart Van Assche UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 88*dd11376bSBart Van Assche UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 89*dd11376bSBart Van Assche UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 90*dd11376bSBart Van Assche UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ 91*dd11376bSBart Van Assche }; 92*dd11376bSBart Van Assche 93*dd11376bSBart Van Assche #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) 94*dd11376bSBart Van Assche #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ 95*dd11376bSBart Van Assche UIC_LINK_ACTIVE_STATE) 96*dd11376bSBart Van Assche #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ 97*dd11376bSBart Van Assche UIC_LINK_HIBERN8_STATE) 98*dd11376bSBart Van Assche #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ 99*dd11376bSBart Van Assche UIC_LINK_BROKEN_STATE) 100*dd11376bSBart Van Assche #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) 101*dd11376bSBart Van Assche #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ 102*dd11376bSBart Van Assche UIC_LINK_ACTIVE_STATE) 103*dd11376bSBart Van Assche #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ 104*dd11376bSBart Van Assche UIC_LINK_HIBERN8_STATE) 105*dd11376bSBart Van Assche #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ 106*dd11376bSBart Van Assche UIC_LINK_BROKEN_STATE) 107*dd11376bSBart Van Assche 108*dd11376bSBart Van Assche #define ufshcd_set_ufs_dev_active(h) \ 109*dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) 110*dd11376bSBart Van Assche #define ufshcd_set_ufs_dev_sleep(h) \ 111*dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) 112*dd11376bSBart Van Assche #define ufshcd_set_ufs_dev_poweroff(h) \ 113*dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) 114*dd11376bSBart Van Assche #define ufshcd_set_ufs_dev_deepsleep(h) \ 115*dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) 116*dd11376bSBart Van Assche #define ufshcd_is_ufs_dev_active(h) \ 117*dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) 118*dd11376bSBart Van Assche #define ufshcd_is_ufs_dev_sleep(h) \ 119*dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) 120*dd11376bSBart Van Assche #define ufshcd_is_ufs_dev_poweroff(h) \ 121*dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) 122*dd11376bSBart Van Assche #define ufshcd_is_ufs_dev_deepsleep(h) \ 123*dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) 124*dd11376bSBart Van Assche 125*dd11376bSBart Van Assche /* 126*dd11376bSBart Van Assche * UFS Power management levels. 127*dd11376bSBart Van Assche * Each level is in increasing order of power savings, except DeepSleep 128*dd11376bSBart Van Assche * which is lower than PowerDown with power on but not PowerDown with 129*dd11376bSBart Van Assche * power off. 130*dd11376bSBart Van Assche */ 131*dd11376bSBart Van Assche enum ufs_pm_level { 132*dd11376bSBart Van Assche UFS_PM_LVL_0, 133*dd11376bSBart Van Assche UFS_PM_LVL_1, 134*dd11376bSBart Van Assche UFS_PM_LVL_2, 135*dd11376bSBart Van Assche UFS_PM_LVL_3, 136*dd11376bSBart Van Assche UFS_PM_LVL_4, 137*dd11376bSBart Van Assche UFS_PM_LVL_5, 138*dd11376bSBart Van Assche UFS_PM_LVL_6, 139*dd11376bSBart Van Assche UFS_PM_LVL_MAX 140*dd11376bSBart Van Assche }; 141*dd11376bSBart Van Assche 142*dd11376bSBart Van Assche struct ufs_pm_lvl_states { 143*dd11376bSBart Van Assche enum ufs_dev_pwr_mode dev_state; 144*dd11376bSBart Van Assche enum uic_link_state link_state; 145*dd11376bSBart Van Assche }; 146*dd11376bSBart Van Assche 147*dd11376bSBart Van Assche /** 148*dd11376bSBart Van Assche * struct ufshcd_lrb - local reference block 149*dd11376bSBart Van Assche * @utr_descriptor_ptr: UTRD address of the command 150*dd11376bSBart Van Assche * @ucd_req_ptr: UCD address of the command 151*dd11376bSBart Van Assche * @ucd_rsp_ptr: Response UPIU address for this command 152*dd11376bSBart Van Assche * @ucd_prdt_ptr: PRDT address of the command 153*dd11376bSBart Van Assche * @utrd_dma_addr: UTRD dma address for debug 154*dd11376bSBart Van Assche * @ucd_prdt_dma_addr: PRDT dma address for debug 155*dd11376bSBart Van Assche * @ucd_rsp_dma_addr: UPIU response dma address for debug 156*dd11376bSBart Van Assche * @ucd_req_dma_addr: UPIU request dma address for debug 157*dd11376bSBart Van Assche * @cmd: pointer to SCSI command 158*dd11376bSBart Van Assche * @scsi_status: SCSI status of the command 159*dd11376bSBart Van Assche * @command_type: SCSI, UFS, Query. 160*dd11376bSBart Van Assche * @task_tag: Task tag of the command 161*dd11376bSBart Van Assche * @lun: LUN of the command 162*dd11376bSBart Van Assche * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) 163*dd11376bSBart Van Assche * @issue_time_stamp: time stamp for debug purposes 164*dd11376bSBart Van Assche * @compl_time_stamp: time stamp for statistics 165*dd11376bSBart Van Assche * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) 166*dd11376bSBart Van Assche * @data_unit_num: the data unit number for the first block for inline crypto 167*dd11376bSBart Van Assche * @req_abort_skip: skip request abort task flag 168*dd11376bSBart Van Assche */ 169*dd11376bSBart Van Assche struct ufshcd_lrb { 170*dd11376bSBart Van Assche struct utp_transfer_req_desc *utr_descriptor_ptr; 171*dd11376bSBart Van Assche struct utp_upiu_req *ucd_req_ptr; 172*dd11376bSBart Van Assche struct utp_upiu_rsp *ucd_rsp_ptr; 173*dd11376bSBart Van Assche struct ufshcd_sg_entry *ucd_prdt_ptr; 174*dd11376bSBart Van Assche 175*dd11376bSBart Van Assche dma_addr_t utrd_dma_addr; 176*dd11376bSBart Van Assche dma_addr_t ucd_req_dma_addr; 177*dd11376bSBart Van Assche dma_addr_t ucd_rsp_dma_addr; 178*dd11376bSBart Van Assche dma_addr_t ucd_prdt_dma_addr; 179*dd11376bSBart Van Assche 180*dd11376bSBart Van Assche struct scsi_cmnd *cmd; 181*dd11376bSBart Van Assche int scsi_status; 182*dd11376bSBart Van Assche 183*dd11376bSBart Van Assche int command_type; 184*dd11376bSBart Van Assche int task_tag; 185*dd11376bSBart Van Assche u8 lun; /* UPIU LUN id field is only 8-bit wide */ 186*dd11376bSBart Van Assche bool intr_cmd; 187*dd11376bSBart Van Assche ktime_t issue_time_stamp; 188*dd11376bSBart Van Assche ktime_t compl_time_stamp; 189*dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_CRYPTO 190*dd11376bSBart Van Assche int crypto_key_slot; 191*dd11376bSBart Van Assche u64 data_unit_num; 192*dd11376bSBart Van Assche #endif 193*dd11376bSBart Van Assche 194*dd11376bSBart Van Assche bool req_abort_skip; 195*dd11376bSBart Van Assche }; 196*dd11376bSBart Van Assche 197*dd11376bSBart Van Assche /** 198*dd11376bSBart Van Assche * struct ufs_query - holds relevant data structures for query request 199*dd11376bSBart Van Assche * @request: request upiu and function 200*dd11376bSBart Van Assche * @descriptor: buffer for sending/receiving descriptor 201*dd11376bSBart Van Assche * @response: response upiu and response 202*dd11376bSBart Van Assche */ 203*dd11376bSBart Van Assche struct ufs_query { 204*dd11376bSBart Van Assche struct ufs_query_req request; 205*dd11376bSBart Van Assche u8 *descriptor; 206*dd11376bSBart Van Assche struct ufs_query_res response; 207*dd11376bSBart Van Assche }; 208*dd11376bSBart Van Assche 209*dd11376bSBart Van Assche /** 210*dd11376bSBart Van Assche * struct ufs_dev_cmd - all assosiated fields with device management commands 211*dd11376bSBart Van Assche * @type: device management command type - Query, NOP OUT 212*dd11376bSBart Van Assche * @lock: lock to allow one command at a time 213*dd11376bSBart Van Assche * @complete: internal commands completion 214*dd11376bSBart Van Assche * @query: Device management query information 215*dd11376bSBart Van Assche */ 216*dd11376bSBart Van Assche struct ufs_dev_cmd { 217*dd11376bSBart Van Assche enum dev_cmd_type type; 218*dd11376bSBart Van Assche struct mutex lock; 219*dd11376bSBart Van Assche struct completion *complete; 220*dd11376bSBart Van Assche struct ufs_query query; 221*dd11376bSBart Van Assche }; 222*dd11376bSBart Van Assche 223*dd11376bSBart Van Assche /** 224*dd11376bSBart Van Assche * struct ufs_clk_info - UFS clock related info 225*dd11376bSBart Van Assche * @list: list headed by hba->clk_list_head 226*dd11376bSBart Van Assche * @clk: clock node 227*dd11376bSBart Van Assche * @name: clock name 228*dd11376bSBart Van Assche * @max_freq: maximum frequency supported by the clock 229*dd11376bSBart Van Assche * @min_freq: min frequency that can be used for clock scaling 230*dd11376bSBart Van Assche * @curr_freq: indicates the current frequency that it is set to 231*dd11376bSBart Van Assche * @keep_link_active: indicates that the clk should not be disabled if 232*dd11376bSBart Van Assche * link is active 233*dd11376bSBart Van Assche * @enabled: variable to check against multiple enable/disable 234*dd11376bSBart Van Assche */ 235*dd11376bSBart Van Assche struct ufs_clk_info { 236*dd11376bSBart Van Assche struct list_head list; 237*dd11376bSBart Van Assche struct clk *clk; 238*dd11376bSBart Van Assche const char *name; 239*dd11376bSBart Van Assche u32 max_freq; 240*dd11376bSBart Van Assche u32 min_freq; 241*dd11376bSBart Van Assche u32 curr_freq; 242*dd11376bSBart Van Assche bool keep_link_active; 243*dd11376bSBart Van Assche bool enabled; 244*dd11376bSBart Van Assche }; 245*dd11376bSBart Van Assche 246*dd11376bSBart Van Assche enum ufs_notify_change_status { 247*dd11376bSBart Van Assche PRE_CHANGE, 248*dd11376bSBart Van Assche POST_CHANGE, 249*dd11376bSBart Van Assche }; 250*dd11376bSBart Van Assche 251*dd11376bSBart Van Assche struct ufs_pa_layer_attr { 252*dd11376bSBart Van Assche u32 gear_rx; 253*dd11376bSBart Van Assche u32 gear_tx; 254*dd11376bSBart Van Assche u32 lane_rx; 255*dd11376bSBart Van Assche u32 lane_tx; 256*dd11376bSBart Van Assche u32 pwr_rx; 257*dd11376bSBart Van Assche u32 pwr_tx; 258*dd11376bSBart Van Assche u32 hs_rate; 259*dd11376bSBart Van Assche }; 260*dd11376bSBart Van Assche 261*dd11376bSBart Van Assche struct ufs_pwr_mode_info { 262*dd11376bSBart Van Assche bool is_valid; 263*dd11376bSBart Van Assche struct ufs_pa_layer_attr info; 264*dd11376bSBart Van Assche }; 265*dd11376bSBart Van Assche 266*dd11376bSBart Van Assche /** 267*dd11376bSBart Van Assche * struct ufs_hba_variant_ops - variant specific callbacks 268*dd11376bSBart Van Assche * @name: variant name 269*dd11376bSBart Van Assche * @init: called when the driver is initialized 270*dd11376bSBart Van Assche * @exit: called to cleanup everything done in init 271*dd11376bSBart Van Assche * @get_ufs_hci_version: called to get UFS HCI version 272*dd11376bSBart Van Assche * @clk_scale_notify: notifies that clks are scaled up/down 273*dd11376bSBart Van Assche * @setup_clocks: called before touching any of the controller registers 274*dd11376bSBart Van Assche * @hce_enable_notify: called before and after HCE enable bit is set to allow 275*dd11376bSBart Van Assche * variant specific Uni-Pro initialization. 276*dd11376bSBart Van Assche * @link_startup_notify: called before and after Link startup is carried out 277*dd11376bSBart Van Assche * to allow variant specific Uni-Pro initialization. 278*dd11376bSBart Van Assche * @pwr_change_notify: called before and after a power mode change 279*dd11376bSBart Van Assche * is carried out to allow vendor spesific capabilities 280*dd11376bSBart Van Assche * to be set. 281*dd11376bSBart Van Assche * @setup_xfer_req: called before any transfer request is issued 282*dd11376bSBart Van Assche * to set some things 283*dd11376bSBart Van Assche * @setup_task_mgmt: called before any task management request is issued 284*dd11376bSBart Van Assche * to set some things 285*dd11376bSBart Van Assche * @hibern8_notify: called around hibern8 enter/exit 286*dd11376bSBart Van Assche * @apply_dev_quirks: called to apply device specific quirks 287*dd11376bSBart Van Assche * @fixup_dev_quirks: called to modify device specific quirks 288*dd11376bSBart Van Assche * @suspend: called during host controller PM callback 289*dd11376bSBart Van Assche * @resume: called during host controller PM callback 290*dd11376bSBart Van Assche * @dbg_register_dump: used to dump controller debug information 291*dd11376bSBart Van Assche * @phy_initialization: used to initialize phys 292*dd11376bSBart Van Assche * @device_reset: called to issue a reset pulse on the UFS device 293*dd11376bSBart Van Assche * @config_scaling_param: called to configure clock scaling parameters 294*dd11376bSBart Van Assche * @program_key: program or evict an inline encryption key 295*dd11376bSBart Van Assche * @event_notify: called to notify important events 296*dd11376bSBart Van Assche */ 297*dd11376bSBart Van Assche struct ufs_hba_variant_ops { 298*dd11376bSBart Van Assche const char *name; 299*dd11376bSBart Van Assche int (*init)(struct ufs_hba *); 300*dd11376bSBart Van Assche void (*exit)(struct ufs_hba *); 301*dd11376bSBart Van Assche u32 (*get_ufs_hci_version)(struct ufs_hba *); 302*dd11376bSBart Van Assche int (*clk_scale_notify)(struct ufs_hba *, bool, 303*dd11376bSBart Van Assche enum ufs_notify_change_status); 304*dd11376bSBart Van Assche int (*setup_clocks)(struct ufs_hba *, bool, 305*dd11376bSBart Van Assche enum ufs_notify_change_status); 306*dd11376bSBart Van Assche int (*hce_enable_notify)(struct ufs_hba *, 307*dd11376bSBart Van Assche enum ufs_notify_change_status); 308*dd11376bSBart Van Assche int (*link_startup_notify)(struct ufs_hba *, 309*dd11376bSBart Van Assche enum ufs_notify_change_status); 310*dd11376bSBart Van Assche int (*pwr_change_notify)(struct ufs_hba *, 311*dd11376bSBart Van Assche enum ufs_notify_change_status status, 312*dd11376bSBart Van Assche struct ufs_pa_layer_attr *, 313*dd11376bSBart Van Assche struct ufs_pa_layer_attr *); 314*dd11376bSBart Van Assche void (*setup_xfer_req)(struct ufs_hba *hba, int tag, 315*dd11376bSBart Van Assche bool is_scsi_cmd); 316*dd11376bSBart Van Assche void (*setup_task_mgmt)(struct ufs_hba *, int, u8); 317*dd11376bSBart Van Assche void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, 318*dd11376bSBart Van Assche enum ufs_notify_change_status); 319*dd11376bSBart Van Assche int (*apply_dev_quirks)(struct ufs_hba *hba); 320*dd11376bSBart Van Assche void (*fixup_dev_quirks)(struct ufs_hba *hba); 321*dd11376bSBart Van Assche int (*suspend)(struct ufs_hba *, enum ufs_pm_op, 322*dd11376bSBart Van Assche enum ufs_notify_change_status); 323*dd11376bSBart Van Assche int (*resume)(struct ufs_hba *, enum ufs_pm_op); 324*dd11376bSBart Van Assche void (*dbg_register_dump)(struct ufs_hba *hba); 325*dd11376bSBart Van Assche int (*phy_initialization)(struct ufs_hba *); 326*dd11376bSBart Van Assche int (*device_reset)(struct ufs_hba *hba); 327*dd11376bSBart Van Assche void (*config_scaling_param)(struct ufs_hba *hba, 328*dd11376bSBart Van Assche struct devfreq_dev_profile *profile, 329*dd11376bSBart Van Assche struct devfreq_simple_ondemand_data *data); 330*dd11376bSBart Van Assche int (*program_key)(struct ufs_hba *hba, 331*dd11376bSBart Van Assche const union ufs_crypto_cfg_entry *cfg, int slot); 332*dd11376bSBart Van Assche void (*event_notify)(struct ufs_hba *hba, 333*dd11376bSBart Van Assche enum ufs_event_type evt, void *data); 334*dd11376bSBart Van Assche }; 335*dd11376bSBart Van Assche 336*dd11376bSBart Van Assche /* clock gating state */ 337*dd11376bSBart Van Assche enum clk_gating_state { 338*dd11376bSBart Van Assche CLKS_OFF, 339*dd11376bSBart Van Assche CLKS_ON, 340*dd11376bSBart Van Assche REQ_CLKS_OFF, 341*dd11376bSBart Van Assche REQ_CLKS_ON, 342*dd11376bSBart Van Assche }; 343*dd11376bSBart Van Assche 344*dd11376bSBart Van Assche /** 345*dd11376bSBart Van Assche * struct ufs_clk_gating - UFS clock gating related info 346*dd11376bSBart Van Assche * @gate_work: worker to turn off clocks after some delay as specified in 347*dd11376bSBart Van Assche * delay_ms 348*dd11376bSBart Van Assche * @ungate_work: worker to turn on clocks that will be used in case of 349*dd11376bSBart Van Assche * interrupt context 350*dd11376bSBart Van Assche * @state: the current clocks state 351*dd11376bSBart Van Assche * @delay_ms: gating delay in ms 352*dd11376bSBart Van Assche * @is_suspended: clk gating is suspended when set to 1 which can be used 353*dd11376bSBart Van Assche * during suspend/resume 354*dd11376bSBart Van Assche * @delay_attr: sysfs attribute to control delay_attr 355*dd11376bSBart Van Assche * @enable_attr: sysfs attribute to enable/disable clock gating 356*dd11376bSBart Van Assche * @is_enabled: Indicates the current status of clock gating 357*dd11376bSBart Van Assche * @is_initialized: Indicates whether clock gating is initialized or not 358*dd11376bSBart Van Assche * @active_reqs: number of requests that are pending and should be waited for 359*dd11376bSBart Van Assche * completion before gating clocks. 360*dd11376bSBart Van Assche * @clk_gating_workq: workqueue for clock gating work. 361*dd11376bSBart Van Assche */ 362*dd11376bSBart Van Assche struct ufs_clk_gating { 363*dd11376bSBart Van Assche struct delayed_work gate_work; 364*dd11376bSBart Van Assche struct work_struct ungate_work; 365*dd11376bSBart Van Assche enum clk_gating_state state; 366*dd11376bSBart Van Assche unsigned long delay_ms; 367*dd11376bSBart Van Assche bool is_suspended; 368*dd11376bSBart Van Assche struct device_attribute delay_attr; 369*dd11376bSBart Van Assche struct device_attribute enable_attr; 370*dd11376bSBart Van Assche bool is_enabled; 371*dd11376bSBart Van Assche bool is_initialized; 372*dd11376bSBart Van Assche int active_reqs; 373*dd11376bSBart Van Assche struct workqueue_struct *clk_gating_workq; 374*dd11376bSBart Van Assche }; 375*dd11376bSBart Van Assche 376*dd11376bSBart Van Assche struct ufs_saved_pwr_info { 377*dd11376bSBart Van Assche struct ufs_pa_layer_attr info; 378*dd11376bSBart Van Assche bool is_valid; 379*dd11376bSBart Van Assche }; 380*dd11376bSBart Van Assche 381*dd11376bSBart Van Assche /** 382*dd11376bSBart Van Assche * struct ufs_clk_scaling - UFS clock scaling related data 383*dd11376bSBart Van Assche * @active_reqs: number of requests that are pending. If this is zero when 384*dd11376bSBart Van Assche * devfreq ->target() function is called then schedule "suspend_work" to 385*dd11376bSBart Van Assche * suspend devfreq. 386*dd11376bSBart Van Assche * @tot_busy_t: Total busy time in current polling window 387*dd11376bSBart Van Assche * @window_start_t: Start time (in jiffies) of the current polling window 388*dd11376bSBart Van Assche * @busy_start_t: Start time of current busy period 389*dd11376bSBart Van Assche * @enable_attr: sysfs attribute to enable/disable clock scaling 390*dd11376bSBart Van Assche * @saved_pwr_info: UFS power mode may also be changed during scaling and this 391*dd11376bSBart Van Assche * one keeps track of previous power mode. 392*dd11376bSBart Van Assche * @workq: workqueue to schedule devfreq suspend/resume work 393*dd11376bSBart Van Assche * @suspend_work: worker to suspend devfreq 394*dd11376bSBart Van Assche * @resume_work: worker to resume devfreq 395*dd11376bSBart Van Assche * @min_gear: lowest HS gear to scale down to 396*dd11376bSBart Van Assche * @is_enabled: tracks if scaling is currently enabled or not, controlled by 397*dd11376bSBart Van Assche * clkscale_enable sysfs node 398*dd11376bSBart Van Assche * @is_allowed: tracks if scaling is currently allowed or not, used to block 399*dd11376bSBart Van Assche * clock scaling which is not invoked from devfreq governor 400*dd11376bSBart Van Assche * @is_initialized: Indicates whether clock scaling is initialized or not 401*dd11376bSBart Van Assche * @is_busy_started: tracks if busy period has started or not 402*dd11376bSBart Van Assche * @is_suspended: tracks if devfreq is suspended or not 403*dd11376bSBart Van Assche */ 404*dd11376bSBart Van Assche struct ufs_clk_scaling { 405*dd11376bSBart Van Assche int active_reqs; 406*dd11376bSBart Van Assche unsigned long tot_busy_t; 407*dd11376bSBart Van Assche ktime_t window_start_t; 408*dd11376bSBart Van Assche ktime_t busy_start_t; 409*dd11376bSBart Van Assche struct device_attribute enable_attr; 410*dd11376bSBart Van Assche struct ufs_saved_pwr_info saved_pwr_info; 411*dd11376bSBart Van Assche struct workqueue_struct *workq; 412*dd11376bSBart Van Assche struct work_struct suspend_work; 413*dd11376bSBart Van Assche struct work_struct resume_work; 414*dd11376bSBart Van Assche u32 min_gear; 415*dd11376bSBart Van Assche bool is_enabled; 416*dd11376bSBart Van Assche bool is_allowed; 417*dd11376bSBart Van Assche bool is_initialized; 418*dd11376bSBart Van Assche bool is_busy_started; 419*dd11376bSBart Van Assche bool is_suspended; 420*dd11376bSBart Van Assche }; 421*dd11376bSBart Van Assche 422*dd11376bSBart Van Assche #define UFS_EVENT_HIST_LENGTH 8 423*dd11376bSBart Van Assche /** 424*dd11376bSBart Van Assche * struct ufs_event_hist - keeps history of errors 425*dd11376bSBart Van Assche * @pos: index to indicate cyclic buffer position 426*dd11376bSBart Van Assche * @val: cyclic buffer for registers value 427*dd11376bSBart Van Assche * @tstamp: cyclic buffer for time stamp 428*dd11376bSBart Van Assche * @cnt: error counter 429*dd11376bSBart Van Assche */ 430*dd11376bSBart Van Assche struct ufs_event_hist { 431*dd11376bSBart Van Assche int pos; 432*dd11376bSBart Van Assche u32 val[UFS_EVENT_HIST_LENGTH]; 433*dd11376bSBart Van Assche ktime_t tstamp[UFS_EVENT_HIST_LENGTH]; 434*dd11376bSBart Van Assche unsigned long long cnt; 435*dd11376bSBart Van Assche }; 436*dd11376bSBart Van Assche 437*dd11376bSBart Van Assche /** 438*dd11376bSBart Van Assche * struct ufs_stats - keeps usage/err statistics 439*dd11376bSBart Van Assche * @last_intr_status: record the last interrupt status. 440*dd11376bSBart Van Assche * @last_intr_ts: record the last interrupt timestamp. 441*dd11376bSBart Van Assche * @hibern8_exit_cnt: Counter to keep track of number of exits, 442*dd11376bSBart Van Assche * reset this after link-startup. 443*dd11376bSBart Van Assche * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. 444*dd11376bSBart Van Assche * Clear after the first successful command completion. 445*dd11376bSBart Van Assche * @event: array with event history. 446*dd11376bSBart Van Assche */ 447*dd11376bSBart Van Assche struct ufs_stats { 448*dd11376bSBart Van Assche u32 last_intr_status; 449*dd11376bSBart Van Assche ktime_t last_intr_ts; 450*dd11376bSBart Van Assche 451*dd11376bSBart Van Assche u32 hibern8_exit_cnt; 452*dd11376bSBart Van Assche ktime_t last_hibern8_exit_tstamp; 453*dd11376bSBart Van Assche struct ufs_event_hist event[UFS_EVT_CNT]; 454*dd11376bSBart Van Assche }; 455*dd11376bSBart Van Assche 456*dd11376bSBart Van Assche /** 457*dd11376bSBart Van Assche * enum ufshcd_state - UFS host controller state 458*dd11376bSBart Van Assche * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command 459*dd11376bSBart Van Assche * processing. 460*dd11376bSBart Van Assche * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process 461*dd11376bSBart Van Assche * SCSI commands. 462*dd11376bSBart Van Assche * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. 463*dd11376bSBart Van Assche * SCSI commands may be submitted to the controller. 464*dd11376bSBart Van Assche * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail 465*dd11376bSBart Van Assche * newly submitted SCSI commands with error code DID_BAD_TARGET. 466*dd11376bSBart Van Assche * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery 467*dd11376bSBart Van Assche * failed. Fail all SCSI commands with error code DID_ERROR. 468*dd11376bSBart Van Assche */ 469*dd11376bSBart Van Assche enum ufshcd_state { 470*dd11376bSBart Van Assche UFSHCD_STATE_RESET, 471*dd11376bSBart Van Assche UFSHCD_STATE_OPERATIONAL, 472*dd11376bSBart Van Assche UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, 473*dd11376bSBart Van Assche UFSHCD_STATE_EH_SCHEDULED_FATAL, 474*dd11376bSBart Van Assche UFSHCD_STATE_ERROR, 475*dd11376bSBart Van Assche }; 476*dd11376bSBart Van Assche 477*dd11376bSBart Van Assche enum ufshcd_quirks { 478*dd11376bSBart Van Assche /* Interrupt aggregation support is broken */ 479*dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, 480*dd11376bSBart Van Assche 481*dd11376bSBart Van Assche /* 482*dd11376bSBart Van Assche * delay before each dme command is required as the unipro 483*dd11376bSBart Van Assche * layer has shown instabilities 484*dd11376bSBart Van Assche */ 485*dd11376bSBart Van Assche UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, 486*dd11376bSBart Van Assche 487*dd11376bSBart Van Assche /* 488*dd11376bSBart Van Assche * If UFS host controller is having issue in processing LCC (Line 489*dd11376bSBart Van Assche * Control Command) coming from device then enable this quirk. 490*dd11376bSBart Van Assche * When this quirk is enabled, host controller driver should disable 491*dd11376bSBart Van Assche * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 492*dd11376bSBart Van Assche * attribute of device to 0). 493*dd11376bSBart Van Assche */ 494*dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, 495*dd11376bSBart Van Assche 496*dd11376bSBart Van Assche /* 497*dd11376bSBart Van Assche * The attribute PA_RXHSUNTERMCAP specifies whether or not the 498*dd11376bSBart Van Assche * inbound Link supports unterminated line in HS mode. Setting this 499*dd11376bSBart Van Assche * attribute to 1 fixes moving to HS gear. 500*dd11376bSBart Van Assche */ 501*dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, 502*dd11376bSBart Van Assche 503*dd11376bSBart Van Assche /* 504*dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller only allows 505*dd11376bSBart Van Assche * accessing the peer dme attributes in AUTO mode (FAST AUTO or 506*dd11376bSBart Van Assche * SLOW AUTO). 507*dd11376bSBart Van Assche */ 508*dd11376bSBart Van Assche UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, 509*dd11376bSBart Van Assche 510*dd11376bSBart Van Assche /* 511*dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller doesn't 512*dd11376bSBart Van Assche * advertise the correct version in UFS_VER register. If this quirk 513*dd11376bSBart Van Assche * is enabled, standard UFS host driver will call the vendor specific 514*dd11376bSBart Van Assche * ops (get_ufs_hci_version) to get the correct version. 515*dd11376bSBart Van Assche */ 516*dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, 517*dd11376bSBart Van Assche 518*dd11376bSBart Van Assche /* 519*dd11376bSBart Van Assche * Clear handling for transfer/task request list is just opposite. 520*dd11376bSBart Van Assche */ 521*dd11376bSBart Van Assche UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, 522*dd11376bSBart Van Assche 523*dd11376bSBart Van Assche /* 524*dd11376bSBart Van Assche * This quirk needs to be enabled if host controller doesn't allow 525*dd11376bSBart Van Assche * that the interrupt aggregation timer and counter are reset by s/w. 526*dd11376bSBart Van Assche */ 527*dd11376bSBart Van Assche UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, 528*dd11376bSBart Van Assche 529*dd11376bSBart Van Assche /* 530*dd11376bSBart Van Assche * This quirks needs to be enabled if host controller cannot be 531*dd11376bSBart Van Assche * enabled via HCE register. 532*dd11376bSBart Van Assche */ 533*dd11376bSBart Van Assche UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, 534*dd11376bSBart Van Assche 535*dd11376bSBart Van Assche /* 536*dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller regards 537*dd11376bSBart Van Assche * resolution of the values of PRDTO and PRDTL in UTRD as byte. 538*dd11376bSBart Van Assche */ 539*dd11376bSBart Van Assche UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, 540*dd11376bSBart Van Assche 541*dd11376bSBart Van Assche /* 542*dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller reports 543*dd11376bSBart Van Assche * OCS FATAL ERROR with device error through sense data 544*dd11376bSBart Van Assche */ 545*dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, 546*dd11376bSBart Van Assche 547*dd11376bSBart Van Assche /* 548*dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller has 549*dd11376bSBart Van Assche * auto-hibernate capability but it doesn't work. 550*dd11376bSBart Van Assche */ 551*dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, 552*dd11376bSBart Van Assche 553*dd11376bSBart Van Assche /* 554*dd11376bSBart Van Assche * This quirk needs to disable manual flush for write booster 555*dd11376bSBart Van Assche */ 556*dd11376bSBart Van Assche UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, 557*dd11376bSBart Van Assche 558*dd11376bSBart Van Assche /* 559*dd11376bSBart Van Assche * This quirk needs to disable unipro timeout values 560*dd11376bSBart Van Assche * before power mode change 561*dd11376bSBart Van Assche */ 562*dd11376bSBart Van Assche UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, 563*dd11376bSBart Van Assche 564*dd11376bSBart Van Assche /* 565*dd11376bSBart Van Assche * This quirk allows only sg entries aligned with page size. 566*dd11376bSBart Van Assche */ 567*dd11376bSBart Van Assche UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE = 1 << 14, 568*dd11376bSBart Van Assche 569*dd11376bSBart Van Assche /* 570*dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller does not 571*dd11376bSBart Van Assche * support UIC command 572*dd11376bSBart Van Assche */ 573*dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, 574*dd11376bSBart Van Assche 575*dd11376bSBart Van Assche /* 576*dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller cannot 577*dd11376bSBart Van Assche * support physical host configuration. 578*dd11376bSBart Van Assche */ 579*dd11376bSBart Van Assche UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, 580*dd11376bSBart Van Assche }; 581*dd11376bSBart Van Assche 582*dd11376bSBart Van Assche enum ufshcd_caps { 583*dd11376bSBart Van Assche /* Allow dynamic clk gating */ 584*dd11376bSBart Van Assche UFSHCD_CAP_CLK_GATING = 1 << 0, 585*dd11376bSBart Van Assche 586*dd11376bSBart Van Assche /* Allow hiberb8 with clk gating */ 587*dd11376bSBart Van Assche UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, 588*dd11376bSBart Van Assche 589*dd11376bSBart Van Assche /* Allow dynamic clk scaling */ 590*dd11376bSBart Van Assche UFSHCD_CAP_CLK_SCALING = 1 << 2, 591*dd11376bSBart Van Assche 592*dd11376bSBart Van Assche /* Allow auto bkops to enabled during runtime suspend */ 593*dd11376bSBart Van Assche UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, 594*dd11376bSBart Van Assche 595*dd11376bSBart Van Assche /* 596*dd11376bSBart Van Assche * This capability allows host controller driver to use the UFS HCI's 597*dd11376bSBart Van Assche * interrupt aggregation capability. 598*dd11376bSBart Van Assche * CAUTION: Enabling this might reduce overall UFS throughput. 599*dd11376bSBart Van Assche */ 600*dd11376bSBart Van Assche UFSHCD_CAP_INTR_AGGR = 1 << 4, 601*dd11376bSBart Van Assche 602*dd11376bSBart Van Assche /* 603*dd11376bSBart Van Assche * This capability allows the device auto-bkops to be always enabled 604*dd11376bSBart Van Assche * except during suspend (both runtime and suspend). 605*dd11376bSBart Van Assche * Enabling this capability means that device will always be allowed 606*dd11376bSBart Van Assche * to do background operation when it's active but it might degrade 607*dd11376bSBart Van Assche * the performance of ongoing read/write operations. 608*dd11376bSBart Van Assche */ 609*dd11376bSBart Van Assche UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, 610*dd11376bSBart Van Assche 611*dd11376bSBart Van Assche /* 612*dd11376bSBart Van Assche * This capability allows host controller driver to automatically 613*dd11376bSBart Van Assche * enable runtime power management by itself instead of waiting 614*dd11376bSBart Van Assche * for userspace to control the power management. 615*dd11376bSBart Van Assche */ 616*dd11376bSBart Van Assche UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, 617*dd11376bSBart Van Assche 618*dd11376bSBart Van Assche /* 619*dd11376bSBart Van Assche * This capability allows the host controller driver to turn-on 620*dd11376bSBart Van Assche * WriteBooster, if the underlying device supports it and is 621*dd11376bSBart Van Assche * provisioned to be used. This would increase the write performance. 622*dd11376bSBart Van Assche */ 623*dd11376bSBart Van Assche UFSHCD_CAP_WB_EN = 1 << 7, 624*dd11376bSBart Van Assche 625*dd11376bSBart Van Assche /* 626*dd11376bSBart Van Assche * This capability allows the host controller driver to use the 627*dd11376bSBart Van Assche * inline crypto engine, if it is present 628*dd11376bSBart Van Assche */ 629*dd11376bSBart Van Assche UFSHCD_CAP_CRYPTO = 1 << 8, 630*dd11376bSBart Van Assche 631*dd11376bSBart Van Assche /* 632*dd11376bSBart Van Assche * This capability allows the controller regulators to be put into 633*dd11376bSBart Van Assche * lpm mode aggressively during clock gating. 634*dd11376bSBart Van Assche * This would increase power savings. 635*dd11376bSBart Van Assche */ 636*dd11376bSBart Van Assche UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, 637*dd11376bSBart Van Assche 638*dd11376bSBart Van Assche /* 639*dd11376bSBart Van Assche * This capability allows the host controller driver to use DeepSleep, 640*dd11376bSBart Van Assche * if it is supported by the UFS device. The host controller driver must 641*dd11376bSBart Van Assche * support device hardware reset via the hba->device_reset() callback, 642*dd11376bSBart Van Assche * in order to exit DeepSleep state. 643*dd11376bSBart Van Assche */ 644*dd11376bSBart Van Assche UFSHCD_CAP_DEEPSLEEP = 1 << 10, 645*dd11376bSBart Van Assche 646*dd11376bSBart Van Assche /* 647*dd11376bSBart Van Assche * This capability allows the host controller driver to use temperature 648*dd11376bSBart Van Assche * notification if it is supported by the UFS device. 649*dd11376bSBart Van Assche */ 650*dd11376bSBart Van Assche UFSHCD_CAP_TEMP_NOTIF = 1 << 11, 651*dd11376bSBart Van Assche }; 652*dd11376bSBart Van Assche 653*dd11376bSBart Van Assche struct ufs_hba_variant_params { 654*dd11376bSBart Van Assche struct devfreq_dev_profile devfreq_profile; 655*dd11376bSBart Van Assche struct devfreq_simple_ondemand_data ondemand_data; 656*dd11376bSBart Van Assche u16 hba_enable_delay_us; 657*dd11376bSBart Van Assche u32 wb_flush_threshold; 658*dd11376bSBart Van Assche }; 659*dd11376bSBart Van Assche 660*dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_HPB 661*dd11376bSBart Van Assche /** 662*dd11376bSBart Van Assche * struct ufshpb_dev_info - UFSHPB device related info 663*dd11376bSBart Van Assche * @num_lu: the number of user logical unit to check whether all lu finished 664*dd11376bSBart Van Assche * initialization 665*dd11376bSBart Van Assche * @rgn_size: device reported HPB region size 666*dd11376bSBart Van Assche * @srgn_size: device reported HPB sub-region size 667*dd11376bSBart Van Assche * @slave_conf_cnt: counter to check all lu finished initialization 668*dd11376bSBart Van Assche * @hpb_disabled: flag to check if HPB is disabled 669*dd11376bSBart Van Assche * @max_hpb_single_cmd: device reported bMAX_DATA_SIZE_FOR_SINGLE_CMD value 670*dd11376bSBart Van Assche * @is_legacy: flag to check HPB 1.0 671*dd11376bSBart Van Assche * @control_mode: either host or device 672*dd11376bSBart Van Assche */ 673*dd11376bSBart Van Assche struct ufshpb_dev_info { 674*dd11376bSBart Van Assche int num_lu; 675*dd11376bSBart Van Assche int rgn_size; 676*dd11376bSBart Van Assche int srgn_size; 677*dd11376bSBart Van Assche atomic_t slave_conf_cnt; 678*dd11376bSBart Van Assche bool hpb_disabled; 679*dd11376bSBart Van Assche u8 max_hpb_single_cmd; 680*dd11376bSBart Van Assche bool is_legacy; 681*dd11376bSBart Van Assche u8 control_mode; 682*dd11376bSBart Van Assche }; 683*dd11376bSBart Van Assche #endif 684*dd11376bSBart Van Assche 685*dd11376bSBart Van Assche struct ufs_hba_monitor { 686*dd11376bSBart Van Assche unsigned long chunk_size; 687*dd11376bSBart Van Assche 688*dd11376bSBart Van Assche unsigned long nr_sec_rw[2]; 689*dd11376bSBart Van Assche ktime_t total_busy[2]; 690*dd11376bSBart Van Assche 691*dd11376bSBart Van Assche unsigned long nr_req[2]; 692*dd11376bSBart Van Assche /* latencies*/ 693*dd11376bSBart Van Assche ktime_t lat_sum[2]; 694*dd11376bSBart Van Assche ktime_t lat_max[2]; 695*dd11376bSBart Van Assche ktime_t lat_min[2]; 696*dd11376bSBart Van Assche 697*dd11376bSBart Van Assche u32 nr_queued[2]; 698*dd11376bSBart Van Assche ktime_t busy_start_ts[2]; 699*dd11376bSBart Van Assche 700*dd11376bSBart Van Assche ktime_t enabled_ts; 701*dd11376bSBart Van Assche bool enabled; 702*dd11376bSBart Van Assche }; 703*dd11376bSBart Van Assche 704*dd11376bSBart Van Assche /** 705*dd11376bSBart Van Assche * struct ufs_hba - per adapter private structure 706*dd11376bSBart Van Assche * @mmio_base: UFSHCI base register address 707*dd11376bSBart Van Assche * @ucdl_base_addr: UFS Command Descriptor base address 708*dd11376bSBart Van Assche * @utrdl_base_addr: UTP Transfer Request Descriptor base address 709*dd11376bSBart Van Assche * @utmrdl_base_addr: UTP Task Management Descriptor base address 710*dd11376bSBart Van Assche * @ucdl_dma_addr: UFS Command Descriptor DMA address 711*dd11376bSBart Van Assche * @utrdl_dma_addr: UTRDL DMA address 712*dd11376bSBart Van Assche * @utmrdl_dma_addr: UTMRDL DMA address 713*dd11376bSBart Van Assche * @host: Scsi_Host instance of the driver 714*dd11376bSBart Van Assche * @dev: device handle 715*dd11376bSBart Van Assche * @ufs_device_wlun: WLUN that controls the entire UFS device. 716*dd11376bSBart Van Assche * @hwmon_device: device instance registered with the hwmon core. 717*dd11376bSBart Van Assche * @curr_dev_pwr_mode: active UFS device power mode. 718*dd11376bSBart Van Assche * @uic_link_state: active state of the link to the UFS device. 719*dd11376bSBart Van Assche * @rpm_lvl: desired UFS power management level during runtime PM. 720*dd11376bSBart Van Assche * @spm_lvl: desired UFS power management level during system PM. 721*dd11376bSBart Van Assche * @pm_op_in_progress: whether or not a PM operation is in progress. 722*dd11376bSBart Van Assche * @ahit: value of Auto-Hibernate Idle Timer register. 723*dd11376bSBart Van Assche * @lrb: local reference block 724*dd11376bSBart Van Assche * @outstanding_tasks: Bits representing outstanding task requests 725*dd11376bSBart Van Assche * @outstanding_lock: Protects @outstanding_reqs. 726*dd11376bSBart Van Assche * @outstanding_reqs: Bits representing outstanding transfer requests 727*dd11376bSBart Van Assche * @capabilities: UFS Controller Capabilities 728*dd11376bSBart Van Assche * @nutrs: Transfer Request Queue depth supported by controller 729*dd11376bSBart Van Assche * @nutmrs: Task Management Queue depth supported by controller 730*dd11376bSBart Van Assche * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. 731*dd11376bSBart Van Assche * @ufs_version: UFS Version to which controller complies 732*dd11376bSBart Van Assche * @vops: pointer to variant specific operations 733*dd11376bSBart Van Assche * @vps: pointer to variant specific parameters 734*dd11376bSBart Van Assche * @priv: pointer to variant specific private data 735*dd11376bSBart Van Assche * @irq: Irq number of the controller 736*dd11376bSBart Van Assche * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. 737*dd11376bSBart Van Assche * @dev_ref_clk_freq: reference clock frequency 738*dd11376bSBart Van Assche * @quirks: bitmask with information about deviations from the UFSHCI standard. 739*dd11376bSBart Van Assche * @dev_quirks: bitmask with information about deviations from the UFS standard. 740*dd11376bSBart Van Assche * @tmf_tag_set: TMF tag set. 741*dd11376bSBart Van Assche * @tmf_queue: Used to allocate TMF tags. 742*dd11376bSBart Van Assche * @tmf_rqs: array with pointers to TMF requests while these are in progress. 743*dd11376bSBart Van Assche * @active_uic_cmd: handle of active UIC command 744*dd11376bSBart Van Assche * @uic_cmd_mutex: mutex for UIC command 745*dd11376bSBart Van Assche * @uic_async_done: completion used during UIC processing 746*dd11376bSBart Van Assche * @ufshcd_state: UFSHCD state 747*dd11376bSBart Van Assche * @eh_flags: Error handling flags 748*dd11376bSBart Van Assche * @intr_mask: Interrupt Mask Bits 749*dd11376bSBart Van Assche * @ee_ctrl_mask: Exception event control mask 750*dd11376bSBart Van Assche * @ee_drv_mask: Exception event mask for driver 751*dd11376bSBart Van Assche * @ee_usr_mask: Exception event mask for user (set via debugfs) 752*dd11376bSBart Van Assche * @ee_ctrl_mutex: Used to serialize exception event information. 753*dd11376bSBart Van Assche * @is_powered: flag to check if HBA is powered 754*dd11376bSBart Van Assche * @shutting_down: flag to check if shutdown has been invoked 755*dd11376bSBart Van Assche * @host_sem: semaphore used to serialize concurrent contexts 756*dd11376bSBart Van Assche * @eh_wq: Workqueue that eh_work works on 757*dd11376bSBart Van Assche * @eh_work: Worker to handle UFS errors that require s/w attention 758*dd11376bSBart Van Assche * @eeh_work: Worker to handle exception events 759*dd11376bSBart Van Assche * @errors: HBA errors 760*dd11376bSBart Van Assche * @uic_error: UFS interconnect layer error status 761*dd11376bSBart Van Assche * @saved_err: sticky error mask 762*dd11376bSBart Van Assche * @saved_uic_err: sticky UIC error mask 763*dd11376bSBart Van Assche * @ufs_stats: various error counters 764*dd11376bSBart Van Assche * @force_reset: flag to force eh_work perform a full reset 765*dd11376bSBart Van Assche * @force_pmc: flag to force a power mode change 766*dd11376bSBart Van Assche * @silence_err_logs: flag to silence error logs 767*dd11376bSBart Van Assche * @dev_cmd: ufs device management command information 768*dd11376bSBart Van Assche * @last_dme_cmd_tstamp: time stamp of the last completed DME command 769*dd11376bSBart Van Assche * @nop_out_timeout: NOP OUT timeout value 770*dd11376bSBart Van Assche * @dev_info: information about the UFS device 771*dd11376bSBart Van Assche * @auto_bkops_enabled: to track whether bkops is enabled in device 772*dd11376bSBart Van Assche * @vreg_info: UFS device voltage regulator information 773*dd11376bSBart Van Assche * @clk_list_head: UFS host controller clocks list node head 774*dd11376bSBart Van Assche * @req_abort_count: number of times ufshcd_abort() has been called 775*dd11376bSBart Van Assche * @lanes_per_direction: number of lanes per data direction between the UFS 776*dd11376bSBart Van Assche * controller and the UFS device. 777*dd11376bSBart Van Assche * @pwr_info: holds current power mode 778*dd11376bSBart Van Assche * @max_pwr_info: keeps the device max valid pwm 779*dd11376bSBart Van Assche * @clk_gating: information related to clock gating 780*dd11376bSBart Van Assche * @caps: bitmask with information about UFS controller capabilities 781*dd11376bSBart Van Assche * @devfreq: frequency scaling information owned by the devfreq core 782*dd11376bSBart Van Assche * @clk_scaling: frequency scaling information owned by the UFS driver 783*dd11376bSBart Van Assche * @is_sys_suspended: whether or not the entire system has been suspended 784*dd11376bSBart Van Assche * @urgent_bkops_lvl: keeps track of urgent bkops level for device 785*dd11376bSBart Van Assche * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for 786*dd11376bSBart Van Assche * device is known or not. 787*dd11376bSBart Van Assche * @clk_scaling_lock: used to serialize device commands and clock scaling 788*dd11376bSBart Van Assche * @desc_size: descriptor sizes reported by device 789*dd11376bSBart Van Assche * @scsi_block_reqs_cnt: reference counting for scsi block requests 790*dd11376bSBart Van Assche * @bsg_dev: struct device associated with the BSG queue 791*dd11376bSBart Van Assche * @bsg_queue: BSG queue associated with the UFS controller 792*dd11376bSBart Van Assche * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power 793*dd11376bSBart Van Assche * management) after the UFS device has finished a WriteBooster buffer 794*dd11376bSBart Van Assche * flush or auto BKOP. 795*dd11376bSBart Van Assche * @ufshpb_dev: information related to HPB (Host Performance Booster). 796*dd11376bSBart Van Assche * @monitor: statistics about UFS commands 797*dd11376bSBart Van Assche * @crypto_capabilities: Content of crypto capabilities register (0x100) 798*dd11376bSBart Van Assche * @crypto_cap_array: Array of crypto capabilities 799*dd11376bSBart Van Assche * @crypto_cfg_register: Start of the crypto cfg array 800*dd11376bSBart Van Assche * @crypto_profile: the crypto profile of this hba (if applicable) 801*dd11376bSBart Van Assche * @debugfs_root: UFS controller debugfs root directory 802*dd11376bSBart Van Assche * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay 803*dd11376bSBart Van Assche * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore 804*dd11376bSBart Van Assche * ee_ctrl_mask 805*dd11376bSBart Van Assche * @luns_avail: number of regular and well known LUNs supported by the UFS 806*dd11376bSBart Van Assche * device 807*dd11376bSBart Van Assche * @complete_put: whether or not to call ufshcd_rpm_put() from inside 808*dd11376bSBart Van Assche * ufshcd_resume_complete() 809*dd11376bSBart Van Assche */ 810*dd11376bSBart Van Assche struct ufs_hba { 811*dd11376bSBart Van Assche void __iomem *mmio_base; 812*dd11376bSBart Van Assche 813*dd11376bSBart Van Assche /* Virtual memory reference */ 814*dd11376bSBart Van Assche struct utp_transfer_cmd_desc *ucdl_base_addr; 815*dd11376bSBart Van Assche struct utp_transfer_req_desc *utrdl_base_addr; 816*dd11376bSBart Van Assche struct utp_task_req_desc *utmrdl_base_addr; 817*dd11376bSBart Van Assche 818*dd11376bSBart Van Assche /* DMA memory reference */ 819*dd11376bSBart Van Assche dma_addr_t ucdl_dma_addr; 820*dd11376bSBart Van Assche dma_addr_t utrdl_dma_addr; 821*dd11376bSBart Van Assche dma_addr_t utmrdl_dma_addr; 822*dd11376bSBart Van Assche 823*dd11376bSBart Van Assche struct Scsi_Host *host; 824*dd11376bSBart Van Assche struct device *dev; 825*dd11376bSBart Van Assche struct scsi_device *ufs_device_wlun; 826*dd11376bSBart Van Assche 827*dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_HWMON 828*dd11376bSBart Van Assche struct device *hwmon_device; 829*dd11376bSBart Van Assche #endif 830*dd11376bSBart Van Assche 831*dd11376bSBart Van Assche enum ufs_dev_pwr_mode curr_dev_pwr_mode; 832*dd11376bSBart Van Assche enum uic_link_state uic_link_state; 833*dd11376bSBart Van Assche /* Desired UFS power management level during runtime PM */ 834*dd11376bSBart Van Assche enum ufs_pm_level rpm_lvl; 835*dd11376bSBart Van Assche /* Desired UFS power management level during system PM */ 836*dd11376bSBart Van Assche enum ufs_pm_level spm_lvl; 837*dd11376bSBart Van Assche int pm_op_in_progress; 838*dd11376bSBart Van Assche 839*dd11376bSBart Van Assche /* Auto-Hibernate Idle Timer register value */ 840*dd11376bSBart Van Assche u32 ahit; 841*dd11376bSBart Van Assche 842*dd11376bSBart Van Assche struct ufshcd_lrb *lrb; 843*dd11376bSBart Van Assche 844*dd11376bSBart Van Assche unsigned long outstanding_tasks; 845*dd11376bSBart Van Assche spinlock_t outstanding_lock; 846*dd11376bSBart Van Assche unsigned long outstanding_reqs; 847*dd11376bSBart Van Assche 848*dd11376bSBart Van Assche u32 capabilities; 849*dd11376bSBart Van Assche int nutrs; 850*dd11376bSBart Van Assche int nutmrs; 851*dd11376bSBart Van Assche u32 reserved_slot; 852*dd11376bSBart Van Assche u32 ufs_version; 853*dd11376bSBart Van Assche const struct ufs_hba_variant_ops *vops; 854*dd11376bSBart Van Assche struct ufs_hba_variant_params *vps; 855*dd11376bSBart Van Assche void *priv; 856*dd11376bSBart Van Assche unsigned int irq; 857*dd11376bSBart Van Assche bool is_irq_enabled; 858*dd11376bSBart Van Assche enum ufs_ref_clk_freq dev_ref_clk_freq; 859*dd11376bSBart Van Assche 860*dd11376bSBart Van Assche unsigned int quirks; /* Deviations from standard UFSHCI spec. */ 861*dd11376bSBart Van Assche 862*dd11376bSBart Van Assche /* Device deviations from standard UFS device spec. */ 863*dd11376bSBart Van Assche unsigned int dev_quirks; 864*dd11376bSBart Van Assche 865*dd11376bSBart Van Assche struct blk_mq_tag_set tmf_tag_set; 866*dd11376bSBart Van Assche struct request_queue *tmf_queue; 867*dd11376bSBart Van Assche struct request **tmf_rqs; 868*dd11376bSBart Van Assche 869*dd11376bSBart Van Assche struct uic_command *active_uic_cmd; 870*dd11376bSBart Van Assche struct mutex uic_cmd_mutex; 871*dd11376bSBart Van Assche struct completion *uic_async_done; 872*dd11376bSBart Van Assche 873*dd11376bSBart Van Assche enum ufshcd_state ufshcd_state; 874*dd11376bSBart Van Assche u32 eh_flags; 875*dd11376bSBart Van Assche u32 intr_mask; 876*dd11376bSBart Van Assche u16 ee_ctrl_mask; 877*dd11376bSBart Van Assche u16 ee_drv_mask; 878*dd11376bSBart Van Assche u16 ee_usr_mask; 879*dd11376bSBart Van Assche struct mutex ee_ctrl_mutex; 880*dd11376bSBart Van Assche bool is_powered; 881*dd11376bSBart Van Assche bool shutting_down; 882*dd11376bSBart Van Assche struct semaphore host_sem; 883*dd11376bSBart Van Assche 884*dd11376bSBart Van Assche /* Work Queues */ 885*dd11376bSBart Van Assche struct workqueue_struct *eh_wq; 886*dd11376bSBart Van Assche struct work_struct eh_work; 887*dd11376bSBart Van Assche struct work_struct eeh_work; 888*dd11376bSBart Van Assche 889*dd11376bSBart Van Assche /* HBA Errors */ 890*dd11376bSBart Van Assche u32 errors; 891*dd11376bSBart Van Assche u32 uic_error; 892*dd11376bSBart Van Assche u32 saved_err; 893*dd11376bSBart Van Assche u32 saved_uic_err; 894*dd11376bSBart Van Assche struct ufs_stats ufs_stats; 895*dd11376bSBart Van Assche bool force_reset; 896*dd11376bSBart Van Assche bool force_pmc; 897*dd11376bSBart Van Assche bool silence_err_logs; 898*dd11376bSBart Van Assche 899*dd11376bSBart Van Assche /* Device management request data */ 900*dd11376bSBart Van Assche struct ufs_dev_cmd dev_cmd; 901*dd11376bSBart Van Assche ktime_t last_dme_cmd_tstamp; 902*dd11376bSBart Van Assche int nop_out_timeout; 903*dd11376bSBart Van Assche 904*dd11376bSBart Van Assche /* Keeps information of the UFS device connected to this host */ 905*dd11376bSBart Van Assche struct ufs_dev_info dev_info; 906*dd11376bSBart Van Assche bool auto_bkops_enabled; 907*dd11376bSBart Van Assche struct ufs_vreg_info vreg_info; 908*dd11376bSBart Van Assche struct list_head clk_list_head; 909*dd11376bSBart Van Assche 910*dd11376bSBart Van Assche /* Number of requests aborts */ 911*dd11376bSBart Van Assche int req_abort_count; 912*dd11376bSBart Van Assche 913*dd11376bSBart Van Assche /* Number of lanes available (1 or 2) for Rx/Tx */ 914*dd11376bSBart Van Assche u32 lanes_per_direction; 915*dd11376bSBart Van Assche struct ufs_pa_layer_attr pwr_info; 916*dd11376bSBart Van Assche struct ufs_pwr_mode_info max_pwr_info; 917*dd11376bSBart Van Assche 918*dd11376bSBart Van Assche struct ufs_clk_gating clk_gating; 919*dd11376bSBart Van Assche /* Control to enable/disable host capabilities */ 920*dd11376bSBart Van Assche u32 caps; 921*dd11376bSBart Van Assche 922*dd11376bSBart Van Assche struct devfreq *devfreq; 923*dd11376bSBart Van Assche struct ufs_clk_scaling clk_scaling; 924*dd11376bSBart Van Assche bool is_sys_suspended; 925*dd11376bSBart Van Assche 926*dd11376bSBart Van Assche enum bkops_status urgent_bkops_lvl; 927*dd11376bSBart Van Assche bool is_urgent_bkops_lvl_checked; 928*dd11376bSBart Van Assche 929*dd11376bSBart Van Assche struct rw_semaphore clk_scaling_lock; 930*dd11376bSBart Van Assche unsigned char desc_size[QUERY_DESC_IDN_MAX]; 931*dd11376bSBart Van Assche atomic_t scsi_block_reqs_cnt; 932*dd11376bSBart Van Assche 933*dd11376bSBart Van Assche struct device bsg_dev; 934*dd11376bSBart Van Assche struct request_queue *bsg_queue; 935*dd11376bSBart Van Assche struct delayed_work rpm_dev_flush_recheck_work; 936*dd11376bSBart Van Assche 937*dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_HPB 938*dd11376bSBart Van Assche struct ufshpb_dev_info ufshpb_dev; 939*dd11376bSBart Van Assche #endif 940*dd11376bSBart Van Assche 941*dd11376bSBart Van Assche struct ufs_hba_monitor monitor; 942*dd11376bSBart Van Assche 943*dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_CRYPTO 944*dd11376bSBart Van Assche union ufs_crypto_capabilities crypto_capabilities; 945*dd11376bSBart Van Assche union ufs_crypto_cap_entry *crypto_cap_array; 946*dd11376bSBart Van Assche u32 crypto_cfg_register; 947*dd11376bSBart Van Assche struct blk_crypto_profile crypto_profile; 948*dd11376bSBart Van Assche #endif 949*dd11376bSBart Van Assche #ifdef CONFIG_DEBUG_FS 950*dd11376bSBart Van Assche struct dentry *debugfs_root; 951*dd11376bSBart Van Assche struct delayed_work debugfs_ee_work; 952*dd11376bSBart Van Assche u32 debugfs_ee_rate_limit_ms; 953*dd11376bSBart Van Assche #endif 954*dd11376bSBart Van Assche u32 luns_avail; 955*dd11376bSBart Van Assche bool complete_put; 956*dd11376bSBart Van Assche }; 957*dd11376bSBart Van Assche 958*dd11376bSBart Van Assche /* Returns true if clocks can be gated. Otherwise false */ 959*dd11376bSBart Van Assche static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) 960*dd11376bSBart Van Assche { 961*dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_CLK_GATING; 962*dd11376bSBart Van Assche } 963*dd11376bSBart Van Assche static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) 964*dd11376bSBart Van Assche { 965*dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 966*dd11376bSBart Van Assche } 967*dd11376bSBart Van Assche static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) 968*dd11376bSBart Van Assche { 969*dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_CLK_SCALING; 970*dd11376bSBart Van Assche } 971*dd11376bSBart Van Assche static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) 972*dd11376bSBart Van Assche { 973*dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 974*dd11376bSBart Van Assche } 975*dd11376bSBart Van Assche static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) 976*dd11376bSBart Van Assche { 977*dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; 978*dd11376bSBart Van Assche } 979*dd11376bSBart Van Assche 980*dd11376bSBart Van Assche static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) 981*dd11376bSBart Van Assche { 982*dd11376bSBart Van Assche return (hba->caps & UFSHCD_CAP_INTR_AGGR) && 983*dd11376bSBart Van Assche !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); 984*dd11376bSBart Van Assche } 985*dd11376bSBart Van Assche 986*dd11376bSBart Van Assche static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) 987*dd11376bSBart Van Assche { 988*dd11376bSBart Van Assche return !!(ufshcd_is_link_hibern8(hba) && 989*dd11376bSBart Van Assche (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); 990*dd11376bSBart Van Assche } 991*dd11376bSBart Van Assche 992*dd11376bSBart Van Assche static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) 993*dd11376bSBart Van Assche { 994*dd11376bSBart Van Assche return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && 995*dd11376bSBart Van Assche !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); 996*dd11376bSBart Van Assche } 997*dd11376bSBart Van Assche 998*dd11376bSBart Van Assche static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) 999*dd11376bSBart Van Assche { 1000*dd11376bSBart Van Assche return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); 1001*dd11376bSBart Van Assche } 1002*dd11376bSBart Van Assche 1003*dd11376bSBart Van Assche static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) 1004*dd11376bSBart Van Assche { 1005*dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_WB_EN; 1006*dd11376bSBart Van Assche } 1007*dd11376bSBart Van Assche 1008*dd11376bSBart Van Assche #define ufshcd_writel(hba, val, reg) \ 1009*dd11376bSBart Van Assche writel((val), (hba)->mmio_base + (reg)) 1010*dd11376bSBart Van Assche #define ufshcd_readl(hba, reg) \ 1011*dd11376bSBart Van Assche readl((hba)->mmio_base + (reg)) 1012*dd11376bSBart Van Assche 1013*dd11376bSBart Van Assche /** 1014*dd11376bSBart Van Assche * ufshcd_rmwl - perform read/modify/write for a controller register 1015*dd11376bSBart Van Assche * @hba: per adapter instance 1016*dd11376bSBart Van Assche * @mask: mask to apply on read value 1017*dd11376bSBart Van Assche * @val: actual value to write 1018*dd11376bSBart Van Assche * @reg: register address 1019*dd11376bSBart Van Assche */ 1020*dd11376bSBart Van Assche static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) 1021*dd11376bSBart Van Assche { 1022*dd11376bSBart Van Assche u32 tmp; 1023*dd11376bSBart Van Assche 1024*dd11376bSBart Van Assche tmp = ufshcd_readl(hba, reg); 1025*dd11376bSBart Van Assche tmp &= ~mask; 1026*dd11376bSBart Van Assche tmp |= (val & mask); 1027*dd11376bSBart Van Assche ufshcd_writel(hba, tmp, reg); 1028*dd11376bSBart Van Assche } 1029*dd11376bSBart Van Assche 1030*dd11376bSBart Van Assche int ufshcd_alloc_host(struct device *, struct ufs_hba **); 1031*dd11376bSBart Van Assche void ufshcd_dealloc_host(struct ufs_hba *); 1032*dd11376bSBart Van Assche int ufshcd_hba_enable(struct ufs_hba *hba); 1033*dd11376bSBart Van Assche int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); 1034*dd11376bSBart Van Assche int ufshcd_link_recovery(struct ufs_hba *hba); 1035*dd11376bSBart Van Assche int ufshcd_make_hba_operational(struct ufs_hba *hba); 1036*dd11376bSBart Van Assche void ufshcd_remove(struct ufs_hba *); 1037*dd11376bSBart Van Assche int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); 1038*dd11376bSBart Van Assche int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); 1039*dd11376bSBart Van Assche void ufshcd_delay_us(unsigned long us, unsigned long tolerance); 1040*dd11376bSBart Van Assche void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); 1041*dd11376bSBart Van Assche void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); 1042*dd11376bSBart Van Assche void ufshcd_hba_stop(struct ufs_hba *hba); 1043*dd11376bSBart Van Assche void ufshcd_schedule_eh_work(struct ufs_hba *hba); 1044*dd11376bSBart Van Assche 1045*dd11376bSBart Van Assche static inline void check_upiu_size(void) 1046*dd11376bSBart Van Assche { 1047*dd11376bSBart Van Assche BUILD_BUG_ON(ALIGNED_UPIU_SIZE < 1048*dd11376bSBart Van Assche GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE); 1049*dd11376bSBart Van Assche } 1050*dd11376bSBart Van Assche 1051*dd11376bSBart Van Assche /** 1052*dd11376bSBart Van Assche * ufshcd_set_variant - set variant specific data to the hba 1053*dd11376bSBart Van Assche * @hba: per adapter instance 1054*dd11376bSBart Van Assche * @variant: pointer to variant specific data 1055*dd11376bSBart Van Assche */ 1056*dd11376bSBart Van Assche static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) 1057*dd11376bSBart Van Assche { 1058*dd11376bSBart Van Assche BUG_ON(!hba); 1059*dd11376bSBart Van Assche hba->priv = variant; 1060*dd11376bSBart Van Assche } 1061*dd11376bSBart Van Assche 1062*dd11376bSBart Van Assche /** 1063*dd11376bSBart Van Assche * ufshcd_get_variant - get variant specific data from the hba 1064*dd11376bSBart Van Assche * @hba: per adapter instance 1065*dd11376bSBart Van Assche */ 1066*dd11376bSBart Van Assche static inline void *ufshcd_get_variant(struct ufs_hba *hba) 1067*dd11376bSBart Van Assche { 1068*dd11376bSBart Van Assche BUG_ON(!hba); 1069*dd11376bSBart Van Assche return hba->priv; 1070*dd11376bSBart Van Assche } 1071*dd11376bSBart Van Assche 1072*dd11376bSBart Van Assche #ifdef CONFIG_PM 1073*dd11376bSBart Van Assche extern int ufshcd_runtime_suspend(struct device *dev); 1074*dd11376bSBart Van Assche extern int ufshcd_runtime_resume(struct device *dev); 1075*dd11376bSBart Van Assche #endif 1076*dd11376bSBart Van Assche #ifdef CONFIG_PM_SLEEP 1077*dd11376bSBart Van Assche extern int ufshcd_system_suspend(struct device *dev); 1078*dd11376bSBart Van Assche extern int ufshcd_system_resume(struct device *dev); 1079*dd11376bSBart Van Assche #endif 1080*dd11376bSBart Van Assche extern int ufshcd_shutdown(struct ufs_hba *hba); 1081*dd11376bSBart Van Assche extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 1082*dd11376bSBart Van Assche int agreed_gear, 1083*dd11376bSBart Van Assche int adapt_val); 1084*dd11376bSBart Van Assche extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 1085*dd11376bSBart Van Assche u8 attr_set, u32 mib_val, u8 peer); 1086*dd11376bSBart Van Assche extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 1087*dd11376bSBart Van Assche u32 *mib_val, u8 peer); 1088*dd11376bSBart Van Assche extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, 1089*dd11376bSBart Van Assche struct ufs_pa_layer_attr *desired_pwr_mode); 1090*dd11376bSBart Van Assche 1091*dd11376bSBart Van Assche /* UIC command interfaces for DME primitives */ 1092*dd11376bSBart Van Assche #define DME_LOCAL 0 1093*dd11376bSBart Van Assche #define DME_PEER 1 1094*dd11376bSBart Van Assche #define ATTR_SET_NOR 0 /* NORMAL */ 1095*dd11376bSBart Van Assche #define ATTR_SET_ST 1 /* STATIC */ 1096*dd11376bSBart Van Assche 1097*dd11376bSBart Van Assche static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 1098*dd11376bSBart Van Assche u32 mib_val) 1099*dd11376bSBart Van Assche { 1100*dd11376bSBart Van Assche return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1101*dd11376bSBart Van Assche mib_val, DME_LOCAL); 1102*dd11376bSBart Van Assche } 1103*dd11376bSBart Van Assche 1104*dd11376bSBart Van Assche static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, 1105*dd11376bSBart Van Assche u32 mib_val) 1106*dd11376bSBart Van Assche { 1107*dd11376bSBart Van Assche return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1108*dd11376bSBart Van Assche mib_val, DME_LOCAL); 1109*dd11376bSBart Van Assche } 1110*dd11376bSBart Van Assche 1111*dd11376bSBart Van Assche static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 1112*dd11376bSBart Van Assche u32 mib_val) 1113*dd11376bSBart Van Assche { 1114*dd11376bSBart Van Assche return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1115*dd11376bSBart Van Assche mib_val, DME_PEER); 1116*dd11376bSBart Van Assche } 1117*dd11376bSBart Van Assche 1118*dd11376bSBart Van Assche static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, 1119*dd11376bSBart Van Assche u32 mib_val) 1120*dd11376bSBart Van Assche { 1121*dd11376bSBart Van Assche return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1122*dd11376bSBart Van Assche mib_val, DME_PEER); 1123*dd11376bSBart Van Assche } 1124*dd11376bSBart Van Assche 1125*dd11376bSBart Van Assche static inline int ufshcd_dme_get(struct ufs_hba *hba, 1126*dd11376bSBart Van Assche u32 attr_sel, u32 *mib_val) 1127*dd11376bSBart Van Assche { 1128*dd11376bSBart Van Assche return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 1129*dd11376bSBart Van Assche } 1130*dd11376bSBart Van Assche 1131*dd11376bSBart Van Assche static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 1132*dd11376bSBart Van Assche u32 attr_sel, u32 *mib_val) 1133*dd11376bSBart Van Assche { 1134*dd11376bSBart Van Assche return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 1135*dd11376bSBart Van Assche } 1136*dd11376bSBart Van Assche 1137*dd11376bSBart Van Assche static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) 1138*dd11376bSBart Van Assche { 1139*dd11376bSBart Van Assche return (pwr_info->pwr_rx == FAST_MODE || 1140*dd11376bSBart Van Assche pwr_info->pwr_rx == FASTAUTO_MODE) && 1141*dd11376bSBart Van Assche (pwr_info->pwr_tx == FAST_MODE || 1142*dd11376bSBart Van Assche pwr_info->pwr_tx == FASTAUTO_MODE); 1143*dd11376bSBart Van Assche } 1144*dd11376bSBart Van Assche 1145*dd11376bSBart Van Assche static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) 1146*dd11376bSBart Van Assche { 1147*dd11376bSBart Van Assche return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); 1148*dd11376bSBart Van Assche } 1149*dd11376bSBart Van Assche 1150*dd11376bSBart Van Assche /* Expose Query-Request API */ 1151*dd11376bSBart Van Assche int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 1152*dd11376bSBart Van Assche enum query_opcode opcode, 1153*dd11376bSBart Van Assche enum desc_idn idn, u8 index, 1154*dd11376bSBart Van Assche u8 selector, 1155*dd11376bSBart Van Assche u8 *desc_buf, int *buf_len); 1156*dd11376bSBart Van Assche int ufshcd_read_desc_param(struct ufs_hba *hba, 1157*dd11376bSBart Van Assche enum desc_idn desc_id, 1158*dd11376bSBart Van Assche int desc_index, 1159*dd11376bSBart Van Assche u8 param_offset, 1160*dd11376bSBart Van Assche u8 *param_read_buf, 1161*dd11376bSBart Van Assche u8 param_size); 1162*dd11376bSBart Van Assche int ufshcd_query_attr_retry(struct ufs_hba *hba, enum query_opcode opcode, 1163*dd11376bSBart Van Assche enum attr_idn idn, u8 index, u8 selector, 1164*dd11376bSBart Van Assche u32 *attr_val); 1165*dd11376bSBart Van Assche int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 1166*dd11376bSBart Van Assche enum attr_idn idn, u8 index, u8 selector, u32 *attr_val); 1167*dd11376bSBart Van Assche int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 1168*dd11376bSBart Van Assche enum flag_idn idn, u8 index, bool *flag_res); 1169*dd11376bSBart Van Assche 1170*dd11376bSBart Van Assche void ufshcd_auto_hibern8_enable(struct ufs_hba *hba); 1171*dd11376bSBart Van Assche void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); 1172*dd11376bSBart Van Assche void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 1173*dd11376bSBart Van Assche const struct ufs_dev_quirk *fixups); 1174*dd11376bSBart Van Assche #define SD_ASCII_STD true 1175*dd11376bSBart Van Assche #define SD_RAW false 1176*dd11376bSBart Van Assche int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 1177*dd11376bSBart Van Assche u8 **buf, bool ascii); 1178*dd11376bSBart Van Assche 1179*dd11376bSBart Van Assche int ufshcd_hold(struct ufs_hba *hba, bool async); 1180*dd11376bSBart Van Assche void ufshcd_release(struct ufs_hba *hba); 1181*dd11376bSBart Van Assche 1182*dd11376bSBart Van Assche void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); 1183*dd11376bSBart Van Assche 1184*dd11376bSBart Van Assche void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, 1185*dd11376bSBart Van Assche int *desc_length); 1186*dd11376bSBart Van Assche 1187*dd11376bSBart Van Assche u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); 1188*dd11376bSBart Van Assche 1189*dd11376bSBart Van Assche int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); 1190*dd11376bSBart Van Assche 1191*dd11376bSBart Van Assche int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 1192*dd11376bSBart Van Assche struct utp_upiu_req *req_upiu, 1193*dd11376bSBart Van Assche struct utp_upiu_req *rsp_upiu, 1194*dd11376bSBart Van Assche int msgcode, 1195*dd11376bSBart Van Assche u8 *desc_buff, int *buff_len, 1196*dd11376bSBart Van Assche enum query_opcode desc_op); 1197*dd11376bSBart Van Assche 1198*dd11376bSBart Van Assche int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); 1199*dd11376bSBart Van Assche int ufshcd_suspend_prepare(struct device *dev); 1200*dd11376bSBart Van Assche int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); 1201*dd11376bSBart Van Assche void ufshcd_resume_complete(struct device *dev); 1202*dd11376bSBart Van Assche 1203*dd11376bSBart Van Assche /* Wrapper functions for safely calling variant operations */ 1204*dd11376bSBart Van Assche static inline int ufshcd_vops_init(struct ufs_hba *hba) 1205*dd11376bSBart Van Assche { 1206*dd11376bSBart Van Assche if (hba->vops && hba->vops->init) 1207*dd11376bSBart Van Assche return hba->vops->init(hba); 1208*dd11376bSBart Van Assche 1209*dd11376bSBart Van Assche return 0; 1210*dd11376bSBart Van Assche } 1211*dd11376bSBart Van Assche 1212*dd11376bSBart Van Assche static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) 1213*dd11376bSBart Van Assche { 1214*dd11376bSBart Van Assche if (hba->vops && hba->vops->phy_initialization) 1215*dd11376bSBart Van Assche return hba->vops->phy_initialization(hba); 1216*dd11376bSBart Van Assche 1217*dd11376bSBart Van Assche return 0; 1218*dd11376bSBart Van Assche } 1219*dd11376bSBart Van Assche 1220*dd11376bSBart Van Assche extern struct ufs_pm_lvl_states ufs_pm_lvl_states[]; 1221*dd11376bSBart Van Assche 1222*dd11376bSBart Van Assche int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1223*dd11376bSBart Van Assche const char *prefix); 1224*dd11376bSBart Van Assche 1225*dd11376bSBart Van Assche int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); 1226*dd11376bSBart Van Assche int ufshcd_write_ee_control(struct ufs_hba *hba); 1227*dd11376bSBart Van Assche int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, u16 *other_mask, 1228*dd11376bSBart Van Assche u16 set, u16 clr); 1229*dd11376bSBart Van Assche 1230*dd11376bSBart Van Assche #endif /* End of Header */ 1231