1dd11376bSBart Van Assche /* SPDX-License-Identifier: GPL-2.0-or-later */ 2dd11376bSBart Van Assche /* 3dd11376bSBart Van Assche * Universal Flash Storage Host controller driver 4dd11376bSBart Van Assche * Copyright (C) 2011-2013 Samsung India Software Operations 5dd11376bSBart Van Assche * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6dd11376bSBart Van Assche * 7dd11376bSBart Van Assche * Authors: 8dd11376bSBart Van Assche * Santosh Yaraganavi <santosh.sy@samsung.com> 9dd11376bSBart Van Assche * Vinayak Holikatti <h.vinayak@samsung.com> 10dd11376bSBart Van Assche */ 11dd11376bSBart Van Assche 12dd11376bSBart Van Assche #ifndef _UFSHCD_H 13dd11376bSBart Van Assche #define _UFSHCD_H 14dd11376bSBart Van Assche 15dd11376bSBart Van Assche #include <linux/bitfield.h> 16dd11376bSBart Van Assche #include <linux/blk-crypto-profile.h> 17dd11376bSBart Van Assche #include <linux/blk-mq.h> 18dd11376bSBart Van Assche #include <linux/devfreq.h> 19dd11376bSBart Van Assche #include <linux/pm_runtime.h> 20f3e57da5SBean Huo #include <linux/dma-direction.h> 21dd11376bSBart Van Assche #include <scsi/scsi_device.h> 22dd11376bSBart Van Assche #include <ufs/unipro.h> 23dd11376bSBart Van Assche #include <ufs/ufs.h> 24dd11376bSBart Van Assche #include <ufs/ufs_quirks.h> 25dd11376bSBart Van Assche #include <ufs/ufshci.h> 26dd11376bSBart Van Assche 27dd11376bSBart Van Assche #define UFSHCD "ufshcd" 28dd11376bSBart Van Assche 29dd11376bSBart Van Assche struct ufs_hba; 30dd11376bSBart Van Assche 31dd11376bSBart Van Assche enum dev_cmd_type { 32dd11376bSBart Van Assche DEV_CMD_TYPE_NOP = 0x0, 33dd11376bSBart Van Assche DEV_CMD_TYPE_QUERY = 0x1, 346ff265fcSBean Huo DEV_CMD_TYPE_RPMB = 0x2, 35dd11376bSBart Van Assche }; 36dd11376bSBart Van Assche 37dd11376bSBart Van Assche enum ufs_event_type { 38dd11376bSBart Van Assche /* uic specific errors */ 39dd11376bSBart Van Assche UFS_EVT_PA_ERR = 0, 40dd11376bSBart Van Assche UFS_EVT_DL_ERR, 41dd11376bSBart Van Assche UFS_EVT_NL_ERR, 42dd11376bSBart Van Assche UFS_EVT_TL_ERR, 43dd11376bSBart Van Assche UFS_EVT_DME_ERR, 44dd11376bSBart Van Assche 45dd11376bSBart Van Assche /* fatal errors */ 46dd11376bSBart Van Assche UFS_EVT_AUTO_HIBERN8_ERR, 47dd11376bSBart Van Assche UFS_EVT_FATAL_ERR, 48dd11376bSBart Van Assche UFS_EVT_LINK_STARTUP_FAIL, 49dd11376bSBart Van Assche UFS_EVT_RESUME_ERR, 50dd11376bSBart Van Assche UFS_EVT_SUSPEND_ERR, 51dd11376bSBart Van Assche UFS_EVT_WL_SUSP_ERR, 52dd11376bSBart Van Assche UFS_EVT_WL_RES_ERR, 53dd11376bSBart Van Assche 54dd11376bSBart Van Assche /* abnormal events */ 55dd11376bSBart Van Assche UFS_EVT_DEV_RESET, 56dd11376bSBart Van Assche UFS_EVT_HOST_RESET, 57dd11376bSBart Van Assche UFS_EVT_ABORT, 58dd11376bSBart Van Assche 59dd11376bSBart Van Assche UFS_EVT_CNT, 60dd11376bSBart Van Assche }; 61dd11376bSBart Van Assche 62dd11376bSBart Van Assche /** 63dd11376bSBart Van Assche * struct uic_command - UIC command structure 64dd11376bSBart Van Assche * @command: UIC command 65dd11376bSBart Van Assche * @argument1: UIC command argument 1 66dd11376bSBart Van Assche * @argument2: UIC command argument 2 67dd11376bSBart Van Assche * @argument3: UIC command argument 3 68dd11376bSBart Van Assche * @cmd_active: Indicate if UIC command is outstanding 69dd11376bSBart Van Assche * @done: UIC command completion 70dd11376bSBart Van Assche */ 71dd11376bSBart Van Assche struct uic_command { 72dd11376bSBart Van Assche u32 command; 73dd11376bSBart Van Assche u32 argument1; 74dd11376bSBart Van Assche u32 argument2; 75dd11376bSBart Van Assche u32 argument3; 76dd11376bSBart Van Assche int cmd_active; 77dd11376bSBart Van Assche struct completion done; 78dd11376bSBart Van Assche }; 79dd11376bSBart Van Assche 80dd11376bSBart Van Assche /* Used to differentiate the power management options */ 81dd11376bSBart Van Assche enum ufs_pm_op { 82dd11376bSBart Van Assche UFS_RUNTIME_PM, 83dd11376bSBart Van Assche UFS_SYSTEM_PM, 84dd11376bSBart Van Assche UFS_SHUTDOWN_PM, 85dd11376bSBart Van Assche }; 86dd11376bSBart Van Assche 87dd11376bSBart Van Assche /* Host <-> Device UniPro Link state */ 88dd11376bSBart Van Assche enum uic_link_state { 89dd11376bSBart Van Assche UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 90dd11376bSBart Van Assche UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 91dd11376bSBart Van Assche UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 92dd11376bSBart Van Assche UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ 93dd11376bSBart Van Assche }; 94dd11376bSBart Van Assche 95dd11376bSBart Van Assche #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) 96dd11376bSBart Van Assche #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ 97dd11376bSBart Van Assche UIC_LINK_ACTIVE_STATE) 98dd11376bSBart Van Assche #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ 99dd11376bSBart Van Assche UIC_LINK_HIBERN8_STATE) 100dd11376bSBart Van Assche #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ 101dd11376bSBart Van Assche UIC_LINK_BROKEN_STATE) 102dd11376bSBart Van Assche #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) 103dd11376bSBart Van Assche #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ 104dd11376bSBart Van Assche UIC_LINK_ACTIVE_STATE) 105dd11376bSBart Van Assche #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ 106dd11376bSBart Van Assche UIC_LINK_HIBERN8_STATE) 107dd11376bSBart Van Assche #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ 108dd11376bSBart Van Assche UIC_LINK_BROKEN_STATE) 109dd11376bSBart Van Assche 110dd11376bSBart Van Assche #define ufshcd_set_ufs_dev_active(h) \ 111dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) 112dd11376bSBart Van Assche #define ufshcd_set_ufs_dev_sleep(h) \ 113dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) 114dd11376bSBart Van Assche #define ufshcd_set_ufs_dev_poweroff(h) \ 115dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) 116dd11376bSBart Van Assche #define ufshcd_set_ufs_dev_deepsleep(h) \ 117dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) 118dd11376bSBart Van Assche #define ufshcd_is_ufs_dev_active(h) \ 119dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) 120dd11376bSBart Van Assche #define ufshcd_is_ufs_dev_sleep(h) \ 121dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) 122dd11376bSBart Van Assche #define ufshcd_is_ufs_dev_poweroff(h) \ 123dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) 124dd11376bSBart Van Assche #define ufshcd_is_ufs_dev_deepsleep(h) \ 125dd11376bSBart Van Assche ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) 126dd11376bSBart Van Assche 127dd11376bSBart Van Assche /* 128dd11376bSBart Van Assche * UFS Power management levels. 129dd11376bSBart Van Assche * Each level is in increasing order of power savings, except DeepSleep 130dd11376bSBart Van Assche * which is lower than PowerDown with power on but not PowerDown with 131dd11376bSBart Van Assche * power off. 132dd11376bSBart Van Assche */ 133dd11376bSBart Van Assche enum ufs_pm_level { 134dd11376bSBart Van Assche UFS_PM_LVL_0, 135dd11376bSBart Van Assche UFS_PM_LVL_1, 136dd11376bSBart Van Assche UFS_PM_LVL_2, 137dd11376bSBart Van Assche UFS_PM_LVL_3, 138dd11376bSBart Van Assche UFS_PM_LVL_4, 139dd11376bSBart Van Assche UFS_PM_LVL_5, 140dd11376bSBart Van Assche UFS_PM_LVL_6, 141dd11376bSBart Van Assche UFS_PM_LVL_MAX 142dd11376bSBart Van Assche }; 143dd11376bSBart Van Assche 144dd11376bSBart Van Assche struct ufs_pm_lvl_states { 145dd11376bSBart Van Assche enum ufs_dev_pwr_mode dev_state; 146dd11376bSBart Van Assche enum uic_link_state link_state; 147dd11376bSBart Van Assche }; 148dd11376bSBart Van Assche 149dd11376bSBart Van Assche /** 150dd11376bSBart Van Assche * struct ufshcd_lrb - local reference block 151dd11376bSBart Van Assche * @utr_descriptor_ptr: UTRD address of the command 152dd11376bSBart Van Assche * @ucd_req_ptr: UCD address of the command 153dd11376bSBart Van Assche * @ucd_rsp_ptr: Response UPIU address for this command 154dd11376bSBart Van Assche * @ucd_prdt_ptr: PRDT address of the command 155dd11376bSBart Van Assche * @utrd_dma_addr: UTRD dma address for debug 156dd11376bSBart Van Assche * @ucd_prdt_dma_addr: PRDT dma address for debug 157dd11376bSBart Van Assche * @ucd_rsp_dma_addr: UPIU response dma address for debug 158dd11376bSBart Van Assche * @ucd_req_dma_addr: UPIU request dma address for debug 159dd11376bSBart Van Assche * @cmd: pointer to SCSI command 160dd11376bSBart Van Assche * @scsi_status: SCSI status of the command 161dd11376bSBart Van Assche * @command_type: SCSI, UFS, Query. 162dd11376bSBart Van Assche * @task_tag: Task tag of the command 163dd11376bSBart Van Assche * @lun: LUN of the command 164dd11376bSBart Van Assche * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) 1650f85e747SDaniil Lunev * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) 1660f85e747SDaniil Lunev * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) 1670f85e747SDaniil Lunev * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) 1680f85e747SDaniil Lunev * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) 169dd11376bSBart Van Assche * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) 170dd11376bSBart Van Assche * @data_unit_num: the data unit number for the first block for inline crypto 171dd11376bSBart Van Assche * @req_abort_skip: skip request abort task flag 172dd11376bSBart Van Assche */ 173dd11376bSBart Van Assche struct ufshcd_lrb { 174dd11376bSBart Van Assche struct utp_transfer_req_desc *utr_descriptor_ptr; 175dd11376bSBart Van Assche struct utp_upiu_req *ucd_req_ptr; 176dd11376bSBart Van Assche struct utp_upiu_rsp *ucd_rsp_ptr; 177dd11376bSBart Van Assche struct ufshcd_sg_entry *ucd_prdt_ptr; 178dd11376bSBart Van Assche 179dd11376bSBart Van Assche dma_addr_t utrd_dma_addr; 180dd11376bSBart Van Assche dma_addr_t ucd_req_dma_addr; 181dd11376bSBart Van Assche dma_addr_t ucd_rsp_dma_addr; 182dd11376bSBart Van Assche dma_addr_t ucd_prdt_dma_addr; 183dd11376bSBart Van Assche 184dd11376bSBart Van Assche struct scsi_cmnd *cmd; 185dd11376bSBart Van Assche int scsi_status; 186dd11376bSBart Van Assche 187dd11376bSBart Van Assche int command_type; 188dd11376bSBart Van Assche int task_tag; 189dd11376bSBart Van Assche u8 lun; /* UPIU LUN id field is only 8-bit wide */ 190dd11376bSBart Van Assche bool intr_cmd; 191dd11376bSBart Van Assche ktime_t issue_time_stamp; 1920f85e747SDaniil Lunev u64 issue_time_stamp_local_clock; 193dd11376bSBart Van Assche ktime_t compl_time_stamp; 1940f85e747SDaniil Lunev u64 compl_time_stamp_local_clock; 195dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_CRYPTO 196dd11376bSBart Van Assche int crypto_key_slot; 197dd11376bSBart Van Assche u64 data_unit_num; 198dd11376bSBart Van Assche #endif 199dd11376bSBart Van Assche 200dd11376bSBart Van Assche bool req_abort_skip; 201dd11376bSBart Van Assche }; 202dd11376bSBart Van Assche 203dd11376bSBart Van Assche /** 204dd11376bSBart Van Assche * struct ufs_query - holds relevant data structures for query request 205dd11376bSBart Van Assche * @request: request upiu and function 206dd11376bSBart Van Assche * @descriptor: buffer for sending/receiving descriptor 207dd11376bSBart Van Assche * @response: response upiu and response 208dd11376bSBart Van Assche */ 209dd11376bSBart Van Assche struct ufs_query { 210dd11376bSBart Van Assche struct ufs_query_req request; 211dd11376bSBart Van Assche u8 *descriptor; 212dd11376bSBart Van Assche struct ufs_query_res response; 213dd11376bSBart Van Assche }; 214dd11376bSBart Van Assche 215dd11376bSBart Van Assche /** 216dd11376bSBart Van Assche * struct ufs_dev_cmd - all assosiated fields with device management commands 217dd11376bSBart Van Assche * @type: device management command type - Query, NOP OUT 218dd11376bSBart Van Assche * @lock: lock to allow one command at a time 219dd11376bSBart Van Assche * @complete: internal commands completion 220dd11376bSBart Van Assche * @query: Device management query information 221dd11376bSBart Van Assche */ 222dd11376bSBart Van Assche struct ufs_dev_cmd { 223dd11376bSBart Van Assche enum dev_cmd_type type; 224dd11376bSBart Van Assche struct mutex lock; 225dd11376bSBart Van Assche struct completion *complete; 226dd11376bSBart Van Assche struct ufs_query query; 227dd11376bSBart Van Assche }; 228dd11376bSBart Van Assche 229dd11376bSBart Van Assche /** 230dd11376bSBart Van Assche * struct ufs_clk_info - UFS clock related info 231dd11376bSBart Van Assche * @list: list headed by hba->clk_list_head 232dd11376bSBart Van Assche * @clk: clock node 233dd11376bSBart Van Assche * @name: clock name 234dd11376bSBart Van Assche * @max_freq: maximum frequency supported by the clock 235dd11376bSBart Van Assche * @min_freq: min frequency that can be used for clock scaling 236dd11376bSBart Van Assche * @curr_freq: indicates the current frequency that it is set to 237dd11376bSBart Van Assche * @keep_link_active: indicates that the clk should not be disabled if 238dd11376bSBart Van Assche * link is active 239dd11376bSBart Van Assche * @enabled: variable to check against multiple enable/disable 240dd11376bSBart Van Assche */ 241dd11376bSBart Van Assche struct ufs_clk_info { 242dd11376bSBart Van Assche struct list_head list; 243dd11376bSBart Van Assche struct clk *clk; 244dd11376bSBart Van Assche const char *name; 245dd11376bSBart Van Assche u32 max_freq; 246dd11376bSBart Van Assche u32 min_freq; 247dd11376bSBart Van Assche u32 curr_freq; 248dd11376bSBart Van Assche bool keep_link_active; 249dd11376bSBart Van Assche bool enabled; 250dd11376bSBart Van Assche }; 251dd11376bSBart Van Assche 252dd11376bSBart Van Assche enum ufs_notify_change_status { 253dd11376bSBart Van Assche PRE_CHANGE, 254dd11376bSBart Van Assche POST_CHANGE, 255dd11376bSBart Van Assche }; 256dd11376bSBart Van Assche 257dd11376bSBart Van Assche struct ufs_pa_layer_attr { 258dd11376bSBart Van Assche u32 gear_rx; 259dd11376bSBart Van Assche u32 gear_tx; 260dd11376bSBart Van Assche u32 lane_rx; 261dd11376bSBart Van Assche u32 lane_tx; 262dd11376bSBart Van Assche u32 pwr_rx; 263dd11376bSBart Van Assche u32 pwr_tx; 264dd11376bSBart Van Assche u32 hs_rate; 265dd11376bSBart Van Assche }; 266dd11376bSBart Van Assche 267dd11376bSBart Van Assche struct ufs_pwr_mode_info { 268dd11376bSBart Van Assche bool is_valid; 269dd11376bSBart Van Assche struct ufs_pa_layer_attr info; 270dd11376bSBart Van Assche }; 271dd11376bSBart Van Assche 272dd11376bSBart Van Assche /** 273dd11376bSBart Van Assche * struct ufs_hba_variant_ops - variant specific callbacks 274dd11376bSBart Van Assche * @name: variant name 275dd11376bSBart Van Assche * @init: called when the driver is initialized 276dd11376bSBart Van Assche * @exit: called to cleanup everything done in init 277dd11376bSBart Van Assche * @get_ufs_hci_version: called to get UFS HCI version 278dd11376bSBart Van Assche * @clk_scale_notify: notifies that clks are scaled up/down 279dd11376bSBart Van Assche * @setup_clocks: called before touching any of the controller registers 280dd11376bSBart Van Assche * @hce_enable_notify: called before and after HCE enable bit is set to allow 281dd11376bSBart Van Assche * variant specific Uni-Pro initialization. 282dd11376bSBart Van Assche * @link_startup_notify: called before and after Link startup is carried out 283dd11376bSBart Van Assche * to allow variant specific Uni-Pro initialization. 284dd11376bSBart Van Assche * @pwr_change_notify: called before and after a power mode change 285dd11376bSBart Van Assche * is carried out to allow vendor spesific capabilities 286dd11376bSBart Van Assche * to be set. 287dd11376bSBart Van Assche * @setup_xfer_req: called before any transfer request is issued 288dd11376bSBart Van Assche * to set some things 289dd11376bSBart Van Assche * @setup_task_mgmt: called before any task management request is issued 290dd11376bSBart Van Assche * to set some things 291dd11376bSBart Van Assche * @hibern8_notify: called around hibern8 enter/exit 292dd11376bSBart Van Assche * @apply_dev_quirks: called to apply device specific quirks 293dd11376bSBart Van Assche * @fixup_dev_quirks: called to modify device specific quirks 294dd11376bSBart Van Assche * @suspend: called during host controller PM callback 295dd11376bSBart Van Assche * @resume: called during host controller PM callback 296dd11376bSBart Van Assche * @dbg_register_dump: used to dump controller debug information 297dd11376bSBart Van Assche * @phy_initialization: used to initialize phys 298dd11376bSBart Van Assche * @device_reset: called to issue a reset pulse on the UFS device 299dd11376bSBart Van Assche * @config_scaling_param: called to configure clock scaling parameters 300dd11376bSBart Van Assche * @program_key: program or evict an inline encryption key 301dd11376bSBart Van Assche * @event_notify: called to notify important events 302c2c38c57SManivannan Sadhasivam * @reinit_notify: called to notify reinit of UFSHCD during max gear switch 303*c263b4efSAsutosh Das * @mcq_config_resource: called to configure MCQ platform resources 304dd11376bSBart Van Assche */ 305dd11376bSBart Van Assche struct ufs_hba_variant_ops { 306dd11376bSBart Van Assche const char *name; 307dd11376bSBart Van Assche int (*init)(struct ufs_hba *); 308dd11376bSBart Van Assche void (*exit)(struct ufs_hba *); 309dd11376bSBart Van Assche u32 (*get_ufs_hci_version)(struct ufs_hba *); 310dd11376bSBart Van Assche int (*clk_scale_notify)(struct ufs_hba *, bool, 311dd11376bSBart Van Assche enum ufs_notify_change_status); 312dd11376bSBart Van Assche int (*setup_clocks)(struct ufs_hba *, bool, 313dd11376bSBart Van Assche enum ufs_notify_change_status); 314dd11376bSBart Van Assche int (*hce_enable_notify)(struct ufs_hba *, 315dd11376bSBart Van Assche enum ufs_notify_change_status); 316dd11376bSBart Van Assche int (*link_startup_notify)(struct ufs_hba *, 317dd11376bSBart Van Assche enum ufs_notify_change_status); 318dd11376bSBart Van Assche int (*pwr_change_notify)(struct ufs_hba *, 319dd11376bSBart Van Assche enum ufs_notify_change_status status, 320dd11376bSBart Van Assche struct ufs_pa_layer_attr *, 321dd11376bSBart Van Assche struct ufs_pa_layer_attr *); 322dd11376bSBart Van Assche void (*setup_xfer_req)(struct ufs_hba *hba, int tag, 323dd11376bSBart Van Assche bool is_scsi_cmd); 324dd11376bSBart Van Assche void (*setup_task_mgmt)(struct ufs_hba *, int, u8); 325dd11376bSBart Van Assche void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, 326dd11376bSBart Van Assche enum ufs_notify_change_status); 327dd11376bSBart Van Assche int (*apply_dev_quirks)(struct ufs_hba *hba); 328dd11376bSBart Van Assche void (*fixup_dev_quirks)(struct ufs_hba *hba); 329dd11376bSBart Van Assche int (*suspend)(struct ufs_hba *, enum ufs_pm_op, 330dd11376bSBart Van Assche enum ufs_notify_change_status); 331dd11376bSBart Van Assche int (*resume)(struct ufs_hba *, enum ufs_pm_op); 332dd11376bSBart Van Assche void (*dbg_register_dump)(struct ufs_hba *hba); 333dd11376bSBart Van Assche int (*phy_initialization)(struct ufs_hba *); 334dd11376bSBart Van Assche int (*device_reset)(struct ufs_hba *hba); 335dd11376bSBart Van Assche void (*config_scaling_param)(struct ufs_hba *hba, 336dd11376bSBart Van Assche struct devfreq_dev_profile *profile, 337dd11376bSBart Van Assche struct devfreq_simple_ondemand_data *data); 338dd11376bSBart Van Assche int (*program_key)(struct ufs_hba *hba, 339dd11376bSBart Van Assche const union ufs_crypto_cfg_entry *cfg, int slot); 340dd11376bSBart Van Assche void (*event_notify)(struct ufs_hba *hba, 341dd11376bSBart Van Assche enum ufs_event_type evt, void *data); 342c2c38c57SManivannan Sadhasivam void (*reinit_notify)(struct ufs_hba *); 343*c263b4efSAsutosh Das int (*mcq_config_resource)(struct ufs_hba *hba); 344dd11376bSBart Van Assche }; 345dd11376bSBart Van Assche 346dd11376bSBart Van Assche /* clock gating state */ 347dd11376bSBart Van Assche enum clk_gating_state { 348dd11376bSBart Van Assche CLKS_OFF, 349dd11376bSBart Van Assche CLKS_ON, 350dd11376bSBart Van Assche REQ_CLKS_OFF, 351dd11376bSBart Van Assche REQ_CLKS_ON, 352dd11376bSBart Van Assche }; 353dd11376bSBart Van Assche 354dd11376bSBart Van Assche /** 355dd11376bSBart Van Assche * struct ufs_clk_gating - UFS clock gating related info 356dd11376bSBart Van Assche * @gate_work: worker to turn off clocks after some delay as specified in 357dd11376bSBart Van Assche * delay_ms 358dd11376bSBart Van Assche * @ungate_work: worker to turn on clocks that will be used in case of 359dd11376bSBart Van Assche * interrupt context 360dd11376bSBart Van Assche * @state: the current clocks state 361dd11376bSBart Van Assche * @delay_ms: gating delay in ms 362dd11376bSBart Van Assche * @is_suspended: clk gating is suspended when set to 1 which can be used 363dd11376bSBart Van Assche * during suspend/resume 364dd11376bSBart Van Assche * @delay_attr: sysfs attribute to control delay_attr 365dd11376bSBart Van Assche * @enable_attr: sysfs attribute to enable/disable clock gating 366dd11376bSBart Van Assche * @is_enabled: Indicates the current status of clock gating 367dd11376bSBart Van Assche * @is_initialized: Indicates whether clock gating is initialized or not 368dd11376bSBart Van Assche * @active_reqs: number of requests that are pending and should be waited for 369dd11376bSBart Van Assche * completion before gating clocks. 370dd11376bSBart Van Assche * @clk_gating_workq: workqueue for clock gating work. 371dd11376bSBart Van Assche */ 372dd11376bSBart Van Assche struct ufs_clk_gating { 373dd11376bSBart Van Assche struct delayed_work gate_work; 374dd11376bSBart Van Assche struct work_struct ungate_work; 375dd11376bSBart Van Assche enum clk_gating_state state; 376dd11376bSBart Van Assche unsigned long delay_ms; 377dd11376bSBart Van Assche bool is_suspended; 378dd11376bSBart Van Assche struct device_attribute delay_attr; 379dd11376bSBart Van Assche struct device_attribute enable_attr; 380dd11376bSBart Van Assche bool is_enabled; 381dd11376bSBart Van Assche bool is_initialized; 382dd11376bSBart Van Assche int active_reqs; 383dd11376bSBart Van Assche struct workqueue_struct *clk_gating_workq; 384dd11376bSBart Van Assche }; 385dd11376bSBart Van Assche 386dd11376bSBart Van Assche struct ufs_saved_pwr_info { 387dd11376bSBart Van Assche struct ufs_pa_layer_attr info; 388dd11376bSBart Van Assche bool is_valid; 389dd11376bSBart Van Assche }; 390dd11376bSBart Van Assche 391dd11376bSBart Van Assche /** 392dd11376bSBart Van Assche * struct ufs_clk_scaling - UFS clock scaling related data 393dd11376bSBart Van Assche * @active_reqs: number of requests that are pending. If this is zero when 394dd11376bSBart Van Assche * devfreq ->target() function is called then schedule "suspend_work" to 395dd11376bSBart Van Assche * suspend devfreq. 396dd11376bSBart Van Assche * @tot_busy_t: Total busy time in current polling window 397dd11376bSBart Van Assche * @window_start_t: Start time (in jiffies) of the current polling window 398dd11376bSBart Van Assche * @busy_start_t: Start time of current busy period 399dd11376bSBart Van Assche * @enable_attr: sysfs attribute to enable/disable clock scaling 400dd11376bSBart Van Assche * @saved_pwr_info: UFS power mode may also be changed during scaling and this 401dd11376bSBart Van Assche * one keeps track of previous power mode. 402dd11376bSBart Van Assche * @workq: workqueue to schedule devfreq suspend/resume work 403dd11376bSBart Van Assche * @suspend_work: worker to suspend devfreq 404dd11376bSBart Van Assche * @resume_work: worker to resume devfreq 405dd11376bSBart Van Assche * @min_gear: lowest HS gear to scale down to 406dd11376bSBart Van Assche * @is_enabled: tracks if scaling is currently enabled or not, controlled by 407dd11376bSBart Van Assche * clkscale_enable sysfs node 408dd11376bSBart Van Assche * @is_allowed: tracks if scaling is currently allowed or not, used to block 409dd11376bSBart Van Assche * clock scaling which is not invoked from devfreq governor 410dd11376bSBart Van Assche * @is_initialized: Indicates whether clock scaling is initialized or not 411dd11376bSBart Van Assche * @is_busy_started: tracks if busy period has started or not 412dd11376bSBart Van Assche * @is_suspended: tracks if devfreq is suspended or not 413dd11376bSBart Van Assche */ 414dd11376bSBart Van Assche struct ufs_clk_scaling { 415dd11376bSBart Van Assche int active_reqs; 416dd11376bSBart Van Assche unsigned long tot_busy_t; 417dd11376bSBart Van Assche ktime_t window_start_t; 418dd11376bSBart Van Assche ktime_t busy_start_t; 419dd11376bSBart Van Assche struct device_attribute enable_attr; 420dd11376bSBart Van Assche struct ufs_saved_pwr_info saved_pwr_info; 421dd11376bSBart Van Assche struct workqueue_struct *workq; 422dd11376bSBart Van Assche struct work_struct suspend_work; 423dd11376bSBart Van Assche struct work_struct resume_work; 424dd11376bSBart Van Assche u32 min_gear; 425dd11376bSBart Van Assche bool is_enabled; 426dd11376bSBart Van Assche bool is_allowed; 427dd11376bSBart Van Assche bool is_initialized; 428dd11376bSBart Van Assche bool is_busy_started; 429dd11376bSBart Van Assche bool is_suspended; 430dd11376bSBart Van Assche }; 431dd11376bSBart Van Assche 432dd11376bSBart Van Assche #define UFS_EVENT_HIST_LENGTH 8 433dd11376bSBart Van Assche /** 434dd11376bSBart Van Assche * struct ufs_event_hist - keeps history of errors 435dd11376bSBart Van Assche * @pos: index to indicate cyclic buffer position 436dd11376bSBart Van Assche * @val: cyclic buffer for registers value 437dd11376bSBart Van Assche * @tstamp: cyclic buffer for time stamp 438dd11376bSBart Van Assche * @cnt: error counter 439dd11376bSBart Van Assche */ 440dd11376bSBart Van Assche struct ufs_event_hist { 441dd11376bSBart Van Assche int pos; 442dd11376bSBart Van Assche u32 val[UFS_EVENT_HIST_LENGTH]; 4430f85e747SDaniil Lunev u64 tstamp[UFS_EVENT_HIST_LENGTH]; 444dd11376bSBart Van Assche unsigned long long cnt; 445dd11376bSBart Van Assche }; 446dd11376bSBart Van Assche 447dd11376bSBart Van Assche /** 448dd11376bSBart Van Assche * struct ufs_stats - keeps usage/err statistics 449dd11376bSBart Van Assche * @last_intr_status: record the last interrupt status. 450dd11376bSBart Van Assche * @last_intr_ts: record the last interrupt timestamp. 451dd11376bSBart Van Assche * @hibern8_exit_cnt: Counter to keep track of number of exits, 452dd11376bSBart Van Assche * reset this after link-startup. 453dd11376bSBart Van Assche * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. 454dd11376bSBart Van Assche * Clear after the first successful command completion. 455dd11376bSBart Van Assche * @event: array with event history. 456dd11376bSBart Van Assche */ 457dd11376bSBart Van Assche struct ufs_stats { 458dd11376bSBart Van Assche u32 last_intr_status; 4590f85e747SDaniil Lunev u64 last_intr_ts; 460dd11376bSBart Van Assche 461dd11376bSBart Van Assche u32 hibern8_exit_cnt; 4620f85e747SDaniil Lunev u64 last_hibern8_exit_tstamp; 463dd11376bSBart Van Assche struct ufs_event_hist event[UFS_EVT_CNT]; 464dd11376bSBart Van Assche }; 465dd11376bSBart Van Assche 466dd11376bSBart Van Assche /** 467dd11376bSBart Van Assche * enum ufshcd_state - UFS host controller state 468dd11376bSBart Van Assche * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command 469dd11376bSBart Van Assche * processing. 470dd11376bSBart Van Assche * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process 471dd11376bSBart Van Assche * SCSI commands. 472dd11376bSBart Van Assche * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. 473dd11376bSBart Van Assche * SCSI commands may be submitted to the controller. 474dd11376bSBart Van Assche * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail 475dd11376bSBart Van Assche * newly submitted SCSI commands with error code DID_BAD_TARGET. 476dd11376bSBart Van Assche * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery 477dd11376bSBart Van Assche * failed. Fail all SCSI commands with error code DID_ERROR. 478dd11376bSBart Van Assche */ 479dd11376bSBart Van Assche enum ufshcd_state { 480dd11376bSBart Van Assche UFSHCD_STATE_RESET, 481dd11376bSBart Van Assche UFSHCD_STATE_OPERATIONAL, 482dd11376bSBart Van Assche UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, 483dd11376bSBart Van Assche UFSHCD_STATE_EH_SCHEDULED_FATAL, 484dd11376bSBart Van Assche UFSHCD_STATE_ERROR, 485dd11376bSBart Van Assche }; 486dd11376bSBart Van Assche 487dd11376bSBart Van Assche enum ufshcd_quirks { 488dd11376bSBart Van Assche /* Interrupt aggregation support is broken */ 489dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, 490dd11376bSBart Van Assche 491dd11376bSBart Van Assche /* 492dd11376bSBart Van Assche * delay before each dme command is required as the unipro 493dd11376bSBart Van Assche * layer has shown instabilities 494dd11376bSBart Van Assche */ 495dd11376bSBart Van Assche UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, 496dd11376bSBart Van Assche 497dd11376bSBart Van Assche /* 498dd11376bSBart Van Assche * If UFS host controller is having issue in processing LCC (Line 499dd11376bSBart Van Assche * Control Command) coming from device then enable this quirk. 500dd11376bSBart Van Assche * When this quirk is enabled, host controller driver should disable 501dd11376bSBart Van Assche * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 502dd11376bSBart Van Assche * attribute of device to 0). 503dd11376bSBart Van Assche */ 504dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, 505dd11376bSBart Van Assche 506dd11376bSBart Van Assche /* 507dd11376bSBart Van Assche * The attribute PA_RXHSUNTERMCAP specifies whether or not the 508dd11376bSBart Van Assche * inbound Link supports unterminated line in HS mode. Setting this 509dd11376bSBart Van Assche * attribute to 1 fixes moving to HS gear. 510dd11376bSBart Van Assche */ 511dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, 512dd11376bSBart Van Assche 513dd11376bSBart Van Assche /* 514dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller only allows 515dd11376bSBart Van Assche * accessing the peer dme attributes in AUTO mode (FAST AUTO or 516dd11376bSBart Van Assche * SLOW AUTO). 517dd11376bSBart Van Assche */ 518dd11376bSBart Van Assche UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, 519dd11376bSBart Van Assche 520dd11376bSBart Van Assche /* 521dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller doesn't 522dd11376bSBart Van Assche * advertise the correct version in UFS_VER register. If this quirk 523dd11376bSBart Van Assche * is enabled, standard UFS host driver will call the vendor specific 524dd11376bSBart Van Assche * ops (get_ufs_hci_version) to get the correct version. 525dd11376bSBart Van Assche */ 526dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, 527dd11376bSBart Van Assche 528dd11376bSBart Van Assche /* 529dd11376bSBart Van Assche * Clear handling for transfer/task request list is just opposite. 530dd11376bSBart Van Assche */ 531dd11376bSBart Van Assche UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, 532dd11376bSBart Van Assche 533dd11376bSBart Van Assche /* 534dd11376bSBart Van Assche * This quirk needs to be enabled if host controller doesn't allow 535dd11376bSBart Van Assche * that the interrupt aggregation timer and counter are reset by s/w. 536dd11376bSBart Van Assche */ 537dd11376bSBart Van Assche UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, 538dd11376bSBart Van Assche 539dd11376bSBart Van Assche /* 540dd11376bSBart Van Assche * This quirks needs to be enabled if host controller cannot be 541dd11376bSBart Van Assche * enabled via HCE register. 542dd11376bSBart Van Assche */ 543dd11376bSBart Van Assche UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, 544dd11376bSBart Van Assche 545dd11376bSBart Van Assche /* 546dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller regards 547dd11376bSBart Van Assche * resolution of the values of PRDTO and PRDTL in UTRD as byte. 548dd11376bSBart Van Assche */ 549dd11376bSBart Van Assche UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, 550dd11376bSBart Van Assche 551dd11376bSBart Van Assche /* 552dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller reports 553dd11376bSBart Van Assche * OCS FATAL ERROR with device error through sense data 554dd11376bSBart Van Assche */ 555dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, 556dd11376bSBart Van Assche 557dd11376bSBart Van Assche /* 558dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller has 559dd11376bSBart Van Assche * auto-hibernate capability but it doesn't work. 560dd11376bSBart Van Assche */ 561dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, 562dd11376bSBart Van Assche 563dd11376bSBart Van Assche /* 564dd11376bSBart Van Assche * This quirk needs to disable manual flush for write booster 565dd11376bSBart Van Assche */ 566dd11376bSBart Van Assche UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, 567dd11376bSBart Van Assche 568dd11376bSBart Van Assche /* 569dd11376bSBart Van Assche * This quirk needs to disable unipro timeout values 570dd11376bSBart Van Assche * before power mode change 571dd11376bSBart Van Assche */ 572dd11376bSBart Van Assche UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, 573dd11376bSBart Van Assche 574dd11376bSBart Van Assche /* 575dd11376bSBart Van Assche * This quirk allows only sg entries aligned with page size. 576dd11376bSBart Van Assche */ 577dd11376bSBart Van Assche UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE = 1 << 14, 578dd11376bSBart Van Assche 579dd11376bSBart Van Assche /* 580dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller does not 581dd11376bSBart Van Assche * support UIC command 582dd11376bSBart Van Assche */ 583dd11376bSBart Van Assche UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, 584dd11376bSBart Van Assche 585dd11376bSBart Van Assche /* 586dd11376bSBart Van Assche * This quirk needs to be enabled if the host controller cannot 587dd11376bSBart Van Assche * support physical host configuration. 588dd11376bSBart Van Assche */ 589dd11376bSBart Van Assche UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, 5906554400dSYoshihiro Shimoda 5916554400dSYoshihiro Shimoda /* 5926554400dSYoshihiro Shimoda * This quirk needs to be enabled if the host controller has 5936554400dSYoshihiro Shimoda * 64-bit addressing supported capability but it doesn't work. 5946554400dSYoshihiro Shimoda */ 5956554400dSYoshihiro Shimoda UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17, 5962f11bbc2SYoshihiro Shimoda 5972f11bbc2SYoshihiro Shimoda /* 5982f11bbc2SYoshihiro Shimoda * This quirk needs to be enabled if the host controller has 5992f11bbc2SYoshihiro Shimoda * auto-hibernate capability but it's FASTAUTO only. 6002f11bbc2SYoshihiro Shimoda */ 6012f11bbc2SYoshihiro Shimoda UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, 60296a7141dSManivannan Sadhasivam 60396a7141dSManivannan Sadhasivam /* 60496a7141dSManivannan Sadhasivam * This quirk needs to be enabled if the host controller needs 60596a7141dSManivannan Sadhasivam * to reinit the device after switching to maximum gear. 60696a7141dSManivannan Sadhasivam */ 60796a7141dSManivannan Sadhasivam UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, 608dd11376bSBart Van Assche }; 609dd11376bSBart Van Assche 610dd11376bSBart Van Assche enum ufshcd_caps { 611dd11376bSBart Van Assche /* Allow dynamic clk gating */ 612dd11376bSBart Van Assche UFSHCD_CAP_CLK_GATING = 1 << 0, 613dd11376bSBart Van Assche 614dd11376bSBart Van Assche /* Allow hiberb8 with clk gating */ 615dd11376bSBart Van Assche UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, 616dd11376bSBart Van Assche 617dd11376bSBart Van Assche /* Allow dynamic clk scaling */ 618dd11376bSBart Van Assche UFSHCD_CAP_CLK_SCALING = 1 << 2, 619dd11376bSBart Van Assche 620dd11376bSBart Van Assche /* Allow auto bkops to enabled during runtime suspend */ 621dd11376bSBart Van Assche UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, 622dd11376bSBart Van Assche 623dd11376bSBart Van Assche /* 624dd11376bSBart Van Assche * This capability allows host controller driver to use the UFS HCI's 625dd11376bSBart Van Assche * interrupt aggregation capability. 626dd11376bSBart Van Assche * CAUTION: Enabling this might reduce overall UFS throughput. 627dd11376bSBart Van Assche */ 628dd11376bSBart Van Assche UFSHCD_CAP_INTR_AGGR = 1 << 4, 629dd11376bSBart Van Assche 630dd11376bSBart Van Assche /* 631dd11376bSBart Van Assche * This capability allows the device auto-bkops to be always enabled 632dd11376bSBart Van Assche * except during suspend (both runtime and suspend). 633dd11376bSBart Van Assche * Enabling this capability means that device will always be allowed 634dd11376bSBart Van Assche * to do background operation when it's active but it might degrade 635dd11376bSBart Van Assche * the performance of ongoing read/write operations. 636dd11376bSBart Van Assche */ 637dd11376bSBart Van Assche UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, 638dd11376bSBart Van Assche 639dd11376bSBart Van Assche /* 640dd11376bSBart Van Assche * This capability allows host controller driver to automatically 641dd11376bSBart Van Assche * enable runtime power management by itself instead of waiting 642dd11376bSBart Van Assche * for userspace to control the power management. 643dd11376bSBart Van Assche */ 644dd11376bSBart Van Assche UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, 645dd11376bSBart Van Assche 646dd11376bSBart Van Assche /* 647dd11376bSBart Van Assche * This capability allows the host controller driver to turn-on 648dd11376bSBart Van Assche * WriteBooster, if the underlying device supports it and is 649dd11376bSBart Van Assche * provisioned to be used. This would increase the write performance. 650dd11376bSBart Van Assche */ 651dd11376bSBart Van Assche UFSHCD_CAP_WB_EN = 1 << 7, 652dd11376bSBart Van Assche 653dd11376bSBart Van Assche /* 654dd11376bSBart Van Assche * This capability allows the host controller driver to use the 655dd11376bSBart Van Assche * inline crypto engine, if it is present 656dd11376bSBart Van Assche */ 657dd11376bSBart Van Assche UFSHCD_CAP_CRYPTO = 1 << 8, 658dd11376bSBart Van Assche 659dd11376bSBart Van Assche /* 660dd11376bSBart Van Assche * This capability allows the controller regulators to be put into 661dd11376bSBart Van Assche * lpm mode aggressively during clock gating. 662dd11376bSBart Van Assche * This would increase power savings. 663dd11376bSBart Van Assche */ 664dd11376bSBart Van Assche UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, 665dd11376bSBart Van Assche 666dd11376bSBart Van Assche /* 667dd11376bSBart Van Assche * This capability allows the host controller driver to use DeepSleep, 668dd11376bSBart Van Assche * if it is supported by the UFS device. The host controller driver must 669dd11376bSBart Van Assche * support device hardware reset via the hba->device_reset() callback, 670dd11376bSBart Van Assche * in order to exit DeepSleep state. 671dd11376bSBart Van Assche */ 672dd11376bSBart Van Assche UFSHCD_CAP_DEEPSLEEP = 1 << 10, 673dd11376bSBart Van Assche 674dd11376bSBart Van Assche /* 675dd11376bSBart Van Assche * This capability allows the host controller driver to use temperature 676dd11376bSBart Van Assche * notification if it is supported by the UFS device. 677dd11376bSBart Van Assche */ 678dd11376bSBart Van Assche UFSHCD_CAP_TEMP_NOTIF = 1 << 11, 67987bd0501SPeter Wang 68087bd0501SPeter Wang /* 68187bd0501SPeter Wang * Enable WriteBooster when scaling up the clock and disable 68287bd0501SPeter Wang * WriteBooster when scaling the clock down. 68387bd0501SPeter Wang */ 68487bd0501SPeter Wang UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, 685dd11376bSBart Van Assche }; 686dd11376bSBart Van Assche 687dd11376bSBart Van Assche struct ufs_hba_variant_params { 688dd11376bSBart Van Assche struct devfreq_dev_profile devfreq_profile; 689dd11376bSBart Van Assche struct devfreq_simple_ondemand_data ondemand_data; 690dd11376bSBart Van Assche u16 hba_enable_delay_us; 691dd11376bSBart Van Assche u32 wb_flush_threshold; 692dd11376bSBart Van Assche }; 693dd11376bSBart Van Assche 694dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_HPB 695dd11376bSBart Van Assche /** 696dd11376bSBart Van Assche * struct ufshpb_dev_info - UFSHPB device related info 697dd11376bSBart Van Assche * @num_lu: the number of user logical unit to check whether all lu finished 698dd11376bSBart Van Assche * initialization 699dd11376bSBart Van Assche * @rgn_size: device reported HPB region size 700dd11376bSBart Van Assche * @srgn_size: device reported HPB sub-region size 701dd11376bSBart Van Assche * @slave_conf_cnt: counter to check all lu finished initialization 702dd11376bSBart Van Assche * @hpb_disabled: flag to check if HPB is disabled 703dd11376bSBart Van Assche * @max_hpb_single_cmd: device reported bMAX_DATA_SIZE_FOR_SINGLE_CMD value 704dd11376bSBart Van Assche * @is_legacy: flag to check HPB 1.0 705dd11376bSBart Van Assche * @control_mode: either host or device 706dd11376bSBart Van Assche */ 707dd11376bSBart Van Assche struct ufshpb_dev_info { 708dd11376bSBart Van Assche int num_lu; 709dd11376bSBart Van Assche int rgn_size; 710dd11376bSBart Van Assche int srgn_size; 711dd11376bSBart Van Assche atomic_t slave_conf_cnt; 712dd11376bSBart Van Assche bool hpb_disabled; 713dd11376bSBart Van Assche u8 max_hpb_single_cmd; 714dd11376bSBart Van Assche bool is_legacy; 715dd11376bSBart Van Assche u8 control_mode; 716dd11376bSBart Van Assche }; 717dd11376bSBart Van Assche #endif 718dd11376bSBart Van Assche 719dd11376bSBart Van Assche struct ufs_hba_monitor { 720dd11376bSBart Van Assche unsigned long chunk_size; 721dd11376bSBart Van Assche 722dd11376bSBart Van Assche unsigned long nr_sec_rw[2]; 723dd11376bSBart Van Assche ktime_t total_busy[2]; 724dd11376bSBart Van Assche 725dd11376bSBart Van Assche unsigned long nr_req[2]; 726dd11376bSBart Van Assche /* latencies*/ 727dd11376bSBart Van Assche ktime_t lat_sum[2]; 728dd11376bSBart Van Assche ktime_t lat_max[2]; 729dd11376bSBart Van Assche ktime_t lat_min[2]; 730dd11376bSBart Van Assche 731dd11376bSBart Van Assche u32 nr_queued[2]; 732dd11376bSBart Van Assche ktime_t busy_start_ts[2]; 733dd11376bSBart Van Assche 734dd11376bSBart Van Assche ktime_t enabled_ts; 735dd11376bSBart Van Assche bool enabled; 736dd11376bSBart Van Assche }; 737dd11376bSBart Van Assche 738dd11376bSBart Van Assche /** 739*c263b4efSAsutosh Das * struct ufshcd_res_info_t - MCQ related resource regions 740*c263b4efSAsutosh Das * 741*c263b4efSAsutosh Das * @name: resource name 742*c263b4efSAsutosh Das * @resource: pointer to resource region 743*c263b4efSAsutosh Das * @base: register base address 744*c263b4efSAsutosh Das */ 745*c263b4efSAsutosh Das struct ufshcd_res_info { 746*c263b4efSAsutosh Das const char *name; 747*c263b4efSAsutosh Das struct resource *resource; 748*c263b4efSAsutosh Das void __iomem *base; 749*c263b4efSAsutosh Das }; 750*c263b4efSAsutosh Das 751*c263b4efSAsutosh Das enum ufshcd_res { 752*c263b4efSAsutosh Das RES_UFS, 753*c263b4efSAsutosh Das RES_MCQ, 754*c263b4efSAsutosh Das RES_MCQ_SQD, 755*c263b4efSAsutosh Das RES_MCQ_SQIS, 756*c263b4efSAsutosh Das RES_MCQ_CQD, 757*c263b4efSAsutosh Das RES_MCQ_CQIS, 758*c263b4efSAsutosh Das RES_MCQ_VS, 759*c263b4efSAsutosh Das RES_MAX, 760*c263b4efSAsutosh Das }; 761*c263b4efSAsutosh Das 762*c263b4efSAsutosh Das /** 763dd11376bSBart Van Assche * struct ufs_hba - per adapter private structure 764dd11376bSBart Van Assche * @mmio_base: UFSHCI base register address 765dd11376bSBart Van Assche * @ucdl_base_addr: UFS Command Descriptor base address 766dd11376bSBart Van Assche * @utrdl_base_addr: UTP Transfer Request Descriptor base address 767dd11376bSBart Van Assche * @utmrdl_base_addr: UTP Task Management Descriptor base address 768dd11376bSBart Van Assche * @ucdl_dma_addr: UFS Command Descriptor DMA address 769dd11376bSBart Van Assche * @utrdl_dma_addr: UTRDL DMA address 770dd11376bSBart Van Assche * @utmrdl_dma_addr: UTMRDL DMA address 771dd11376bSBart Van Assche * @host: Scsi_Host instance of the driver 772dd11376bSBart Van Assche * @dev: device handle 773dd11376bSBart Van Assche * @ufs_device_wlun: WLUN that controls the entire UFS device. 774dd11376bSBart Van Assche * @hwmon_device: device instance registered with the hwmon core. 775dd11376bSBart Van Assche * @curr_dev_pwr_mode: active UFS device power mode. 776dd11376bSBart Van Assche * @uic_link_state: active state of the link to the UFS device. 777dd11376bSBart Van Assche * @rpm_lvl: desired UFS power management level during runtime PM. 778dd11376bSBart Van Assche * @spm_lvl: desired UFS power management level during system PM. 779dd11376bSBart Van Assche * @pm_op_in_progress: whether or not a PM operation is in progress. 780dd11376bSBart Van Assche * @ahit: value of Auto-Hibernate Idle Timer register. 781dd11376bSBart Van Assche * @lrb: local reference block 782dd11376bSBart Van Assche * @outstanding_tasks: Bits representing outstanding task requests 783dd11376bSBart Van Assche * @outstanding_lock: Protects @outstanding_reqs. 784dd11376bSBart Van Assche * @outstanding_reqs: Bits representing outstanding transfer requests 785dd11376bSBart Van Assche * @capabilities: UFS Controller Capabilities 7866e1d850aSAsutosh Das * @mcq_capabilities: UFS Multi Circular Queue capabilities 787dd11376bSBart Van Assche * @nutrs: Transfer Request Queue depth supported by controller 788dd11376bSBart Van Assche * @nutmrs: Task Management Queue depth supported by controller 789dd11376bSBart Van Assche * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. 790dd11376bSBart Van Assche * @ufs_version: UFS Version to which controller complies 791dd11376bSBart Van Assche * @vops: pointer to variant specific operations 792dd11376bSBart Van Assche * @vps: pointer to variant specific parameters 793dd11376bSBart Van Assche * @priv: pointer to variant specific private data 794ada1e653SEric Biggers * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields) 795dd11376bSBart Van Assche * @irq: Irq number of the controller 796dd11376bSBart Van Assche * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. 797dd11376bSBart Van Assche * @dev_ref_clk_freq: reference clock frequency 798dd11376bSBart Van Assche * @quirks: bitmask with information about deviations from the UFSHCI standard. 799dd11376bSBart Van Assche * @dev_quirks: bitmask with information about deviations from the UFS standard. 800dd11376bSBart Van Assche * @tmf_tag_set: TMF tag set. 801dd11376bSBart Van Assche * @tmf_queue: Used to allocate TMF tags. 802dd11376bSBart Van Assche * @tmf_rqs: array with pointers to TMF requests while these are in progress. 803dd11376bSBart Van Assche * @active_uic_cmd: handle of active UIC command 804dd11376bSBart Van Assche * @uic_cmd_mutex: mutex for UIC command 805dd11376bSBart Van Assche * @uic_async_done: completion used during UIC processing 806dd11376bSBart Van Assche * @ufshcd_state: UFSHCD state 807dd11376bSBart Van Assche * @eh_flags: Error handling flags 808dd11376bSBart Van Assche * @intr_mask: Interrupt Mask Bits 809dd11376bSBart Van Assche * @ee_ctrl_mask: Exception event control mask 810dd11376bSBart Van Assche * @ee_drv_mask: Exception event mask for driver 811dd11376bSBart Van Assche * @ee_usr_mask: Exception event mask for user (set via debugfs) 812dd11376bSBart Van Assche * @ee_ctrl_mutex: Used to serialize exception event information. 813dd11376bSBart Van Assche * @is_powered: flag to check if HBA is powered 814dd11376bSBart Van Assche * @shutting_down: flag to check if shutdown has been invoked 815dd11376bSBart Van Assche * @host_sem: semaphore used to serialize concurrent contexts 816dd11376bSBart Van Assche * @eh_wq: Workqueue that eh_work works on 817dd11376bSBart Van Assche * @eh_work: Worker to handle UFS errors that require s/w attention 818dd11376bSBart Van Assche * @eeh_work: Worker to handle exception events 819dd11376bSBart Van Assche * @errors: HBA errors 820dd11376bSBart Van Assche * @uic_error: UFS interconnect layer error status 821dd11376bSBart Van Assche * @saved_err: sticky error mask 822dd11376bSBart Van Assche * @saved_uic_err: sticky UIC error mask 823dd11376bSBart Van Assche * @ufs_stats: various error counters 824dd11376bSBart Van Assche * @force_reset: flag to force eh_work perform a full reset 825dd11376bSBart Van Assche * @force_pmc: flag to force a power mode change 826dd11376bSBart Van Assche * @silence_err_logs: flag to silence error logs 827dd11376bSBart Van Assche * @dev_cmd: ufs device management command information 828dd11376bSBart Van Assche * @last_dme_cmd_tstamp: time stamp of the last completed DME command 829dd11376bSBart Van Assche * @nop_out_timeout: NOP OUT timeout value 830dd11376bSBart Van Assche * @dev_info: information about the UFS device 831dd11376bSBart Van Assche * @auto_bkops_enabled: to track whether bkops is enabled in device 832dd11376bSBart Van Assche * @vreg_info: UFS device voltage regulator information 833dd11376bSBart Van Assche * @clk_list_head: UFS host controller clocks list node head 834dd11376bSBart Van Assche * @req_abort_count: number of times ufshcd_abort() has been called 835dd11376bSBart Van Assche * @lanes_per_direction: number of lanes per data direction between the UFS 836dd11376bSBart Van Assche * controller and the UFS device. 837dd11376bSBart Van Assche * @pwr_info: holds current power mode 838dd11376bSBart Van Assche * @max_pwr_info: keeps the device max valid pwm 839dd11376bSBart Van Assche * @clk_gating: information related to clock gating 840dd11376bSBart Van Assche * @caps: bitmask with information about UFS controller capabilities 841dd11376bSBart Van Assche * @devfreq: frequency scaling information owned by the devfreq core 842dd11376bSBart Van Assche * @clk_scaling: frequency scaling information owned by the UFS driver 8431a547cbcSBart Van Assche * @system_suspending: system suspend has been started and system resume has 8441a547cbcSBart Van Assche * not yet finished. 8451a547cbcSBart Van Assche * @is_sys_suspended: UFS device has been suspended because of system suspend 846dd11376bSBart Van Assche * @urgent_bkops_lvl: keeps track of urgent bkops level for device 847dd11376bSBart Van Assche * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for 848dd11376bSBart Van Assche * device is known or not. 849dd11376bSBart Van Assche * @clk_scaling_lock: used to serialize device commands and clock scaling 850dd11376bSBart Van Assche * @desc_size: descriptor sizes reported by device 851dd11376bSBart Van Assche * @scsi_block_reqs_cnt: reference counting for scsi block requests 852dd11376bSBart Van Assche * @bsg_dev: struct device associated with the BSG queue 853dd11376bSBart Van Assche * @bsg_queue: BSG queue associated with the UFS controller 854dd11376bSBart Van Assche * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power 855dd11376bSBart Van Assche * management) after the UFS device has finished a WriteBooster buffer 856dd11376bSBart Van Assche * flush or auto BKOP. 857dd11376bSBart Van Assche * @ufshpb_dev: information related to HPB (Host Performance Booster). 858dd11376bSBart Van Assche * @monitor: statistics about UFS commands 859dd11376bSBart Van Assche * @crypto_capabilities: Content of crypto capabilities register (0x100) 860dd11376bSBart Van Assche * @crypto_cap_array: Array of crypto capabilities 861dd11376bSBart Van Assche * @crypto_cfg_register: Start of the crypto cfg array 862dd11376bSBart Van Assche * @crypto_profile: the crypto profile of this hba (if applicable) 863dd11376bSBart Van Assche * @debugfs_root: UFS controller debugfs root directory 864dd11376bSBart Van Assche * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay 865dd11376bSBart Van Assche * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore 866dd11376bSBart Van Assche * ee_ctrl_mask 867dd11376bSBart Van Assche * @luns_avail: number of regular and well known LUNs supported by the UFS 868dd11376bSBart Van Assche * device 86957b1c0efSAsutosh Das * @nr_hw_queues: number of hardware queues configured 87057b1c0efSAsutosh Das * @nr_queues: number of Queues of different queue types 871dd11376bSBart Van Assche * @complete_put: whether or not to call ufshcd_rpm_put() from inside 872dd11376bSBart Van Assche * ufshcd_resume_complete() 8736e1d850aSAsutosh Das * @ext_iid_sup: is EXT_IID is supported by UFSHC 874305a357dSAsutosh Das * @mcq_sup: is mcq supported by UFSHC 875*c263b4efSAsutosh Das * @res: array of resource info of MCQ registers 876*c263b4efSAsutosh Das * @mcq_base: Multi circular queue registers base address 877dd11376bSBart Van Assche */ 878dd11376bSBart Van Assche struct ufs_hba { 879dd11376bSBart Van Assche void __iomem *mmio_base; 880dd11376bSBart Van Assche 881dd11376bSBart Van Assche /* Virtual memory reference */ 882dd11376bSBart Van Assche struct utp_transfer_cmd_desc *ucdl_base_addr; 883dd11376bSBart Van Assche struct utp_transfer_req_desc *utrdl_base_addr; 884dd11376bSBart Van Assche struct utp_task_req_desc *utmrdl_base_addr; 885dd11376bSBart Van Assche 886dd11376bSBart Van Assche /* DMA memory reference */ 887dd11376bSBart Van Assche dma_addr_t ucdl_dma_addr; 888dd11376bSBart Van Assche dma_addr_t utrdl_dma_addr; 889dd11376bSBart Van Assche dma_addr_t utmrdl_dma_addr; 890dd11376bSBart Van Assche 891dd11376bSBart Van Assche struct Scsi_Host *host; 892dd11376bSBart Van Assche struct device *dev; 893dd11376bSBart Van Assche struct scsi_device *ufs_device_wlun; 894dd11376bSBart Van Assche 895dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_HWMON 896dd11376bSBart Van Assche struct device *hwmon_device; 897dd11376bSBart Van Assche #endif 898dd11376bSBart Van Assche 899dd11376bSBart Van Assche enum ufs_dev_pwr_mode curr_dev_pwr_mode; 900dd11376bSBart Van Assche enum uic_link_state uic_link_state; 901dd11376bSBart Van Assche /* Desired UFS power management level during runtime PM */ 902dd11376bSBart Van Assche enum ufs_pm_level rpm_lvl; 903dd11376bSBart Van Assche /* Desired UFS power management level during system PM */ 904dd11376bSBart Van Assche enum ufs_pm_level spm_lvl; 905dd11376bSBart Van Assche int pm_op_in_progress; 906dd11376bSBart Van Assche 907dd11376bSBart Van Assche /* Auto-Hibernate Idle Timer register value */ 908dd11376bSBart Van Assche u32 ahit; 909dd11376bSBart Van Assche 910dd11376bSBart Van Assche struct ufshcd_lrb *lrb; 911dd11376bSBart Van Assche 912dd11376bSBart Van Assche unsigned long outstanding_tasks; 913dd11376bSBart Van Assche spinlock_t outstanding_lock; 914dd11376bSBart Van Assche unsigned long outstanding_reqs; 915dd11376bSBart Van Assche 916dd11376bSBart Van Assche u32 capabilities; 917dd11376bSBart Van Assche int nutrs; 9186e1d850aSAsutosh Das u32 mcq_capabilities; 919dd11376bSBart Van Assche int nutmrs; 920dd11376bSBart Van Assche u32 reserved_slot; 921dd11376bSBart Van Assche u32 ufs_version; 922dd11376bSBart Van Assche const struct ufs_hba_variant_ops *vops; 923dd11376bSBart Van Assche struct ufs_hba_variant_params *vps; 924dd11376bSBart Van Assche void *priv; 925ada1e653SEric Biggers #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 926ada1e653SEric Biggers size_t sg_entry_size; 927ada1e653SEric Biggers #endif 928dd11376bSBart Van Assche unsigned int irq; 929dd11376bSBart Van Assche bool is_irq_enabled; 930dd11376bSBart Van Assche enum ufs_ref_clk_freq dev_ref_clk_freq; 931dd11376bSBart Van Assche 932dd11376bSBart Van Assche unsigned int quirks; /* Deviations from standard UFSHCI spec. */ 933dd11376bSBart Van Assche 934dd11376bSBart Van Assche /* Device deviations from standard UFS device spec. */ 935dd11376bSBart Van Assche unsigned int dev_quirks; 936dd11376bSBart Van Assche 937dd11376bSBart Van Assche struct blk_mq_tag_set tmf_tag_set; 938dd11376bSBart Van Assche struct request_queue *tmf_queue; 939dd11376bSBart Van Assche struct request **tmf_rqs; 940dd11376bSBart Van Assche 941dd11376bSBart Van Assche struct uic_command *active_uic_cmd; 942dd11376bSBart Van Assche struct mutex uic_cmd_mutex; 943dd11376bSBart Van Assche struct completion *uic_async_done; 944dd11376bSBart Van Assche 945dd11376bSBart Van Assche enum ufshcd_state ufshcd_state; 946dd11376bSBart Van Assche u32 eh_flags; 947dd11376bSBart Van Assche u32 intr_mask; 948dd11376bSBart Van Assche u16 ee_ctrl_mask; 949dd11376bSBart Van Assche u16 ee_drv_mask; 950dd11376bSBart Van Assche u16 ee_usr_mask; 951dd11376bSBart Van Assche struct mutex ee_ctrl_mutex; 952dd11376bSBart Van Assche bool is_powered; 953dd11376bSBart Van Assche bool shutting_down; 954dd11376bSBart Van Assche struct semaphore host_sem; 955dd11376bSBart Van Assche 956dd11376bSBart Van Assche /* Work Queues */ 957dd11376bSBart Van Assche struct workqueue_struct *eh_wq; 958dd11376bSBart Van Assche struct work_struct eh_work; 959dd11376bSBart Van Assche struct work_struct eeh_work; 960dd11376bSBart Van Assche 961dd11376bSBart Van Assche /* HBA Errors */ 962dd11376bSBart Van Assche u32 errors; 963dd11376bSBart Van Assche u32 uic_error; 964dd11376bSBart Van Assche u32 saved_err; 965dd11376bSBart Van Assche u32 saved_uic_err; 966dd11376bSBart Van Assche struct ufs_stats ufs_stats; 967dd11376bSBart Van Assche bool force_reset; 968dd11376bSBart Van Assche bool force_pmc; 969dd11376bSBart Van Assche bool silence_err_logs; 970dd11376bSBart Van Assche 971dd11376bSBart Van Assche /* Device management request data */ 972dd11376bSBart Van Assche struct ufs_dev_cmd dev_cmd; 973dd11376bSBart Van Assche ktime_t last_dme_cmd_tstamp; 974dd11376bSBart Van Assche int nop_out_timeout; 975dd11376bSBart Van Assche 976dd11376bSBart Van Assche /* Keeps information of the UFS device connected to this host */ 977dd11376bSBart Van Assche struct ufs_dev_info dev_info; 978dd11376bSBart Van Assche bool auto_bkops_enabled; 979dd11376bSBart Van Assche struct ufs_vreg_info vreg_info; 980dd11376bSBart Van Assche struct list_head clk_list_head; 981dd11376bSBart Van Assche 982dd11376bSBart Van Assche /* Number of requests aborts */ 983dd11376bSBart Van Assche int req_abort_count; 984dd11376bSBart Van Assche 985dd11376bSBart Van Assche /* Number of lanes available (1 or 2) for Rx/Tx */ 986dd11376bSBart Van Assche u32 lanes_per_direction; 987dd11376bSBart Van Assche struct ufs_pa_layer_attr pwr_info; 988dd11376bSBart Van Assche struct ufs_pwr_mode_info max_pwr_info; 989dd11376bSBart Van Assche 990dd11376bSBart Van Assche struct ufs_clk_gating clk_gating; 991dd11376bSBart Van Assche /* Control to enable/disable host capabilities */ 992dd11376bSBart Van Assche u32 caps; 993dd11376bSBart Van Assche 994dd11376bSBart Van Assche struct devfreq *devfreq; 995dd11376bSBart Van Assche struct ufs_clk_scaling clk_scaling; 9961a547cbcSBart Van Assche bool system_suspending; 997dd11376bSBart Van Assche bool is_sys_suspended; 998dd11376bSBart Van Assche 999dd11376bSBart Van Assche enum bkops_status urgent_bkops_lvl; 1000dd11376bSBart Van Assche bool is_urgent_bkops_lvl_checked; 1001dd11376bSBart Van Assche 1002dd11376bSBart Van Assche struct rw_semaphore clk_scaling_lock; 1003dd11376bSBart Van Assche atomic_t scsi_block_reqs_cnt; 1004dd11376bSBart Van Assche 1005dd11376bSBart Van Assche struct device bsg_dev; 1006dd11376bSBart Van Assche struct request_queue *bsg_queue; 1007dd11376bSBart Van Assche struct delayed_work rpm_dev_flush_recheck_work; 1008dd11376bSBart Van Assche 1009dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_HPB 1010dd11376bSBart Van Assche struct ufshpb_dev_info ufshpb_dev; 1011dd11376bSBart Van Assche #endif 1012dd11376bSBart Van Assche 1013dd11376bSBart Van Assche struct ufs_hba_monitor monitor; 1014dd11376bSBart Van Assche 1015dd11376bSBart Van Assche #ifdef CONFIG_SCSI_UFS_CRYPTO 1016dd11376bSBart Van Assche union ufs_crypto_capabilities crypto_capabilities; 1017dd11376bSBart Van Assche union ufs_crypto_cap_entry *crypto_cap_array; 1018dd11376bSBart Van Assche u32 crypto_cfg_register; 1019dd11376bSBart Van Assche struct blk_crypto_profile crypto_profile; 1020dd11376bSBart Van Assche #endif 1021dd11376bSBart Van Assche #ifdef CONFIG_DEBUG_FS 1022dd11376bSBart Van Assche struct dentry *debugfs_root; 1023dd11376bSBart Van Assche struct delayed_work debugfs_ee_work; 1024dd11376bSBart Van Assche u32 debugfs_ee_rate_limit_ms; 1025dd11376bSBart Van Assche #endif 1026dd11376bSBart Van Assche u32 luns_avail; 102757b1c0efSAsutosh Das unsigned int nr_hw_queues; 102857b1c0efSAsutosh Das unsigned int nr_queues[HCTX_MAX_TYPES]; 1029dd11376bSBart Van Assche bool complete_put; 10306e1d850aSAsutosh Das bool ext_iid_sup; 10310cab4023SAsutosh Das bool scsi_host_added; 1032305a357dSAsutosh Das bool mcq_sup; 1033*c263b4efSAsutosh Das struct ufshcd_res_info res[RES_MAX]; 1034*c263b4efSAsutosh Das void __iomem *mcq_base; 1035dd11376bSBart Van Assche }; 1036dd11376bSBart Van Assche 1037ada1e653SEric Biggers #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 1038ada1e653SEric Biggers static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1039ada1e653SEric Biggers { 1040ada1e653SEric Biggers return hba->sg_entry_size; 1041ada1e653SEric Biggers } 1042ada1e653SEric Biggers 1043ada1e653SEric Biggers static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size) 1044ada1e653SEric Biggers { 1045ada1e653SEric Biggers WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry)); 1046ada1e653SEric Biggers hba->sg_entry_size = sg_entry_size; 1047ada1e653SEric Biggers } 1048ada1e653SEric Biggers #else 1049ada1e653SEric Biggers static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1050ada1e653SEric Biggers { 1051ada1e653SEric Biggers return sizeof(struct ufshcd_sg_entry); 1052ada1e653SEric Biggers } 1053ada1e653SEric Biggers 1054ada1e653SEric Biggers #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \ 1055ada1e653SEric Biggers ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) 1056ada1e653SEric Biggers #endif 1057ada1e653SEric Biggers 1058ada1e653SEric Biggers static inline size_t sizeof_utp_transfer_cmd_desc(const struct ufs_hba *hba) 1059ada1e653SEric Biggers { 1060ada1e653SEric Biggers return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); 1061ada1e653SEric Biggers } 1062ada1e653SEric Biggers 1063dd11376bSBart Van Assche /* Returns true if clocks can be gated. Otherwise false */ 1064dd11376bSBart Van Assche static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) 1065dd11376bSBart Van Assche { 1066dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_CLK_GATING; 1067dd11376bSBart Van Assche } 1068dd11376bSBart Van Assche static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) 1069dd11376bSBart Van Assche { 1070dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1071dd11376bSBart Van Assche } 1072dd11376bSBart Van Assche static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) 1073dd11376bSBart Van Assche { 1074dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_CLK_SCALING; 1075dd11376bSBart Van Assche } 1076dd11376bSBart Van Assche static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) 1077dd11376bSBart Van Assche { 1078dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1079dd11376bSBart Van Assche } 1080dd11376bSBart Van Assche static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) 1081dd11376bSBart Van Assche { 1082dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; 1083dd11376bSBart Van Assche } 1084dd11376bSBart Van Assche 1085dd11376bSBart Van Assche static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) 1086dd11376bSBart Van Assche { 1087dd11376bSBart Van Assche return (hba->caps & UFSHCD_CAP_INTR_AGGR) && 1088dd11376bSBart Van Assche !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); 1089dd11376bSBart Van Assche } 1090dd11376bSBart Van Assche 1091dd11376bSBart Van Assche static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) 1092dd11376bSBart Van Assche { 1093dd11376bSBart Van Assche return !!(ufshcd_is_link_hibern8(hba) && 1094dd11376bSBart Van Assche (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); 1095dd11376bSBart Van Assche } 1096dd11376bSBart Van Assche 1097dd11376bSBart Van Assche static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) 1098dd11376bSBart Van Assche { 1099dd11376bSBart Van Assche return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && 1100dd11376bSBart Van Assche !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); 1101dd11376bSBart Van Assche } 1102dd11376bSBart Van Assche 1103dd11376bSBart Van Assche static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) 1104dd11376bSBart Van Assche { 1105dd11376bSBart Van Assche return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); 1106dd11376bSBart Van Assche } 1107dd11376bSBart Van Assche 1108dd11376bSBart Van Assche static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) 1109dd11376bSBart Van Assche { 1110dd11376bSBart Van Assche return hba->caps & UFSHCD_CAP_WB_EN; 1111dd11376bSBart Van Assche } 1112dd11376bSBart Van Assche 111387bd0501SPeter Wang static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) 111487bd0501SPeter Wang { 111587bd0501SPeter Wang return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; 111687bd0501SPeter Wang } 111787bd0501SPeter Wang 1118dd11376bSBart Van Assche #define ufshcd_writel(hba, val, reg) \ 1119dd11376bSBart Van Assche writel((val), (hba)->mmio_base + (reg)) 1120dd11376bSBart Van Assche #define ufshcd_readl(hba, reg) \ 1121dd11376bSBart Van Assche readl((hba)->mmio_base + (reg)) 1122dd11376bSBart Van Assche 1123dd11376bSBart Van Assche /** 1124dd11376bSBart Van Assche * ufshcd_rmwl - perform read/modify/write for a controller register 1125dd11376bSBart Van Assche * @hba: per adapter instance 1126dd11376bSBart Van Assche * @mask: mask to apply on read value 1127dd11376bSBart Van Assche * @val: actual value to write 1128dd11376bSBart Van Assche * @reg: register address 1129dd11376bSBart Van Assche */ 1130dd11376bSBart Van Assche static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) 1131dd11376bSBart Van Assche { 1132dd11376bSBart Van Assche u32 tmp; 1133dd11376bSBart Van Assche 1134dd11376bSBart Van Assche tmp = ufshcd_readl(hba, reg); 1135dd11376bSBart Van Assche tmp &= ~mask; 1136dd11376bSBart Van Assche tmp |= (val & mask); 1137dd11376bSBart Van Assche ufshcd_writel(hba, tmp, reg); 1138dd11376bSBart Van Assche } 1139dd11376bSBart Van Assche 1140dd11376bSBart Van Assche int ufshcd_alloc_host(struct device *, struct ufs_hba **); 1141dd11376bSBart Van Assche void ufshcd_dealloc_host(struct ufs_hba *); 1142dd11376bSBart Van Assche int ufshcd_hba_enable(struct ufs_hba *hba); 1143dd11376bSBart Van Assche int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); 1144dd11376bSBart Van Assche int ufshcd_link_recovery(struct ufs_hba *hba); 1145dd11376bSBart Van Assche int ufshcd_make_hba_operational(struct ufs_hba *hba); 1146dd11376bSBart Van Assche void ufshcd_remove(struct ufs_hba *); 1147dd11376bSBart Van Assche int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); 1148dd11376bSBart Van Assche int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); 1149dd11376bSBart Van Assche void ufshcd_delay_us(unsigned long us, unsigned long tolerance); 1150dd11376bSBart Van Assche void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); 1151dd11376bSBart Van Assche void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); 1152dd11376bSBart Van Assche void ufshcd_hba_stop(struct ufs_hba *hba); 1153dd11376bSBart Van Assche void ufshcd_schedule_eh_work(struct ufs_hba *hba); 1154dd11376bSBart Van Assche 1155dd11376bSBart Van Assche /** 1156dd11376bSBart Van Assche * ufshcd_set_variant - set variant specific data to the hba 1157dd11376bSBart Van Assche * @hba: per adapter instance 1158dd11376bSBart Van Assche * @variant: pointer to variant specific data 1159dd11376bSBart Van Assche */ 1160dd11376bSBart Van Assche static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) 1161dd11376bSBart Van Assche { 1162dd11376bSBart Van Assche BUG_ON(!hba); 1163dd11376bSBart Van Assche hba->priv = variant; 1164dd11376bSBart Van Assche } 1165dd11376bSBart Van Assche 1166dd11376bSBart Van Assche /** 1167dd11376bSBart Van Assche * ufshcd_get_variant - get variant specific data from the hba 1168dd11376bSBart Van Assche * @hba: per adapter instance 1169dd11376bSBart Van Assche */ 1170dd11376bSBart Van Assche static inline void *ufshcd_get_variant(struct ufs_hba *hba) 1171dd11376bSBart Van Assche { 1172dd11376bSBart Van Assche BUG_ON(!hba); 1173dd11376bSBart Van Assche return hba->priv; 1174dd11376bSBart Van Assche } 1175dd11376bSBart Van Assche 1176dd11376bSBart Van Assche #ifdef CONFIG_PM 1177dd11376bSBart Van Assche extern int ufshcd_runtime_suspend(struct device *dev); 1178dd11376bSBart Van Assche extern int ufshcd_runtime_resume(struct device *dev); 1179dd11376bSBart Van Assche #endif 1180dd11376bSBart Van Assche #ifdef CONFIG_PM_SLEEP 1181dd11376bSBart Van Assche extern int ufshcd_system_suspend(struct device *dev); 1182dd11376bSBart Van Assche extern int ufshcd_system_resume(struct device *dev); 1183dd11376bSBart Van Assche #endif 1184dd11376bSBart Van Assche extern int ufshcd_shutdown(struct ufs_hba *hba); 1185dd11376bSBart Van Assche extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 1186dd11376bSBart Van Assche int agreed_gear, 1187dd11376bSBart Van Assche int adapt_val); 1188dd11376bSBart Van Assche extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 1189dd11376bSBart Van Assche u8 attr_set, u32 mib_val, u8 peer); 1190dd11376bSBart Van Assche extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 1191dd11376bSBart Van Assche u32 *mib_val, u8 peer); 1192dd11376bSBart Van Assche extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, 1193dd11376bSBart Van Assche struct ufs_pa_layer_attr *desired_pwr_mode); 1194fc53683bSStanley Chu extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); 1195dd11376bSBart Van Assche 1196dd11376bSBart Van Assche /* UIC command interfaces for DME primitives */ 1197dd11376bSBart Van Assche #define DME_LOCAL 0 1198dd11376bSBart Van Assche #define DME_PEER 1 1199dd11376bSBart Van Assche #define ATTR_SET_NOR 0 /* NORMAL */ 1200dd11376bSBart Van Assche #define ATTR_SET_ST 1 /* STATIC */ 1201dd11376bSBart Van Assche 1202dd11376bSBart Van Assche static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 1203dd11376bSBart Van Assche u32 mib_val) 1204dd11376bSBart Van Assche { 1205dd11376bSBart Van Assche return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1206dd11376bSBart Van Assche mib_val, DME_LOCAL); 1207dd11376bSBart Van Assche } 1208dd11376bSBart Van Assche 1209dd11376bSBart Van Assche static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, 1210dd11376bSBart Van Assche u32 mib_val) 1211dd11376bSBart Van Assche { 1212dd11376bSBart Van Assche return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1213dd11376bSBart Van Assche mib_val, DME_LOCAL); 1214dd11376bSBart Van Assche } 1215dd11376bSBart Van Assche 1216dd11376bSBart Van Assche static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 1217dd11376bSBart Van Assche u32 mib_val) 1218dd11376bSBart Van Assche { 1219dd11376bSBart Van Assche return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1220dd11376bSBart Van Assche mib_val, DME_PEER); 1221dd11376bSBart Van Assche } 1222dd11376bSBart Van Assche 1223dd11376bSBart Van Assche static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, 1224dd11376bSBart Van Assche u32 mib_val) 1225dd11376bSBart Van Assche { 1226dd11376bSBart Van Assche return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1227dd11376bSBart Van Assche mib_val, DME_PEER); 1228dd11376bSBart Van Assche } 1229dd11376bSBart Van Assche 1230dd11376bSBart Van Assche static inline int ufshcd_dme_get(struct ufs_hba *hba, 1231dd11376bSBart Van Assche u32 attr_sel, u32 *mib_val) 1232dd11376bSBart Van Assche { 1233dd11376bSBart Van Assche return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 1234dd11376bSBart Van Assche } 1235dd11376bSBart Van Assche 1236dd11376bSBart Van Assche static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 1237dd11376bSBart Van Assche u32 attr_sel, u32 *mib_val) 1238dd11376bSBart Van Assche { 1239dd11376bSBart Van Assche return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 1240dd11376bSBart Van Assche } 1241dd11376bSBart Van Assche 1242dd11376bSBart Van Assche static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) 1243dd11376bSBart Van Assche { 1244dd11376bSBart Van Assche return (pwr_info->pwr_rx == FAST_MODE || 1245dd11376bSBart Van Assche pwr_info->pwr_rx == FASTAUTO_MODE) && 1246dd11376bSBart Van Assche (pwr_info->pwr_tx == FAST_MODE || 1247dd11376bSBart Van Assche pwr_info->pwr_tx == FASTAUTO_MODE); 1248dd11376bSBart Van Assche } 1249dd11376bSBart Van Assche 1250dd11376bSBart Van Assche static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) 1251dd11376bSBart Van Assche { 1252dd11376bSBart Van Assche return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); 1253dd11376bSBart Van Assche } 1254dd11376bSBart Van Assche 1255dd11376bSBart Van Assche void ufshcd_auto_hibern8_enable(struct ufs_hba *hba); 1256dd11376bSBart Van Assche void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); 1257dd11376bSBart Van Assche void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 1258dd11376bSBart Van Assche const struct ufs_dev_quirk *fixups); 1259dd11376bSBart Van Assche #define SD_ASCII_STD true 1260dd11376bSBart Van Assche #define SD_RAW false 1261dd11376bSBart Van Assche int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 1262dd11376bSBart Van Assche u8 **buf, bool ascii); 1263dd11376bSBart Van Assche 1264dd11376bSBart Van Assche int ufshcd_hold(struct ufs_hba *hba, bool async); 1265dd11376bSBart Van Assche void ufshcd_release(struct ufs_hba *hba); 1266dd11376bSBart Van Assche 1267dd11376bSBart Van Assche void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); 1268dd11376bSBart Van Assche 1269dd11376bSBart Van Assche u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); 1270dd11376bSBart Van Assche 12711d6f9decSStanley Chu int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); 12721d6f9decSStanley Chu 1273dd11376bSBart Van Assche int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); 1274dd11376bSBart Van Assche 1275dd11376bSBart Van Assche int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 1276dd11376bSBart Van Assche struct utp_upiu_req *req_upiu, 1277dd11376bSBart Van Assche struct utp_upiu_req *rsp_upiu, 1278dd11376bSBart Van Assche int msgcode, 1279dd11376bSBart Van Assche u8 *desc_buff, int *buff_len, 1280dd11376bSBart Van Assche enum query_opcode desc_op); 12816ff265fcSBean Huo int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 12826ff265fcSBean Huo struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, 12836ff265fcSBean Huo struct ufs_ehs *ehs_rsp, int sg_cnt, 12846ff265fcSBean Huo struct scatterlist *sg_list, enum dma_data_direction dir); 1285dd11376bSBart Van Assche int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); 12866c4148ceSJinyoung Choi int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); 1287dd11376bSBart Van Assche int ufshcd_suspend_prepare(struct device *dev); 1288dd11376bSBart Van Assche int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); 1289dd11376bSBart Van Assche void ufshcd_resume_complete(struct device *dev); 1290dd11376bSBart Van Assche 1291dd11376bSBart Van Assche /* Wrapper functions for safely calling variant operations */ 1292dd11376bSBart Van Assche static inline int ufshcd_vops_init(struct ufs_hba *hba) 1293dd11376bSBart Van Assche { 1294dd11376bSBart Van Assche if (hba->vops && hba->vops->init) 1295dd11376bSBart Van Assche return hba->vops->init(hba); 1296dd11376bSBart Van Assche 1297dd11376bSBart Van Assche return 0; 1298dd11376bSBart Van Assche } 1299dd11376bSBart Van Assche 1300dd11376bSBart Van Assche static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) 1301dd11376bSBart Van Assche { 1302dd11376bSBart Van Assche if (hba->vops && hba->vops->phy_initialization) 1303dd11376bSBart Van Assche return hba->vops->phy_initialization(hba); 1304dd11376bSBart Van Assche 1305dd11376bSBart Van Assche return 0; 1306dd11376bSBart Van Assche } 1307dd11376bSBart Van Assche 130835d11ec2SKrzysztof Kozlowski extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; 1309dd11376bSBart Van Assche 1310dd11376bSBart Van Assche int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1311dd11376bSBart Van Assche const char *prefix); 1312dd11376bSBart Van Assche 1313dd11376bSBart Van Assche int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); 1314dd11376bSBart Van Assche int ufshcd_write_ee_control(struct ufs_hba *hba); 131535d11ec2SKrzysztof Kozlowski int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 131635d11ec2SKrzysztof Kozlowski const u16 *other_mask, u16 set, u16 clr); 1317dd11376bSBart Van Assche 1318dd11376bSBart Van Assche #endif /* End of Header */ 1319