1e2be04c7SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ 2674e95caSDavid Howells /* 3674e95caSDavid Howells * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 4674e95caSDavid Howells * Creative Labs, Inc. 5674e95caSDavid Howells * Definitions for EMU10K1 (SB Live!) chips 6674e95caSDavid Howells */ 7674e95caSDavid Howells #ifndef _UAPI__SOUND_EMU10K1_H 8674e95caSDavid Howells #define _UAPI__SOUND_EMU10K1_H 9674e95caSDavid Howells 10d06ed0c2STakashi Iwai #ifdef __linux__ 11d06ed0c2STakashi Iwai #include <linux/types.h> 12d06ed0c2STakashi Iwai #endif 13d06ed0c2STakashi Iwai 14674e95caSDavid Howells /* 15674e95caSDavid Howells * ---- FX8010 ---- 16674e95caSDavid Howells */ 17674e95caSDavid Howells 18674e95caSDavid Howells #define EMU10K1_FX8010_PCM_COUNT 8 19674e95caSDavid Howells 20a82d24f8SMikko Rapeli /* 21a82d24f8SMikko Rapeli * Following definition is copied from linux/types.h to support compiling 22a82d24f8SMikko Rapeli * this header file in userspace since they are not generally available for 23a82d24f8SMikko Rapeli * uapi headers. 24a82d24f8SMikko Rapeli */ 25a82d24f8SMikko Rapeli #define __EMU10K1_DECLARE_BITMAP(name,bits) \ 26a82d24f8SMikko Rapeli unsigned long name[(bits) / (sizeof(unsigned long) * 8)] 27a82d24f8SMikko Rapeli 28674e95caSDavid Howells /* instruction set */ 29674e95caSDavid Howells #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */ 30674e95caSDavid Howells #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */ 31674e95caSDavid Howells #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */ 32674e95caSDavid Howells #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */ 33674e95caSDavid Howells #define iMACINT0 0x04 /* R = A + X * Y ; saturation */ 34674e95caSDavid Howells #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */ 35674e95caSDavid Howells #define iACC3 0x06 /* R = A + X + Y ; saturation */ 36674e95caSDavid Howells #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */ 37674e95caSDavid Howells #define iANDXOR 0x08 /* R = (A & X) ^ Y */ 38674e95caSDavid Howells #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */ 39674e95caSDavid Howells #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */ 40674e95caSDavid Howells #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */ 41674e95caSDavid Howells #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */ 42674e95caSDavid Howells #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */ 43674e95caSDavid Howells #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */ 44674e95caSDavid Howells #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */ 45674e95caSDavid Howells 46674e95caSDavid Howells /* GPRs */ 47674e95caSDavid Howells #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */ 48674e95caSDavid Howells #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */ 49674e95caSDavid Howells #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */ 50674e95caSDavid Howells #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */ 51674e95caSDavid Howells /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */ 52674e95caSDavid Howells 53674e95caSDavid Howells #define C_00000000 0x40 54674e95caSDavid Howells #define C_00000001 0x41 55674e95caSDavid Howells #define C_00000002 0x42 56674e95caSDavid Howells #define C_00000003 0x43 57674e95caSDavid Howells #define C_00000004 0x44 58674e95caSDavid Howells #define C_00000008 0x45 59674e95caSDavid Howells #define C_00000010 0x46 60674e95caSDavid Howells #define C_00000020 0x47 61674e95caSDavid Howells #define C_00000100 0x48 62674e95caSDavid Howells #define C_00010000 0x49 63674e95caSDavid Howells #define C_00080000 0x4a 64674e95caSDavid Howells #define C_10000000 0x4b 65674e95caSDavid Howells #define C_20000000 0x4c 66674e95caSDavid Howells #define C_40000000 0x4d 67674e95caSDavid Howells #define C_80000000 0x4e 68674e95caSDavid Howells #define C_7fffffff 0x4f 69674e95caSDavid Howells #define C_ffffffff 0x50 70674e95caSDavid Howells #define C_fffffffe 0x51 71674e95caSDavid Howells #define C_c0000000 0x52 72674e95caSDavid Howells #define C_4f1bbcdc 0x53 73674e95caSDavid Howells #define C_5a7ef9db 0x54 74674e95caSDavid Howells #define C_00100000 0x55 /* ?? */ 75674e95caSDavid Howells #define GPR_ACCU 0x56 /* ACCUM, accumulator */ 76674e95caSDavid Howells #define GPR_COND 0x57 /* CCR, condition register */ 77674e95caSDavid Howells #define GPR_NOISE0 0x58 /* noise source */ 78674e95caSDavid Howells #define GPR_NOISE1 0x59 /* noise source */ 79674e95caSDavid Howells #define GPR_IRQ 0x5a /* IRQ register */ 80674e95caSDavid Howells #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */ 81674e95caSDavid Howells #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */ 82674e95caSDavid Howells #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ 83674e95caSDavid Howells #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ 84674e95caSDavid Howells #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ 85674e95caSDavid Howells #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ 86674e95caSDavid Howells 87674e95caSDavid Howells #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 88674e95caSDavid Howells #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 89674e95caSDavid Howells #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 90674e95caSDavid Howells #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 91674e95caSDavid Howells #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 92674e95caSDavid Howells #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 93674e95caSDavid Howells 94674e95caSDavid Howells #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */ 95674e95caSDavid Howells #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */ 96674e95caSDavid Howells #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */ 97674e95caSDavid Howells #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */ 98674e95caSDavid Howells #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */ 99674e95caSDavid Howells #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */ 100674e95caSDavid Howells #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */ 101674e95caSDavid Howells #define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */ 102674e95caSDavid Howells #define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */ 103674e95caSDavid Howells #define A_GPR(x) (A_FXGPREGBASE + (x)) 104674e95caSDavid Howells 105674e95caSDavid Howells /* cc_reg constants */ 106674e95caSDavid Howells #define CC_REG_NORMALIZED C_00000001 107674e95caSDavid Howells #define CC_REG_BORROW C_00000002 108674e95caSDavid Howells #define CC_REG_MINUS C_00000004 109674e95caSDavid Howells #define CC_REG_ZERO C_00000008 110674e95caSDavid Howells #define CC_REG_SATURATE C_00000010 111674e95caSDavid Howells #define CC_REG_NONZERO C_00000100 112674e95caSDavid Howells 113674e95caSDavid Howells /* FX buses */ 114*a869057cSOswald Buddenhagen // These are arbitrary mappings; our DSP code simply expects 115*a869057cSOswald Buddenhagen // the config files to route the channels this way. 116*a869057cSOswald Buddenhagen // The numbers are documented in {audigy,sb-live}-mixer.rst. 117674e95caSDavid Howells #define FXBUS_PCM_LEFT 0x00 118674e95caSDavid Howells #define FXBUS_PCM_RIGHT 0x01 119674e95caSDavid Howells #define FXBUS_PCM_LEFT_REAR 0x02 120674e95caSDavid Howells #define FXBUS_PCM_RIGHT_REAR 0x03 121674e95caSDavid Howells #define FXBUS_MIDI_LEFT 0x04 122674e95caSDavid Howells #define FXBUS_MIDI_RIGHT 0x05 123674e95caSDavid Howells #define FXBUS_PCM_CENTER 0x06 124674e95caSDavid Howells #define FXBUS_PCM_LFE 0x07 125674e95caSDavid Howells #define FXBUS_PCM_LEFT_FRONT 0x08 126674e95caSDavid Howells #define FXBUS_PCM_RIGHT_FRONT 0x09 127674e95caSDavid Howells #define FXBUS_MIDI_REVERB 0x0c 128674e95caSDavid Howells #define FXBUS_MIDI_CHORUS 0x0d 129674e95caSDavid Howells #define FXBUS_PCM_LEFT_SIDE 0x0e 130674e95caSDavid Howells #define FXBUS_PCM_RIGHT_SIDE 0x0f 131674e95caSDavid Howells #define FXBUS_PT_LEFT 0x14 132674e95caSDavid Howells #define FXBUS_PT_RIGHT 0x15 133674e95caSDavid Howells 134674e95caSDavid Howells /* Inputs */ 135674e95caSDavid Howells #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ 136674e95caSDavid Howells #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ 137674e95caSDavid Howells #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */ 138674e95caSDavid Howells #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */ 139674e95caSDavid Howells #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */ 140674e95caSDavid Howells #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */ 141674e95caSDavid Howells #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */ 142674e95caSDavid Howells #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */ 143674e95caSDavid Howells #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */ 144674e95caSDavid Howells #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */ 145674e95caSDavid Howells #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */ 146674e95caSDavid Howells #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */ 147674e95caSDavid Howells #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */ 148674e95caSDavid Howells #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */ 149674e95caSDavid Howells 150674e95caSDavid Howells /* Outputs */ 151674e95caSDavid Howells #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */ 152674e95caSDavid Howells #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */ 153674e95caSDavid Howells #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */ 154674e95caSDavid Howells #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */ 155674e95caSDavid Howells #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */ 156674e95caSDavid Howells #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */ 157674e95caSDavid Howells #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */ 158674e95caSDavid Howells #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */ 159674e95caSDavid Howells #define EXTOUT_REAR_L 0x08 /* Rear channel - left */ 160674e95caSDavid Howells #define EXTOUT_REAR_R 0x09 /* Rear channel - right */ 161674e95caSDavid Howells #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */ 162674e95caSDavid Howells #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */ 163674e95caSDavid Howells #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */ 164674e95caSDavid Howells #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */ 165674e95caSDavid Howells #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */ 166674e95caSDavid Howells #define EXTOUT_ACENTER 0x11 /* Analog Center */ 167674e95caSDavid Howells #define EXTOUT_ALFE 0x12 /* Analog LFE */ 168674e95caSDavid Howells 169674e95caSDavid Howells /* Audigy Inputs */ 170674e95caSDavid Howells #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ 171674e95caSDavid Howells #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ 172674e95caSDavid Howells #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */ 173674e95caSDavid Howells #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */ 174674e95caSDavid Howells #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */ 175674e95caSDavid Howells #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */ 176674e95caSDavid Howells #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */ 177674e95caSDavid Howells #define A_EXTIN_LINE2_R 0x09 /* right */ 178674e95caSDavid Howells #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */ 179674e95caSDavid Howells #define A_EXTIN_ADC_R 0x0b /* right */ 180674e95caSDavid Howells #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */ 181674e95caSDavid Howells #define A_EXTIN_AUX2_R 0x0d /* - right */ 182674e95caSDavid Howells 183674e95caSDavid Howells /* Audigiy Outputs */ 184674e95caSDavid Howells #define A_EXTOUT_FRONT_L 0x00 /* digital front left */ 185674e95caSDavid Howells #define A_EXTOUT_FRONT_R 0x01 /* right */ 186674e95caSDavid Howells #define A_EXTOUT_CENTER 0x02 /* digital front center */ 187674e95caSDavid Howells #define A_EXTOUT_LFE 0x03 /* digital front lfe */ 188674e95caSDavid Howells #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */ 189674e95caSDavid Howells #define A_EXTOUT_HEADPHONE_R 0x05 /* right */ 190674e95caSDavid Howells #define A_EXTOUT_REAR_L 0x06 /* digital rear left */ 191674e95caSDavid Howells #define A_EXTOUT_REAR_R 0x07 /* right */ 192674e95caSDavid Howells #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */ 193674e95caSDavid Howells #define A_EXTOUT_AFRONT_R 0x09 /* right */ 194674e95caSDavid Howells #define A_EXTOUT_ACENTER 0x0a /* analog center */ 195674e95caSDavid Howells #define A_EXTOUT_ALFE 0x0b /* analog LFE */ 196674e95caSDavid Howells #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */ 197674e95caSDavid Howells #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */ 198674e95caSDavid Howells #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */ 199674e95caSDavid Howells #define A_EXTOUT_AREAR_R 0x0f /* right */ 200674e95caSDavid Howells #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */ 201674e95caSDavid Howells #define A_EXTOUT_AC97_R 0x11 /* right */ 202674e95caSDavid Howells #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */ 203674e95caSDavid Howells #define A_EXTOUT_ADC_CAP_R 0x17 /* right */ 204674e95caSDavid Howells #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */ 205674e95caSDavid Howells 206674e95caSDavid Howells /* Audigy constants */ 207674e95caSDavid Howells #define A_C_00000000 0xc0 208674e95caSDavid Howells #define A_C_00000001 0xc1 209674e95caSDavid Howells #define A_C_00000002 0xc2 210674e95caSDavid Howells #define A_C_00000003 0xc3 211674e95caSDavid Howells #define A_C_00000004 0xc4 212674e95caSDavid Howells #define A_C_00000008 0xc5 213674e95caSDavid Howells #define A_C_00000010 0xc6 214674e95caSDavid Howells #define A_C_00000020 0xc7 215674e95caSDavid Howells #define A_C_00000100 0xc8 216674e95caSDavid Howells #define A_C_00010000 0xc9 217674e95caSDavid Howells #define A_C_00000800 0xca 218674e95caSDavid Howells #define A_C_10000000 0xcb 219674e95caSDavid Howells #define A_C_20000000 0xcc 220674e95caSDavid Howells #define A_C_40000000 0xcd 221674e95caSDavid Howells #define A_C_80000000 0xce 222674e95caSDavid Howells #define A_C_7fffffff 0xcf 223674e95caSDavid Howells #define A_C_ffffffff 0xd0 224674e95caSDavid Howells #define A_C_fffffffe 0xd1 225674e95caSDavid Howells #define A_C_c0000000 0xd2 226674e95caSDavid Howells #define A_C_4f1bbcdc 0xd3 227674e95caSDavid Howells #define A_C_5a7ef9db 0xd4 228674e95caSDavid Howells #define A_C_00100000 0xd5 229674e95caSDavid Howells #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */ 230674e95caSDavid Howells #define A_GPR_COND 0xd7 /* CCR, condition register */ 231674e95caSDavid Howells #define A_GPR_NOISE0 0xd8 /* noise source */ 232674e95caSDavid Howells #define A_GPR_NOISE1 0xd9 /* noise source */ 233674e95caSDavid Howells #define A_GPR_IRQ 0xda /* IRQ register */ 234674e95caSDavid Howells #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */ 235674e95caSDavid Howells #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */ 236674e95caSDavid Howells 237674e95caSDavid Howells /* definitions for debug register */ 238674e95caSDavid Howells #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */ 239674e95caSDavid Howells #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */ 240674e95caSDavid Howells #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */ 241674e95caSDavid Howells #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */ 242674e95caSDavid Howells #define EMU10K1_DBG_STEP 0x00004000 /* start single step */ 243674e95caSDavid Howells #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */ 244674e95caSDavid Howells #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */ 245674e95caSDavid Howells 246674e95caSDavid Howells /* tank memory address line */ 247674e95caSDavid Howells #ifndef __KERNEL__ 248674e95caSDavid Howells #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */ 249674e95caSDavid Howells #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */ 250674e95caSDavid Howells #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */ 251674e95caSDavid Howells #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */ 252674e95caSDavid Howells #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */ 253674e95caSDavid Howells #endif 254674e95caSDavid Howells 255674e95caSDavid Howells struct snd_emu10k1_fx8010_info { 256674e95caSDavid Howells unsigned int internal_tram_size; /* in samples */ 257674e95caSDavid Howells unsigned int external_tram_size; /* in samples */ 258674e95caSDavid Howells char fxbus_names[16][32]; /* names of FXBUSes */ 259674e95caSDavid Howells char extin_names[16][32]; /* names of external inputs */ 260674e95caSDavid Howells char extout_names[32][32]; /* names of external outputs */ 261674e95caSDavid Howells unsigned int gpr_controls; /* count of GPR controls */ 262674e95caSDavid Howells }; 263674e95caSDavid Howells 264674e95caSDavid Howells #define EMU10K1_GPR_TRANSLATION_NONE 0 265674e95caSDavid Howells #define EMU10K1_GPR_TRANSLATION_TABLE100 1 266674e95caSDavid Howells #define EMU10K1_GPR_TRANSLATION_BASS 2 267674e95caSDavid Howells #define EMU10K1_GPR_TRANSLATION_TREBLE 3 268674e95caSDavid Howells #define EMU10K1_GPR_TRANSLATION_ONOFF 4 269674e95caSDavid Howells 2702e468867STakashi Iwai enum emu10k1_ctl_elem_iface { 2712e468867STakashi Iwai EMU10K1_CTL_ELEM_IFACE_MIXER = 2, /* virtual mixer device */ 2722e468867STakashi Iwai EMU10K1_CTL_ELEM_IFACE_PCM = 3, /* PCM device */ 2732e468867STakashi Iwai }; 2742e468867STakashi Iwai 2752e468867STakashi Iwai struct emu10k1_ctl_elem_id { 2762e468867STakashi Iwai unsigned int pad; /* don't use */ 2772e468867STakashi Iwai int iface; /* interface identifier */ 2782e468867STakashi Iwai unsigned int device; /* device/client number */ 2792e468867STakashi Iwai unsigned int subdevice; /* subdevice (substream) number */ 2802e468867STakashi Iwai unsigned char name[44]; /* ASCII name of item */ 2812e468867STakashi Iwai unsigned int index; /* index of item */ 2822e468867STakashi Iwai }; 2832e468867STakashi Iwai 284674e95caSDavid Howells struct snd_emu10k1_fx8010_control_gpr { 2852e468867STakashi Iwai struct emu10k1_ctl_elem_id id; /* full control ID definition */ 286674e95caSDavid Howells unsigned int vcount; /* visible count */ 287674e95caSDavid Howells unsigned int count; /* count of GPR (1..16) */ 288674e95caSDavid Howells unsigned short gpr[32]; /* GPR number(s) */ 289674e95caSDavid Howells unsigned int value[32]; /* initial values */ 290674e95caSDavid Howells unsigned int min; /* minimum range */ 291674e95caSDavid Howells unsigned int max; /* maximum range */ 292674e95caSDavid Howells unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ 293674e95caSDavid Howells const unsigned int *tlv; 294674e95caSDavid Howells }; 295674e95caSDavid Howells 296674e95caSDavid Howells /* old ABI without TLV support */ 297674e95caSDavid Howells struct snd_emu10k1_fx8010_control_old_gpr { 2982e468867STakashi Iwai struct emu10k1_ctl_elem_id id; 299674e95caSDavid Howells unsigned int vcount; 300674e95caSDavid Howells unsigned int count; 301674e95caSDavid Howells unsigned short gpr[32]; 302674e95caSDavid Howells unsigned int value[32]; 303674e95caSDavid Howells unsigned int min; 304674e95caSDavid Howells unsigned int max; 305674e95caSDavid Howells unsigned int translation; 306674e95caSDavid Howells }; 307674e95caSDavid Howells 308674e95caSDavid Howells struct snd_emu10k1_fx8010_code { 309674e95caSDavid Howells char name[128]; 310674e95caSDavid Howells 311a82d24f8SMikko Rapeli __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */ 3122e468867STakashi Iwai __u32 *gpr_map; /* initializers */ 313674e95caSDavid Howells 314674e95caSDavid Howells unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */ 3152e468867STakashi Iwai struct snd_emu10k1_fx8010_control_gpr *gpr_add_controls; /* GPR controls to add/replace */ 316674e95caSDavid Howells 317674e95caSDavid Howells unsigned int gpr_del_control_count; /* count of GPR controls to remove */ 3182e468867STakashi Iwai struct emu10k1_ctl_elem_id *gpr_del_controls; /* IDs of GPR controls to remove */ 319674e95caSDavid Howells 320674e95caSDavid Howells unsigned int gpr_list_control_count; /* count of GPR controls to list */ 321674e95caSDavid Howells unsigned int gpr_list_control_total; /* total count of GPR controls */ 3222e468867STakashi Iwai struct snd_emu10k1_fx8010_control_gpr *gpr_list_controls; /* listed GPR controls */ 323674e95caSDavid Howells 324a82d24f8SMikko Rapeli __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */ 3252e468867STakashi Iwai __u32 *tram_data_map; /* data initializers */ 3262e468867STakashi Iwai __u32 *tram_addr_map; /* map initializers */ 327674e95caSDavid Howells 328a82d24f8SMikko Rapeli __EMU10K1_DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */ 3292e468867STakashi Iwai __u32 *code; /* one instruction - 64 bits */ 330674e95caSDavid Howells }; 331674e95caSDavid Howells 332674e95caSDavid Howells struct snd_emu10k1_fx8010_tram { 333674e95caSDavid Howells unsigned int address; /* 31.bit == 1 -> external TRAM */ 334674e95caSDavid Howells unsigned int size; /* size in samples (4 bytes) */ 335674e95caSDavid Howells unsigned int *samples; /* pointer to samples (20-bit) */ 336674e95caSDavid Howells /* NULL->clear memory */ 337674e95caSDavid Howells }; 338674e95caSDavid Howells 339674e95caSDavid Howells struct snd_emu10k1_fx8010_pcm_rec { 340674e95caSDavid Howells unsigned int substream; /* substream number */ 341674e95caSDavid Howells unsigned int res1; /* reserved */ 342674e95caSDavid Howells unsigned int channels; /* 16-bit channels count, zero = remove this substream */ 343674e95caSDavid Howells unsigned int tram_start; /* ring buffer position in TRAM (in samples) */ 344674e95caSDavid Howells unsigned int buffer_size; /* count of buffered samples */ 345674e95caSDavid Howells unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */ 346674e95caSDavid Howells unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ 347674e95caSDavid Howells unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ 348674e95caSDavid Howells unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ 349674e95caSDavid Howells unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ 350674e95caSDavid Howells unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ 351674e95caSDavid Howells unsigned char pad; /* reserved */ 352674e95caSDavid Howells unsigned char etram[32]; /* external TRAM address & data (one per channel) */ 353674e95caSDavid Howells unsigned int res2; /* reserved */ 354674e95caSDavid Howells }; 355674e95caSDavid Howells 356674e95caSDavid Howells #define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) 357674e95caSDavid Howells 358674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info) 359674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code) 360674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code) 361674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int) 362674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram) 363674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram) 364674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec) 365674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec) 366674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int) 367674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80) 368674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81) 369674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82) 370674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int) 371674e95caSDavid Howells #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int) 372674e95caSDavid Howells 373674e95caSDavid Howells #endif /* _UAPI__SOUND_EMU10K1_H */ 374