1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */ 2 /* 3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef MLX5_ABI_USER_H 35 #define MLX5_ABI_USER_H 36 37 #include <linux/types.h> 38 #include <linux/if_ether.h> /* For ETH_ALEN. */ 39 #include <rdma/ib_user_ioctl_verbs.h> 40 41 enum { 42 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 43 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 44 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, 45 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, 46 MLX5_QP_FLAG_TYPE_DCT = 1 << 4, 47 MLX5_QP_FLAG_TYPE_DCI = 1 << 5, 48 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6, 49 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7, 50 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8, 51 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9, 52 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10, 53 }; 54 55 enum { 56 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 57 }; 58 59 enum { 60 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 61 }; 62 63 /* Increment this value if any changes that break userspace ABI 64 * compatibility are made. 65 */ 66 #define MLX5_IB_UVERBS_ABI_VERSION 1 67 68 /* Make sure that all structs defined in this file remain laid out so 69 * that they pack the same way on 32-bit and 64-bit architectures (to 70 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 71 * In particular do not use pointer types -- pass pointers in __u64 72 * instead. 73 */ 74 75 struct mlx5_ib_alloc_ucontext_req { 76 __u32 total_num_bfregs; 77 __u32 num_low_latency_bfregs; 78 }; 79 80 enum mlx5_lib_caps { 81 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 82 MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1, 83 }; 84 85 enum mlx5_ib_alloc_uctx_v2_flags { 86 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, 87 }; 88 struct mlx5_ib_alloc_ucontext_req_v2 { 89 __u32 total_num_bfregs; 90 __u32 num_low_latency_bfregs; 91 __u32 flags; 92 __u32 comp_mask; 93 __u8 max_cqe_version; 94 __u8 reserved0; 95 __u16 reserved1; 96 __u32 reserved2; 97 __aligned_u64 lib_caps; 98 }; 99 100 enum mlx5_ib_alloc_ucontext_resp_mask { 101 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 102 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1, 103 }; 104 105 enum mlx5_user_cmds_supp_uhw { 106 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 107 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 108 }; 109 110 /* The eth_min_inline response value is set to off-by-one vs the FW 111 * returned value to allow user-space to deal with older kernels. 112 */ 113 enum mlx5_user_inline_mode { 114 MLX5_USER_INLINE_MODE_NA, 115 MLX5_USER_INLINE_MODE_NONE, 116 MLX5_USER_INLINE_MODE_L2, 117 MLX5_USER_INLINE_MODE_IP, 118 MLX5_USER_INLINE_MODE_TCP_UDP, 119 }; 120 121 enum { 122 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0, 123 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1, 124 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2, 125 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3, 126 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4, 127 }; 128 129 struct mlx5_ib_alloc_ucontext_resp { 130 __u32 qp_tab_size; 131 __u32 bf_reg_size; 132 __u32 tot_bfregs; 133 __u32 cache_line_size; 134 __u16 max_sq_desc_sz; 135 __u16 max_rq_desc_sz; 136 __u32 max_send_wqebb; 137 __u32 max_recv_wr; 138 __u32 max_srq_recv_wr; 139 __u16 num_ports; 140 __u16 flow_action_flags; 141 __u32 comp_mask; 142 __u32 response_length; 143 __u8 cqe_version; 144 __u8 cmds_supp_uhw; 145 __u8 eth_min_inline; 146 __u8 clock_info_versions; 147 __aligned_u64 hca_core_clock_offset; 148 __u32 log_uar_size; 149 __u32 num_uars_per_page; 150 __u32 num_dyn_bfregs; 151 __u32 dump_fill_mkey; 152 }; 153 154 struct mlx5_ib_alloc_pd_resp { 155 __u32 pdn; 156 }; 157 158 struct mlx5_ib_tso_caps { 159 __u32 max_tso; /* Maximum tso payload size in bytes */ 160 161 /* Corresponding bit will be set if qp type from 162 * 'enum ib_qp_type' is supported, e.g. 163 * supported_qpts |= 1 << IB_QPT_UD 164 */ 165 __u32 supported_qpts; 166 }; 167 168 struct mlx5_ib_rss_caps { 169 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 170 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 171 __u8 reserved[7]; 172 }; 173 174 enum mlx5_ib_cqe_comp_res_format { 175 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 176 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 177 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2, 178 }; 179 180 struct mlx5_ib_cqe_comp_caps { 181 __u32 max_num; 182 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */ 183 }; 184 185 enum mlx5_ib_packet_pacing_cap_flags { 186 MLX5_IB_PP_SUPPORT_BURST = 1 << 0, 187 }; 188 189 struct mlx5_packet_pacing_caps { 190 __u32 qp_rate_limit_min; 191 __u32 qp_rate_limit_max; /* In kpbs */ 192 193 /* Corresponding bit will be set if qp type from 194 * 'enum ib_qp_type' is supported, e.g. 195 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 196 */ 197 __u32 supported_qpts; 198 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */ 199 __u8 reserved[3]; 200 }; 201 202 enum mlx5_ib_mpw_caps { 203 MPW_RESERVED = 1 << 0, 204 MLX5_IB_ALLOW_MPW = 1 << 1, 205 MLX5_IB_SUPPORT_EMPW = 1 << 2, 206 }; 207 208 enum mlx5_ib_sw_parsing_offloads { 209 MLX5_IB_SW_PARSING = 1 << 0, 210 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 211 MLX5_IB_SW_PARSING_LSO = 1 << 2, 212 }; 213 214 struct mlx5_ib_sw_parsing_caps { 215 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */ 216 217 /* Corresponding bit will be set if qp type from 218 * 'enum ib_qp_type' is supported, e.g. 219 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 220 */ 221 __u32 supported_qpts; 222 }; 223 224 struct mlx5_ib_striding_rq_caps { 225 __u32 min_single_stride_log_num_of_bytes; 226 __u32 max_single_stride_log_num_of_bytes; 227 __u32 min_single_wqe_log_num_of_strides; 228 __u32 max_single_wqe_log_num_of_strides; 229 230 /* Corresponding bit will be set if qp type from 231 * 'enum ib_qp_type' is supported, e.g. 232 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 233 */ 234 __u32 supported_qpts; 235 __u32 reserved; 236 }; 237 238 enum mlx5_ib_query_dev_resp_flags { 239 /* Support 128B CQE compression */ 240 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, 241 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, 242 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2, 243 MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3, 244 }; 245 246 enum mlx5_ib_tunnel_offloads { 247 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, 248 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, 249 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2, 250 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3, 251 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4, 252 }; 253 254 struct mlx5_ib_query_device_resp { 255 __u32 comp_mask; 256 __u32 response_length; 257 struct mlx5_ib_tso_caps tso_caps; 258 struct mlx5_ib_rss_caps rss_caps; 259 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 260 struct mlx5_packet_pacing_caps packet_pacing_caps; 261 __u32 mlx5_ib_support_multi_pkt_send_wqes; 262 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */ 263 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 264 struct mlx5_ib_striding_rq_caps striding_rq_caps; 265 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */ 266 __u32 reserved; 267 }; 268 269 enum mlx5_ib_create_cq_flags { 270 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 271 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1, 272 }; 273 274 struct mlx5_ib_create_cq { 275 __aligned_u64 buf_addr; 276 __aligned_u64 db_addr; 277 __u32 cqe_size; 278 __u8 cqe_comp_en; 279 __u8 cqe_comp_res_format; 280 __u16 flags; 281 __u16 uar_page_index; 282 __u16 reserved0; 283 __u32 reserved1; 284 }; 285 286 struct mlx5_ib_create_cq_resp { 287 __u32 cqn; 288 __u32 reserved; 289 }; 290 291 struct mlx5_ib_resize_cq { 292 __aligned_u64 buf_addr; 293 __u16 cqe_size; 294 __u16 reserved0; 295 __u32 reserved1; 296 }; 297 298 struct mlx5_ib_create_srq { 299 __aligned_u64 buf_addr; 300 __aligned_u64 db_addr; 301 __u32 flags; 302 __u32 reserved0; /* explicit padding (optional on i386) */ 303 __u32 uidx; 304 __u32 reserved1; 305 }; 306 307 struct mlx5_ib_create_srq_resp { 308 __u32 srqn; 309 __u32 reserved; 310 }; 311 312 struct mlx5_ib_create_qp { 313 __aligned_u64 buf_addr; 314 __aligned_u64 db_addr; 315 __u32 sq_wqe_count; 316 __u32 rq_wqe_count; 317 __u32 rq_wqe_shift; 318 __u32 flags; 319 __u32 uidx; 320 __u32 bfreg_index; 321 union { 322 __aligned_u64 sq_buf_addr; 323 __aligned_u64 access_key; 324 }; 325 }; 326 327 /* RX Hash function flags */ 328 enum mlx5_rx_hash_function_flags { 329 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 330 }; 331 332 /* 333 * RX Hash flags, these flags allows to set which incoming packet's field should 334 * participates in RX Hash. Each flag represent certain packet's field, 335 * when the flag is set the field that is represented by the flag will 336 * participate in RX Hash calculation. 337 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 338 * and *TCP and *UDP flags can't be enabled together on the same QP. 339 */ 340 enum mlx5_rx_hash_fields { 341 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 342 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 343 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 344 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 345 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 346 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 347 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 348 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, 349 MLX5_RX_HASH_IPSEC_SPI = 1 << 8, 350 /* Save bits for future fields */ 351 MLX5_RX_HASH_INNER = (1UL << 31), 352 }; 353 354 struct mlx5_ib_create_qp_rss { 355 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 356 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 357 __u8 rx_key_len; /* valid only for Toeplitz */ 358 __u8 reserved[6]; 359 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 360 __u32 comp_mask; 361 __u32 flags; 362 }; 363 364 enum mlx5_ib_create_qp_resp_mask { 365 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0, 366 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1, 367 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2, 368 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3, 369 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR = 1UL << 4, 370 }; 371 372 struct mlx5_ib_create_qp_resp { 373 __u32 bfreg_index; 374 __u32 reserved; 375 __u32 comp_mask; 376 __u32 tirn; 377 __u32 tisn; 378 __u32 rqn; 379 __u32 sqn; 380 __u32 reserved1; 381 __u64 tir_icm_addr; 382 }; 383 384 struct mlx5_ib_alloc_mw { 385 __u32 comp_mask; 386 __u8 num_klms; 387 __u8 reserved1; 388 __u16 reserved2; 389 }; 390 391 enum mlx5_ib_create_wq_mask { 392 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), 393 }; 394 395 struct mlx5_ib_create_wq { 396 __aligned_u64 buf_addr; 397 __aligned_u64 db_addr; 398 __u32 rq_wqe_count; 399 __u32 rq_wqe_shift; 400 __u32 user_index; 401 __u32 flags; 402 __u32 comp_mask; 403 __u32 single_stride_log_num_of_bytes; 404 __u32 single_wqe_log_num_of_strides; 405 __u32 two_byte_shift_en; 406 }; 407 408 struct mlx5_ib_create_ah_resp { 409 __u32 response_length; 410 __u8 dmac[ETH_ALEN]; 411 __u8 reserved[6]; 412 }; 413 414 struct mlx5_ib_burst_info { 415 __u32 max_burst_sz; 416 __u16 typical_pkt_sz; 417 __u16 reserved; 418 }; 419 420 struct mlx5_ib_modify_qp { 421 __u32 comp_mask; 422 struct mlx5_ib_burst_info burst_info; 423 __u32 reserved; 424 }; 425 426 struct mlx5_ib_modify_qp_resp { 427 __u32 response_length; 428 __u32 dctn; 429 }; 430 431 struct mlx5_ib_create_wq_resp { 432 __u32 response_length; 433 __u32 reserved; 434 }; 435 436 struct mlx5_ib_create_rwq_ind_tbl_resp { 437 __u32 response_length; 438 __u32 reserved; 439 }; 440 441 struct mlx5_ib_modify_wq { 442 __u32 comp_mask; 443 __u32 reserved; 444 }; 445 446 struct mlx5_ib_clock_info { 447 __u32 sign; 448 __u32 resv; 449 __aligned_u64 nsec; 450 __aligned_u64 cycles; 451 __aligned_u64 frac; 452 __u32 mult; 453 __u32 shift; 454 __aligned_u64 mask; 455 __aligned_u64 overflow_period; 456 }; 457 458 enum mlx5_ib_mmap_cmd { 459 MLX5_IB_MMAP_REGULAR_PAGE = 0, 460 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 461 MLX5_IB_MMAP_WC_PAGE = 2, 462 MLX5_IB_MMAP_NC_PAGE = 3, 463 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 464 MLX5_IB_MMAP_CORE_CLOCK = 5, 465 MLX5_IB_MMAP_ALLOC_WC = 6, 466 MLX5_IB_MMAP_CLOCK_INFO = 7, 467 MLX5_IB_MMAP_DEVICE_MEM = 8, 468 }; 469 470 enum { 471 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1, 472 }; 473 474 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */ 475 enum { 476 MLX5_IB_CLOCK_INFO_V1 = 0, 477 }; 478 479 struct mlx5_ib_flow_counters_desc { 480 __u32 description; 481 __u32 index; 482 }; 483 484 struct mlx5_ib_flow_counters_data { 485 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data); 486 __u32 ncounters; 487 __u32 reserved; 488 }; 489 490 struct mlx5_ib_create_flow { 491 __u32 ncounters_data; 492 __u32 reserved; 493 /* 494 * Following are counters data based on ncounters_data, each 495 * entry in the data[] should match a corresponding counter object 496 * that was pointed by a counters spec upon the flow creation 497 */ 498 struct mlx5_ib_flow_counters_data data[]; 499 }; 500 501 #endif /* MLX5_ABI_USER_H */ 502