1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */ 2 /* 3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef MLX5_ABI_USER_H 35 #define MLX5_ABI_USER_H 36 37 #include <linux/types.h> 38 #include <linux/if_ether.h> /* For ETH_ALEN. */ 39 #include <rdma/ib_user_ioctl_verbs.h> 40 41 enum { 42 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 43 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 44 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, 45 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, 46 MLX5_QP_FLAG_TYPE_DCT = 1 << 4, 47 MLX5_QP_FLAG_TYPE_DCI = 1 << 5, 48 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6, 49 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7, 50 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8, 51 }; 52 53 enum { 54 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 55 }; 56 57 enum { 58 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 59 }; 60 61 /* Increment this value if any changes that break userspace ABI 62 * compatibility are made. 63 */ 64 #define MLX5_IB_UVERBS_ABI_VERSION 1 65 66 /* Make sure that all structs defined in this file remain laid out so 67 * that they pack the same way on 32-bit and 64-bit architectures (to 68 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 69 * In particular do not use pointer types -- pass pointers in __u64 70 * instead. 71 */ 72 73 struct mlx5_ib_alloc_ucontext_req { 74 __u32 total_num_bfregs; 75 __u32 num_low_latency_bfregs; 76 }; 77 78 enum mlx5_lib_caps { 79 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 80 }; 81 82 enum mlx5_ib_alloc_uctx_v2_flags { 83 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, 84 }; 85 struct mlx5_ib_alloc_ucontext_req_v2 { 86 __u32 total_num_bfregs; 87 __u32 num_low_latency_bfregs; 88 __u32 flags; 89 __u32 comp_mask; 90 __u8 max_cqe_version; 91 __u8 reserved0; 92 __u16 reserved1; 93 __u32 reserved2; 94 __aligned_u64 lib_caps; 95 }; 96 97 enum mlx5_ib_alloc_ucontext_resp_mask { 98 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 99 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1, 100 }; 101 102 enum mlx5_user_cmds_supp_uhw { 103 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 104 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 105 }; 106 107 /* The eth_min_inline response value is set to off-by-one vs the FW 108 * returned value to allow user-space to deal with older kernels. 109 */ 110 enum mlx5_user_inline_mode { 111 MLX5_USER_INLINE_MODE_NA, 112 MLX5_USER_INLINE_MODE_NONE, 113 MLX5_USER_INLINE_MODE_L2, 114 MLX5_USER_INLINE_MODE_IP, 115 MLX5_USER_INLINE_MODE_TCP_UDP, 116 }; 117 118 enum { 119 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0, 120 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1, 121 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2, 122 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3, 123 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4, 124 }; 125 126 struct mlx5_ib_alloc_ucontext_resp { 127 __u32 qp_tab_size; 128 __u32 bf_reg_size; 129 __u32 tot_bfregs; 130 __u32 cache_line_size; 131 __u16 max_sq_desc_sz; 132 __u16 max_rq_desc_sz; 133 __u32 max_send_wqebb; 134 __u32 max_recv_wr; 135 __u32 max_srq_recv_wr; 136 __u16 num_ports; 137 __u16 flow_action_flags; 138 __u32 comp_mask; 139 __u32 response_length; 140 __u8 cqe_version; 141 __u8 cmds_supp_uhw; 142 __u8 eth_min_inline; 143 __u8 clock_info_versions; 144 __aligned_u64 hca_core_clock_offset; 145 __u32 log_uar_size; 146 __u32 num_uars_per_page; 147 __u32 num_dyn_bfregs; 148 __u32 dump_fill_mkey; 149 }; 150 151 struct mlx5_ib_alloc_pd_resp { 152 __u32 pdn; 153 }; 154 155 struct mlx5_ib_tso_caps { 156 __u32 max_tso; /* Maximum tso payload size in bytes */ 157 158 /* Corresponding bit will be set if qp type from 159 * 'enum ib_qp_type' is supported, e.g. 160 * supported_qpts |= 1 << IB_QPT_UD 161 */ 162 __u32 supported_qpts; 163 }; 164 165 struct mlx5_ib_rss_caps { 166 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 167 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 168 __u8 reserved[7]; 169 }; 170 171 enum mlx5_ib_cqe_comp_res_format { 172 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 173 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 174 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2, 175 }; 176 177 struct mlx5_ib_cqe_comp_caps { 178 __u32 max_num; 179 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */ 180 }; 181 182 enum mlx5_ib_packet_pacing_cap_flags { 183 MLX5_IB_PP_SUPPORT_BURST = 1 << 0, 184 }; 185 186 struct mlx5_packet_pacing_caps { 187 __u32 qp_rate_limit_min; 188 __u32 qp_rate_limit_max; /* In kpbs */ 189 190 /* Corresponding bit will be set if qp type from 191 * 'enum ib_qp_type' is supported, e.g. 192 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 193 */ 194 __u32 supported_qpts; 195 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */ 196 __u8 reserved[3]; 197 }; 198 199 enum mlx5_ib_mpw_caps { 200 MPW_RESERVED = 1 << 0, 201 MLX5_IB_ALLOW_MPW = 1 << 1, 202 MLX5_IB_SUPPORT_EMPW = 1 << 2, 203 }; 204 205 enum mlx5_ib_sw_parsing_offloads { 206 MLX5_IB_SW_PARSING = 1 << 0, 207 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 208 MLX5_IB_SW_PARSING_LSO = 1 << 2, 209 }; 210 211 struct mlx5_ib_sw_parsing_caps { 212 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */ 213 214 /* Corresponding bit will be set if qp type from 215 * 'enum ib_qp_type' is supported, e.g. 216 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 217 */ 218 __u32 supported_qpts; 219 }; 220 221 struct mlx5_ib_striding_rq_caps { 222 __u32 min_single_stride_log_num_of_bytes; 223 __u32 max_single_stride_log_num_of_bytes; 224 __u32 min_single_wqe_log_num_of_strides; 225 __u32 max_single_wqe_log_num_of_strides; 226 227 /* Corresponding bit will be set if qp type from 228 * 'enum ib_qp_type' is supported, e.g. 229 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 230 */ 231 __u32 supported_qpts; 232 __u32 reserved; 233 }; 234 235 enum mlx5_ib_query_dev_resp_flags { 236 /* Support 128B CQE compression */ 237 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, 238 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, 239 }; 240 241 enum mlx5_ib_tunnel_offloads { 242 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, 243 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, 244 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2, 245 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3, 246 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4, 247 }; 248 249 struct mlx5_ib_query_device_resp { 250 __u32 comp_mask; 251 __u32 response_length; 252 struct mlx5_ib_tso_caps tso_caps; 253 struct mlx5_ib_rss_caps rss_caps; 254 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 255 struct mlx5_packet_pacing_caps packet_pacing_caps; 256 __u32 mlx5_ib_support_multi_pkt_send_wqes; 257 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */ 258 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 259 struct mlx5_ib_striding_rq_caps striding_rq_caps; 260 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */ 261 __u32 reserved; 262 }; 263 264 enum mlx5_ib_create_cq_flags { 265 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 266 }; 267 268 struct mlx5_ib_create_cq { 269 __aligned_u64 buf_addr; 270 __aligned_u64 db_addr; 271 __u32 cqe_size; 272 __u8 cqe_comp_en; 273 __u8 cqe_comp_res_format; 274 __u16 flags; 275 }; 276 277 struct mlx5_ib_create_cq_resp { 278 __u32 cqn; 279 __u32 reserved; 280 }; 281 282 struct mlx5_ib_resize_cq { 283 __aligned_u64 buf_addr; 284 __u16 cqe_size; 285 __u16 reserved0; 286 __u32 reserved1; 287 }; 288 289 struct mlx5_ib_create_srq { 290 __aligned_u64 buf_addr; 291 __aligned_u64 db_addr; 292 __u32 flags; 293 __u32 reserved0; /* explicit padding (optional on i386) */ 294 __u32 uidx; 295 __u32 reserved1; 296 }; 297 298 struct mlx5_ib_create_srq_resp { 299 __u32 srqn; 300 __u32 reserved; 301 }; 302 303 struct mlx5_ib_create_qp { 304 __aligned_u64 buf_addr; 305 __aligned_u64 db_addr; 306 __u32 sq_wqe_count; 307 __u32 rq_wqe_count; 308 __u32 rq_wqe_shift; 309 __u32 flags; 310 __u32 uidx; 311 __u32 bfreg_index; 312 union { 313 __aligned_u64 sq_buf_addr; 314 __aligned_u64 access_key; 315 }; 316 }; 317 318 /* RX Hash function flags */ 319 enum mlx5_rx_hash_function_flags { 320 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 321 }; 322 323 /* 324 * RX Hash flags, these flags allows to set which incoming packet's field should 325 * participates in RX Hash. Each flag represent certain packet's field, 326 * when the flag is set the field that is represented by the flag will 327 * participate in RX Hash calculation. 328 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 329 * and *TCP and *UDP flags can't be enabled together on the same QP. 330 */ 331 enum mlx5_rx_hash_fields { 332 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 333 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 334 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 335 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 336 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 337 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 338 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 339 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, 340 MLX5_RX_HASH_IPSEC_SPI = 1 << 8, 341 /* Save bits for future fields */ 342 MLX5_RX_HASH_INNER = (1UL << 31), 343 }; 344 345 struct mlx5_ib_create_qp_rss { 346 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 347 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 348 __u8 rx_key_len; /* valid only for Toeplitz */ 349 __u8 reserved[6]; 350 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 351 __u32 comp_mask; 352 __u32 flags; 353 }; 354 355 enum mlx5_ib_create_qp_resp_mask { 356 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0, 357 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1, 358 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2, 359 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3, 360 }; 361 362 struct mlx5_ib_create_qp_resp { 363 __u32 bfreg_index; 364 __u32 reserved; 365 __u32 comp_mask; 366 __u32 tirn; 367 __u32 tisn; 368 __u32 rqn; 369 __u32 sqn; 370 __u32 reserved1; 371 }; 372 373 struct mlx5_ib_alloc_mw { 374 __u32 comp_mask; 375 __u8 num_klms; 376 __u8 reserved1; 377 __u16 reserved2; 378 }; 379 380 enum mlx5_ib_create_wq_mask { 381 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), 382 }; 383 384 struct mlx5_ib_create_wq { 385 __aligned_u64 buf_addr; 386 __aligned_u64 db_addr; 387 __u32 rq_wqe_count; 388 __u32 rq_wqe_shift; 389 __u32 user_index; 390 __u32 flags; 391 __u32 comp_mask; 392 __u32 single_stride_log_num_of_bytes; 393 __u32 single_wqe_log_num_of_strides; 394 __u32 two_byte_shift_en; 395 }; 396 397 struct mlx5_ib_create_ah_resp { 398 __u32 response_length; 399 __u8 dmac[ETH_ALEN]; 400 __u8 reserved[6]; 401 }; 402 403 struct mlx5_ib_burst_info { 404 __u32 max_burst_sz; 405 __u16 typical_pkt_sz; 406 __u16 reserved; 407 }; 408 409 struct mlx5_ib_modify_qp { 410 __u32 comp_mask; 411 struct mlx5_ib_burst_info burst_info; 412 __u32 reserved; 413 }; 414 415 struct mlx5_ib_modify_qp_resp { 416 __u32 response_length; 417 __u32 dctn; 418 }; 419 420 struct mlx5_ib_create_wq_resp { 421 __u32 response_length; 422 __u32 reserved; 423 }; 424 425 struct mlx5_ib_create_rwq_ind_tbl_resp { 426 __u32 response_length; 427 __u32 reserved; 428 }; 429 430 struct mlx5_ib_modify_wq { 431 __u32 comp_mask; 432 __u32 reserved; 433 }; 434 435 struct mlx5_ib_clock_info { 436 __u32 sign; 437 __u32 resv; 438 __aligned_u64 nsec; 439 __aligned_u64 cycles; 440 __aligned_u64 frac; 441 __u32 mult; 442 __u32 shift; 443 __aligned_u64 mask; 444 __aligned_u64 overflow_period; 445 }; 446 447 enum mlx5_ib_mmap_cmd { 448 MLX5_IB_MMAP_REGULAR_PAGE = 0, 449 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 450 MLX5_IB_MMAP_WC_PAGE = 2, 451 MLX5_IB_MMAP_NC_PAGE = 3, 452 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 453 MLX5_IB_MMAP_CORE_CLOCK = 5, 454 MLX5_IB_MMAP_ALLOC_WC = 6, 455 MLX5_IB_MMAP_CLOCK_INFO = 7, 456 MLX5_IB_MMAP_DEVICE_MEM = 8, 457 }; 458 459 enum { 460 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1, 461 }; 462 463 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */ 464 enum { 465 MLX5_IB_CLOCK_INFO_V1 = 0, 466 }; 467 468 struct mlx5_ib_flow_counters_desc { 469 __u32 description; 470 __u32 index; 471 }; 472 473 struct mlx5_ib_flow_counters_data { 474 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data); 475 __u32 ncounters; 476 __u32 reserved; 477 }; 478 479 struct mlx5_ib_create_flow { 480 __u32 ncounters_data; 481 __u32 reserved; 482 /* 483 * Following are counters data based on ncounters_data, each 484 * entry in the data[] should match a corresponding counter object 485 * that was pointed by a counters spec upon the flow creation 486 */ 487 struct mlx5_ib_flow_counters_data data[]; 488 }; 489 490 #endif /* MLX5_ABI_USER_H */ 491