1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef MLX5_ABI_USER_H 35 #define MLX5_ABI_USER_H 36 37 #include <linux/types.h> 38 #include <linux/if_ether.h> /* For ETH_ALEN. */ 39 40 enum { 41 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 42 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 43 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, 44 }; 45 46 enum { 47 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 48 }; 49 50 enum { 51 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 52 }; 53 54 /* Increment this value if any changes that break userspace ABI 55 * compatibility are made. 56 */ 57 #define MLX5_IB_UVERBS_ABI_VERSION 1 58 59 /* Make sure that all structs defined in this file remain laid out so 60 * that they pack the same way on 32-bit and 64-bit architectures (to 61 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 62 * In particular do not use pointer types -- pass pointers in __u64 63 * instead. 64 */ 65 66 struct mlx5_ib_alloc_ucontext_req { 67 __u32 total_num_bfregs; 68 __u32 num_low_latency_bfregs; 69 }; 70 71 enum mlx5_lib_caps { 72 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 73 }; 74 75 struct mlx5_ib_alloc_ucontext_req_v2 { 76 __u32 total_num_bfregs; 77 __u32 num_low_latency_bfregs; 78 __u32 flags; 79 __u32 comp_mask; 80 __u8 max_cqe_version; 81 __u8 reserved0; 82 __u16 reserved1; 83 __u32 reserved2; 84 __u64 lib_caps; 85 }; 86 87 enum mlx5_ib_alloc_ucontext_resp_mask { 88 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 89 }; 90 91 enum mlx5_user_cmds_supp_uhw { 92 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 93 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 94 }; 95 96 /* The eth_min_inline response value is set to off-by-one vs the FW 97 * returned value to allow user-space to deal with older kernels. 98 */ 99 enum mlx5_user_inline_mode { 100 MLX5_USER_INLINE_MODE_NA, 101 MLX5_USER_INLINE_MODE_NONE, 102 MLX5_USER_INLINE_MODE_L2, 103 MLX5_USER_INLINE_MODE_IP, 104 MLX5_USER_INLINE_MODE_TCP_UDP, 105 }; 106 107 struct mlx5_ib_alloc_ucontext_resp { 108 __u32 qp_tab_size; 109 __u32 bf_reg_size; 110 __u32 tot_bfregs; 111 __u32 cache_line_size; 112 __u16 max_sq_desc_sz; 113 __u16 max_rq_desc_sz; 114 __u32 max_send_wqebb; 115 __u32 max_recv_wr; 116 __u32 max_srq_recv_wr; 117 __u16 num_ports; 118 __u16 reserved1; 119 __u32 comp_mask; 120 __u32 response_length; 121 __u8 cqe_version; 122 __u8 cmds_supp_uhw; 123 __u8 eth_min_inline; 124 __u8 reserved2; 125 __u64 hca_core_clock_offset; 126 __u32 log_uar_size; 127 __u32 num_uars_per_page; 128 }; 129 130 struct mlx5_ib_alloc_pd_resp { 131 __u32 pdn; 132 }; 133 134 struct mlx5_ib_tso_caps { 135 __u32 max_tso; /* Maximum tso payload size in bytes */ 136 137 /* Corresponding bit will be set if qp type from 138 * 'enum ib_qp_type' is supported, e.g. 139 * supported_qpts |= 1 << IB_QPT_UD 140 */ 141 __u32 supported_qpts; 142 }; 143 144 struct mlx5_ib_rss_caps { 145 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 146 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 147 __u8 reserved[7]; 148 }; 149 150 enum mlx5_ib_cqe_comp_res_format { 151 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 152 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 153 MLX5_IB_CQE_RES_RESERVED = 1 << 2, 154 }; 155 156 struct mlx5_ib_cqe_comp_caps { 157 __u32 max_num; 158 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */ 159 }; 160 161 struct mlx5_packet_pacing_caps { 162 __u32 qp_rate_limit_min; 163 __u32 qp_rate_limit_max; /* In kpbs */ 164 165 /* Corresponding bit will be set if qp type from 166 * 'enum ib_qp_type' is supported, e.g. 167 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 168 */ 169 __u32 supported_qpts; 170 __u32 reserved; 171 }; 172 173 enum mlx5_ib_mpw_caps { 174 MPW_RESERVED = 1 << 0, 175 MLX5_IB_ALLOW_MPW = 1 << 1, 176 MLX5_IB_SUPPORT_EMPW = 1 << 2, 177 }; 178 179 enum mlx5_ib_sw_parsing_offloads { 180 MLX5_IB_SW_PARSING = 1 << 0, 181 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 182 MLX5_IB_SW_PARSING_LSO = 1 << 2, 183 }; 184 185 struct mlx5_ib_sw_parsing_caps { 186 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */ 187 188 /* Corresponding bit will be set if qp type from 189 * 'enum ib_qp_type' is supported, e.g. 190 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 191 */ 192 __u32 supported_qpts; 193 }; 194 195 struct mlx5_ib_striding_rq_caps { 196 __u32 min_single_stride_log_num_of_bytes; 197 __u32 max_single_stride_log_num_of_bytes; 198 __u32 min_single_wqe_log_num_of_strides; 199 __u32 max_single_wqe_log_num_of_strides; 200 201 /* Corresponding bit will be set if qp type from 202 * 'enum ib_qp_type' is supported, e.g. 203 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 204 */ 205 __u32 supported_qpts; 206 __u32 reserved; 207 }; 208 209 enum mlx5_ib_query_dev_resp_flags { 210 /* Support 128B CQE compression */ 211 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, 212 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, 213 }; 214 215 enum mlx5_ib_tunnel_offloads { 216 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, 217 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, 218 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2 219 }; 220 221 struct mlx5_ib_query_device_resp { 222 __u32 comp_mask; 223 __u32 response_length; 224 struct mlx5_ib_tso_caps tso_caps; 225 struct mlx5_ib_rss_caps rss_caps; 226 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 227 struct mlx5_packet_pacing_caps packet_pacing_caps; 228 __u32 mlx5_ib_support_multi_pkt_send_wqes; 229 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */ 230 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 231 struct mlx5_ib_striding_rq_caps striding_rq_caps; 232 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */ 233 __u32 reserved; 234 }; 235 236 enum mlx5_ib_create_cq_flags { 237 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 238 }; 239 240 struct mlx5_ib_create_cq { 241 __u64 buf_addr; 242 __u64 db_addr; 243 __u32 cqe_size; 244 __u8 cqe_comp_en; 245 __u8 cqe_comp_res_format; 246 __u16 flags; 247 }; 248 249 struct mlx5_ib_create_cq_resp { 250 __u32 cqn; 251 __u32 reserved; 252 }; 253 254 struct mlx5_ib_resize_cq { 255 __u64 buf_addr; 256 __u16 cqe_size; 257 __u16 reserved0; 258 __u32 reserved1; 259 }; 260 261 struct mlx5_ib_create_srq { 262 __u64 buf_addr; 263 __u64 db_addr; 264 __u32 flags; 265 __u32 reserved0; /* explicit padding (optional on i386) */ 266 __u32 uidx; 267 __u32 reserved1; 268 }; 269 270 struct mlx5_ib_create_srq_resp { 271 __u32 srqn; 272 __u32 reserved; 273 }; 274 275 struct mlx5_ib_create_qp { 276 __u64 buf_addr; 277 __u64 db_addr; 278 __u32 sq_wqe_count; 279 __u32 rq_wqe_count; 280 __u32 rq_wqe_shift; 281 __u32 flags; 282 __u32 uidx; 283 __u32 reserved0; 284 __u64 sq_buf_addr; 285 }; 286 287 /* RX Hash function flags */ 288 enum mlx5_rx_hash_function_flags { 289 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 290 }; 291 292 /* 293 * RX Hash flags, these flags allows to set which incoming packet's field should 294 * participates in RX Hash. Each flag represent certain packet's field, 295 * when the flag is set the field that is represented by the flag will 296 * participate in RX Hash calculation. 297 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 298 * and *TCP and *UDP flags can't be enabled together on the same QP. 299 */ 300 enum mlx5_rx_hash_fields { 301 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 302 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 303 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 304 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 305 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 306 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 307 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 308 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, 309 /* Save bits for future fields */ 310 MLX5_RX_HASH_INNER = 1 << 31 311 }; 312 313 struct mlx5_ib_create_qp_rss { 314 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 315 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 316 __u8 rx_key_len; /* valid only for Toeplitz */ 317 __u8 reserved[6]; 318 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 319 __u32 comp_mask; 320 __u32 flags; 321 }; 322 323 struct mlx5_ib_create_qp_resp { 324 __u32 bfreg_index; 325 }; 326 327 struct mlx5_ib_alloc_mw { 328 __u32 comp_mask; 329 __u8 num_klms; 330 __u8 reserved1; 331 __u16 reserved2; 332 }; 333 334 enum mlx5_ib_create_wq_mask { 335 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), 336 }; 337 338 struct mlx5_ib_create_wq { 339 __u64 buf_addr; 340 __u64 db_addr; 341 __u32 rq_wqe_count; 342 __u32 rq_wqe_shift; 343 __u32 user_index; 344 __u32 flags; 345 __u32 comp_mask; 346 __u32 single_stride_log_num_of_bytes; 347 __u32 single_wqe_log_num_of_strides; 348 __u32 two_byte_shift_en; 349 }; 350 351 struct mlx5_ib_create_ah_resp { 352 __u32 response_length; 353 __u8 dmac[ETH_ALEN]; 354 __u8 reserved[6]; 355 }; 356 357 struct mlx5_ib_create_wq_resp { 358 __u32 response_length; 359 __u32 reserved; 360 }; 361 362 struct mlx5_ib_create_rwq_ind_tbl_resp { 363 __u32 response_length; 364 __u32 reserved; 365 }; 366 367 struct mlx5_ib_modify_wq { 368 __u32 comp_mask; 369 __u32 reserved; 370 }; 371 #endif /* MLX5_ABI_USER_H */ 372