1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */ 2 /* 3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef MLX5_ABI_USER_H 35 #define MLX5_ABI_USER_H 36 37 #include <linux/types.h> 38 #include <linux/if_ether.h> /* For ETH_ALEN. */ 39 #include <rdma/ib_user_ioctl_verbs.h> 40 41 enum { 42 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 43 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 44 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, 45 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, 46 MLX5_QP_FLAG_TYPE_DCT = 1 << 4, 47 MLX5_QP_FLAG_TYPE_DCI = 1 << 5, 48 }; 49 50 enum { 51 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 52 }; 53 54 enum { 55 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 56 }; 57 58 /* Increment this value if any changes that break userspace ABI 59 * compatibility are made. 60 */ 61 #define MLX5_IB_UVERBS_ABI_VERSION 1 62 63 /* Make sure that all structs defined in this file remain laid out so 64 * that they pack the same way on 32-bit and 64-bit architectures (to 65 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 66 * In particular do not use pointer types -- pass pointers in __u64 67 * instead. 68 */ 69 70 struct mlx5_ib_alloc_ucontext_req { 71 __u32 total_num_bfregs; 72 __u32 num_low_latency_bfregs; 73 }; 74 75 enum mlx5_lib_caps { 76 MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0, 77 }; 78 79 struct mlx5_ib_alloc_ucontext_req_v2 { 80 __u32 total_num_bfregs; 81 __u32 num_low_latency_bfregs; 82 __u32 flags; 83 __u32 comp_mask; 84 __u8 max_cqe_version; 85 __u8 reserved0; 86 __u16 reserved1; 87 __u32 reserved2; 88 __aligned_u64 lib_caps; 89 }; 90 91 enum mlx5_ib_alloc_ucontext_resp_mask { 92 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 93 }; 94 95 enum mlx5_user_cmds_supp_uhw { 96 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 97 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 98 }; 99 100 /* The eth_min_inline response value is set to off-by-one vs the FW 101 * returned value to allow user-space to deal with older kernels. 102 */ 103 enum mlx5_user_inline_mode { 104 MLX5_USER_INLINE_MODE_NA, 105 MLX5_USER_INLINE_MODE_NONE, 106 MLX5_USER_INLINE_MODE_L2, 107 MLX5_USER_INLINE_MODE_IP, 108 MLX5_USER_INLINE_MODE_TCP_UDP, 109 }; 110 111 enum { 112 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0, 113 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1, 114 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2, 115 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3, 116 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4, 117 }; 118 119 struct mlx5_ib_alloc_ucontext_resp { 120 __u32 qp_tab_size; 121 __u32 bf_reg_size; 122 __u32 tot_bfregs; 123 __u32 cache_line_size; 124 __u16 max_sq_desc_sz; 125 __u16 max_rq_desc_sz; 126 __u32 max_send_wqebb; 127 __u32 max_recv_wr; 128 __u32 max_srq_recv_wr; 129 __u16 num_ports; 130 __u16 flow_action_flags; 131 __u32 comp_mask; 132 __u32 response_length; 133 __u8 cqe_version; 134 __u8 cmds_supp_uhw; 135 __u8 eth_min_inline; 136 __u8 clock_info_versions; 137 __aligned_u64 hca_core_clock_offset; 138 __u32 log_uar_size; 139 __u32 num_uars_per_page; 140 __u32 num_dyn_bfregs; 141 __u32 reserved3; 142 }; 143 144 struct mlx5_ib_alloc_pd_resp { 145 __u32 pdn; 146 }; 147 148 struct mlx5_ib_tso_caps { 149 __u32 max_tso; /* Maximum tso payload size in bytes */ 150 151 /* Corresponding bit will be set if qp type from 152 * 'enum ib_qp_type' is supported, e.g. 153 * supported_qpts |= 1 << IB_QPT_UD 154 */ 155 __u32 supported_qpts; 156 }; 157 158 struct mlx5_ib_rss_caps { 159 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 160 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 161 __u8 reserved[7]; 162 }; 163 164 enum mlx5_ib_cqe_comp_res_format { 165 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 166 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 167 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2, 168 }; 169 170 struct mlx5_ib_cqe_comp_caps { 171 __u32 max_num; 172 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */ 173 }; 174 175 enum mlx5_ib_packet_pacing_cap_flags { 176 MLX5_IB_PP_SUPPORT_BURST = 1 << 0, 177 }; 178 179 struct mlx5_packet_pacing_caps { 180 __u32 qp_rate_limit_min; 181 __u32 qp_rate_limit_max; /* In kpbs */ 182 183 /* Corresponding bit will be set if qp type from 184 * 'enum ib_qp_type' is supported, e.g. 185 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 186 */ 187 __u32 supported_qpts; 188 __u8 cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */ 189 __u8 reserved[3]; 190 }; 191 192 enum mlx5_ib_mpw_caps { 193 MPW_RESERVED = 1 << 0, 194 MLX5_IB_ALLOW_MPW = 1 << 1, 195 MLX5_IB_SUPPORT_EMPW = 1 << 2, 196 }; 197 198 enum mlx5_ib_sw_parsing_offloads { 199 MLX5_IB_SW_PARSING = 1 << 0, 200 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 201 MLX5_IB_SW_PARSING_LSO = 1 << 2, 202 }; 203 204 struct mlx5_ib_sw_parsing_caps { 205 __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */ 206 207 /* Corresponding bit will be set if qp type from 208 * 'enum ib_qp_type' is supported, e.g. 209 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 210 */ 211 __u32 supported_qpts; 212 }; 213 214 struct mlx5_ib_striding_rq_caps { 215 __u32 min_single_stride_log_num_of_bytes; 216 __u32 max_single_stride_log_num_of_bytes; 217 __u32 min_single_wqe_log_num_of_strides; 218 __u32 max_single_wqe_log_num_of_strides; 219 220 /* Corresponding bit will be set if qp type from 221 * 'enum ib_qp_type' is supported, e.g. 222 * supported_qpts |= 1 << IB_QPT_RAW_PACKET 223 */ 224 __u32 supported_qpts; 225 __u32 reserved; 226 }; 227 228 enum mlx5_ib_query_dev_resp_flags { 229 /* Support 128B CQE compression */ 230 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, 231 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, 232 }; 233 234 enum mlx5_ib_tunnel_offloads { 235 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, 236 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, 237 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2, 238 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3, 239 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4, 240 }; 241 242 struct mlx5_ib_query_device_resp { 243 __u32 comp_mask; 244 __u32 response_length; 245 struct mlx5_ib_tso_caps tso_caps; 246 struct mlx5_ib_rss_caps rss_caps; 247 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 248 struct mlx5_packet_pacing_caps packet_pacing_caps; 249 __u32 mlx5_ib_support_multi_pkt_send_wqes; 250 __u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */ 251 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 252 struct mlx5_ib_striding_rq_caps striding_rq_caps; 253 __u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */ 254 __u32 reserved; 255 }; 256 257 enum mlx5_ib_create_cq_flags { 258 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 259 }; 260 261 struct mlx5_ib_create_cq { 262 __aligned_u64 buf_addr; 263 __aligned_u64 db_addr; 264 __u32 cqe_size; 265 __u8 cqe_comp_en; 266 __u8 cqe_comp_res_format; 267 __u16 flags; 268 }; 269 270 struct mlx5_ib_create_cq_resp { 271 __u32 cqn; 272 __u32 reserved; 273 }; 274 275 struct mlx5_ib_resize_cq { 276 __aligned_u64 buf_addr; 277 __u16 cqe_size; 278 __u16 reserved0; 279 __u32 reserved1; 280 }; 281 282 struct mlx5_ib_create_srq { 283 __aligned_u64 buf_addr; 284 __aligned_u64 db_addr; 285 __u32 flags; 286 __u32 reserved0; /* explicit padding (optional on i386) */ 287 __u32 uidx; 288 __u32 reserved1; 289 }; 290 291 struct mlx5_ib_create_srq_resp { 292 __u32 srqn; 293 __u32 reserved; 294 }; 295 296 struct mlx5_ib_create_qp { 297 __aligned_u64 buf_addr; 298 __aligned_u64 db_addr; 299 __u32 sq_wqe_count; 300 __u32 rq_wqe_count; 301 __u32 rq_wqe_shift; 302 __u32 flags; 303 __u32 uidx; 304 __u32 bfreg_index; 305 union { 306 __aligned_u64 sq_buf_addr; 307 __aligned_u64 access_key; 308 }; 309 }; 310 311 /* RX Hash function flags */ 312 enum mlx5_rx_hash_function_flags { 313 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 314 }; 315 316 /* 317 * RX Hash flags, these flags allows to set which incoming packet's field should 318 * participates in RX Hash. Each flag represent certain packet's field, 319 * when the flag is set the field that is represented by the flag will 320 * participate in RX Hash calculation. 321 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 322 * and *TCP and *UDP flags can't be enabled together on the same QP. 323 */ 324 enum mlx5_rx_hash_fields { 325 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 326 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 327 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 328 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 329 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 330 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 331 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 332 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, 333 MLX5_RX_HASH_IPSEC_SPI = 1 << 8, 334 /* Save bits for future fields */ 335 MLX5_RX_HASH_INNER = (1UL << 31), 336 }; 337 338 struct mlx5_ib_create_qp_rss { 339 __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 340 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 341 __u8 rx_key_len; /* valid only for Toeplitz */ 342 __u8 reserved[6]; 343 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 344 __u32 comp_mask; 345 __u32 flags; 346 }; 347 348 struct mlx5_ib_create_qp_resp { 349 __u32 bfreg_index; 350 __u32 reserved; 351 }; 352 353 struct mlx5_ib_alloc_mw { 354 __u32 comp_mask; 355 __u8 num_klms; 356 __u8 reserved1; 357 __u16 reserved2; 358 }; 359 360 enum mlx5_ib_create_wq_mask { 361 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), 362 }; 363 364 struct mlx5_ib_create_wq { 365 __aligned_u64 buf_addr; 366 __aligned_u64 db_addr; 367 __u32 rq_wqe_count; 368 __u32 rq_wqe_shift; 369 __u32 user_index; 370 __u32 flags; 371 __u32 comp_mask; 372 __u32 single_stride_log_num_of_bytes; 373 __u32 single_wqe_log_num_of_strides; 374 __u32 two_byte_shift_en; 375 }; 376 377 struct mlx5_ib_create_ah_resp { 378 __u32 response_length; 379 __u8 dmac[ETH_ALEN]; 380 __u8 reserved[6]; 381 }; 382 383 struct mlx5_ib_burst_info { 384 __u32 max_burst_sz; 385 __u16 typical_pkt_sz; 386 __u16 reserved; 387 }; 388 389 struct mlx5_ib_modify_qp { 390 __u32 comp_mask; 391 struct mlx5_ib_burst_info burst_info; 392 __u32 reserved; 393 }; 394 395 struct mlx5_ib_modify_qp_resp { 396 __u32 response_length; 397 __u32 dctn; 398 }; 399 400 struct mlx5_ib_create_wq_resp { 401 __u32 response_length; 402 __u32 reserved; 403 }; 404 405 struct mlx5_ib_create_rwq_ind_tbl_resp { 406 __u32 response_length; 407 __u32 reserved; 408 }; 409 410 struct mlx5_ib_modify_wq { 411 __u32 comp_mask; 412 __u32 reserved; 413 }; 414 415 struct mlx5_ib_clock_info { 416 __u32 sign; 417 __u32 resv; 418 __aligned_u64 nsec; 419 __aligned_u64 cycles; 420 __aligned_u64 frac; 421 __u32 mult; 422 __u32 shift; 423 __aligned_u64 mask; 424 __aligned_u64 overflow_period; 425 }; 426 427 enum mlx5_ib_mmap_cmd { 428 MLX5_IB_MMAP_REGULAR_PAGE = 0, 429 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 430 MLX5_IB_MMAP_WC_PAGE = 2, 431 MLX5_IB_MMAP_NC_PAGE = 3, 432 /* 5 is chosen in order to be compatible with old versions of libmlx5 */ 433 MLX5_IB_MMAP_CORE_CLOCK = 5, 434 MLX5_IB_MMAP_ALLOC_WC = 6, 435 MLX5_IB_MMAP_CLOCK_INFO = 7, 436 MLX5_IB_MMAP_DEVICE_MEM = 8, 437 }; 438 439 enum { 440 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1, 441 }; 442 443 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */ 444 enum { 445 MLX5_IB_CLOCK_INFO_V1 = 0, 446 }; 447 448 struct mlx5_ib_flow_counters_desc { 449 __u32 description; 450 __u32 index; 451 }; 452 453 struct mlx5_ib_flow_counters_data { 454 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data); 455 __u32 ncounters; 456 __u32 reserved; 457 }; 458 459 struct mlx5_ib_create_flow { 460 __u32 ncounters_data; 461 __u32 reserved; 462 /* 463 * Following are counters data based on ncounters_data, each 464 * entry in the data[] should match a corresponding counter object 465 * that was pointed by a counters spec upon the flow creation 466 */ 467 struct mlx5_ib_flow_counters_data data[]; 468 }; 469 470 #endif /* MLX5_ABI_USER_H */ 471